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Chapter 4 Input/Output Organization. ProcessorMemory I/O device 1I/O device n Bus Figure 4.1. A...
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Transcript of Chapter 4 Input/Output Organization. ProcessorMemory I/O device 1I/O device n Bus Figure 4.1. A...
![Page 1: Chapter 4 Input/Output Organization. ProcessorMemory I/O device 1I/O device n Bus Figure 4.1. A single-bus structure.](https://reader035.fdocuments.net/reader035/viewer/2022081418/56649f425503460f94c616a6/html5/thumbnails/1.jpg)
Chapter 4
Input/Output Organization
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Processor Memory
I/O device 1 I/O device n
Bus
Figure 4.1. A single-bus structure.
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Memory-mapped I/O
• Input and output buffers use same address space as memory locations
• All instructions can access the buffers
– Move DATAIN, R0 Read from keyboard buffer– Move R0, DATAOUT Send to display buffer
– DATAIN, DATAOUT: addresses of keyboard and display buffers
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Isolated I/O
• Separate address space for I/O devices
• Special instructions (e.g., IN, OUT) that indicate that the address is not in memory address space
• Intel processors can use either
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Using the “Address Space”
• Move R0, DATAOUT
• OUT R0, DATAOUT
If memory-mapped, then DATAOUT (say address 123) refers to the display buffer, same address as a memory location
If isolated then DATAOUT (say address 123) refers to the display buffer, and memory location 123 is not used for this
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I/O
Bus
Address lines
Data lines
Control lines
Figure 4.2. I/O interface for an input device.
interfacedecoderAddress Data and
status registersControlcircuits
Input device
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KEN
SOUT
CONTROL
DATAIN
Figure 4.3. Registers in keyboard and display interfaces
DEN
DATAOUT
7
KIRQ SINSTATUS
6 5 4 3 2 1 0
DIRQ
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Move #LINE, R0 Initialize memory pointer
WAITK TestBit #0, STATUS Test SIN
Branch=0 WAITK Wait for character to be entered
Move DATAIN, R1 Read the character
WAITD TestBit #1, STATUS Test SOUT
Branch=0 WAITD Wait for the display to become ready
Move R1, DATAOUT Send the character to the display
Move R1, (R0)+ Store the character and advance the pointer
Compare #$0D, R1 Check if the character is CR
Branch=0 WAITK If not, get another character
Move #$0A, DATAOUT Otherwise, send Line Feed
Call PROCESS Call a subroutine to process the input line
Figure 4.4 A program that reads one line from the keyboard stores it in memory buffer, and echoes it back to the display.
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Interrupts
• Interrupt-request line– Interrupt-request signal– Interrupt-acknowledge signal
• Interrupt-service routine– Similar to subroutine– May have no relationship to program being executed at time
of interrupt• Program info must be saved• Interrupt latency
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Figure 4.5. Transfer of control through the use of interrupts.
here
Interruptoccurs
M
i
2
1
PRINT routine
Program 2Program 1
COMPUTE routine
i 1+
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Handling Interrupts
• Many situations where the processor should ignore interrupt requests– Interrupt-disable– Interrupt-enable
• Typical scenario– Device raises interrupt request– Processor interrupts program being executed– Processor disables interrupts and acknowledges interrupt– Interrupt-service routine executed– Interrupts enabled and program execution resumed
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Processor
INTR
R
Figure 4.6. An equivalent circuit for an open-drain bus used to implement a common interrupt-request line.
INTR1 INTR2 INTRn
Vdd
I NTR
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Processor
INTR
R
INTR1 INTR2 INTRn
Vdd
I NTR
I NTR because it is active when in the low voltage state
line voltage is high (=Vdd) when inactive
inverter (NOT gate)
INTR signal is low when interrupt line is high
pull-up resistor
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Processor
INTR
R
INTR1 INTR2 INTRn
Vdd
I NTR
I NTR because it is active when in the low voltage state
device n interrupts by closing switch, bringing line voltage down to 0
line voltage is low (0) when active
inverter
INTR signal is high when interrupt line is low
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Processor
INTR
R
Figure 4.6. An equivalent circuit for an open-drain bus used to implement a common interrupt-request line.
INTR1 INTR2 INTRn
Vdd
I NTR
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Handling Multiple Devices
• How can the processor recognize the device requesting an interrupt?
• How can the processor obtain the starting address of the appropriate interrupt-service routine?
• Should a device be allowed to interrupt the processor while another interrupt is being serviced?
• How should two or more simultaneous interrupt requests be handled?
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Interrupt Priority
• Multi-level priority organization• During execution of interrupt-service routine
– Disable interrupts from devices at the same level priority or lower
– Continue to accept interrupt requests from higher priority devices
– Privileged instructions executed in supervisor mode• Controlling device requests
– Interrupt-enable• KEN, DEN
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Priority arbitration
Device 1 Device 2 Devicep
circuit
Pro
cess
or
Figure 4.7. Implementation of interrupt priority using individual
INTA1
INTR1 I NTRp
INTAp
interrupt-request and acknowledge lines.
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Priority arbitration
Device 1 Device 2 Device p
circuit
Pro
cess
or
Figure 4.7. Implementation of interrupt priority using individual
INTA1
INTR1 I NTRp
INTAp
interrupt-request and acknowledge lines.
Priority determined by the order in which processor accepts and acknowledges interrupts
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Figure 4.8.Interrupt priority schemes.
(a) Daisy chain
Pro
cess
or
Device 2
I N T R
INTADevice nDevice 1
Daisy chaining of INTA:If device has not requested service, passes the INTA
signal to next deviceIf needs service, does not pass the INTA, puts its code
on the address lines
Polled interrupts:Priority determined by the order in which processor polls the devices (polls
their status registers)
Vectored interrupts:Priority determined by the order in which processor tells device to put its code
on the address lines (order of connection in the chain)
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(b) Arrangement of priority groups
Device Device
circuitPriority arbitration
Pro
ce
ss
or
Device Device
I N T R 1
I N T R p
INTA1
INTA p
Priority determined by the order in which processor accepts and acknowledges interrupts from a particular group
Figure 4.8.Interrupt priority schemes.
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Multiple Interrupts
• Priority in Processor Status Word– Status Register -- active program– Status Word -- inactive program
• Changed only by privileged instruction• Mode changes -- automatic or by privileged
instruction• Interrupt enable/disable, by device, system-wide
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Main Program
Move #LINE, PNTR Initialize buffer pointer
Clear EOL Clear end-of-line indicator
BitSet #2, CONTROL Enable keyboard interrupts
BitSet #9, PS Set interrupt-enable bit in the PS
… continue to process
Interrupt Service Routine
READ MoveMultiple R0-R1, -(SP) Push registers R0,R1 onto stack
Move PNTR, R0 Load memory address pointer
MoveByte DATAIN, R1 Get input character
MoveByte R1, (R0)+ Store it in memory
Move R0, PNTR Update memory pointer
CompareByte #$0D, R1 Check if Carriage Return
Branch NZ RTRN
Move #1, EOL Indicate end-of-line
BitClear #2, CONTROL Disable keyboard interrupts
RTRN MoveMultiple (SP)+, R0-R1 Pop and restore registers
Return Return from interrupt
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Main Program
Move #LINE, PNTR Initialize buffer pointer
Clear EOL Clear end-of-line indicator
BitSet #2, CONTROL Enable keyboard interrupts
BitSet #9, PS Set interrupt-enable bit in the PS
7 6 5 4 3 2 1 0
DEN KEN
CONTROL
9 8 7 6 5 4 3 2 1 0
DIRQ KIRQ
PS
IE
1
1
EOL 0 Variable: Periodically checked by program to determine when line has been read
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Interrupt Service Routine
READ MoveMultiple R0-R1, -(SP) Push registers R0,R1 onto stack
Move PNTR, R0 Load memory address pointer
MoveByte DATAIN, R1 Get input character
MoveByte R1, (R0)+ Store it in memory
Move R0, PNTR Update memory pointer
CompareByte #$0D, R1 Check if Carriage Return
Branch NZ RTRN
Move #1, EOL Indicate end-of-line
BitClear #2, CONTROL Disable keyboard interrupts
RTRN MoveMultiple (SP)+, R0-R1 Pop and restore registers
Return Return from interrupt
Invoked each time the keyboard puts a character in DATAIN and causes an interrupt
Continues until CR character encountered, then keyboard interrupts are disabled until another line is requested
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Interrupt Vectoring
Control Bus
Address Bus
Memory Location
Code
Interrupt
Address of ISR
Device
Interrupt
Service
Routine
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Common Functions of Interrupts• Interrupt transfers control to the interrupt service routine,
generally through the interrupt vector table, which contains the addresses of all the service routines.
• Interrupt architecture must save the address of the interrupted instruction and the contents of the processor status register.
• Incoming interrupts are disabled while another interrupt is being processed to prevent a lost interrupt.
• A software-generated interrupt may be caused either by an error or a user request (sometimes called a trap).
• An operating system is interrupt driven.
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Interrupts
Hardware interrupts—from I/O devices, memory, processor, etc.
Software interrupts—generated by a program.
Interrupts signal attention requests and error conditions.
Interrupts may be intrinsic or user-defined.
Other terms:
Trap
Fault
Exception
System call
IRQ
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Interrupt Handling
Address of Disk Read ISR
Address of Print ISR
Address of Disk Read Complete ISR
Address of Invalid Instruction ISR
Address of Timer ISR
Memory Location
…00
…137
…87
…32
…31
Interrupt Code
0
31
32
87
137
Interrupt Vector Table
software interrupt
hardware interrupt
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Interrupt Handling
• The operating system preserves the state of the CPU by storing registers and the program counter.
• Determines which type of interrupt has occurred:– vectored interrupt system
• Separate segments of code determine what action should be taken for each type of interrupt
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The Objectiveread data compute
write result compute
read data
write result
read data compute
write result compute
read data
write result
read data compute
write result compute
read data
write result
…
…
…
P1:
P2:
P3:
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Diagram of Process StateMultiprogramming
newprogram
readyrunning
terminated
waiting
system call
interrupt
waiting (for I/O, etc.)
admit
dispatchexit
interrupt
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Process Scheduling Queues
• Job queue – set if new programs presented to the system.
• Ready queue – set of all processes residing in main memory, ready and waiting to execute.
• Device queues – set of processes waiting for an I/O device.
• Process migration between the various queues.
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Diagram of Process StateMultiprogramming
newprogram
readyrunning
terminated
waitingJob
Queue
Job A Job B Job C
etc.
Ready Queue
Process 1 Process 6 Process 9
Process 10 etc.
Wait Queue(s)
Process 2 Process 7 Process 8
Process 11 etc.
Process 3
Process 4 Process 5
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Diagram of Process StateMultiprogramming
newprogram
readyrunning
terminated
waitingJob
Queue
Job A Job B Job C
etc.
Ready Queue
Process 1 Process 6 Process 9
Process 10 etc.
Wait Queue(s)
Process 2 Process 7 Process 8
Process 11 etc.
Process 3
admit
dispatch
interrupt (preempt)
exit
system call, I/O or event
wait
interrupt, I/O or event completed
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OSINT Set interrupt vectors:
Time-slice clock SCHEDULER
Software interrupt OSSERVICES
Keyboard interrupts IOData...
OSSERVICES Examine stack to determine requested operation
Call appropriate routine
SCHEDULER Save program state
Select a runnable process (say process B)
Restore saved context of new process
Pop new values for PS and PC from stack
Return from interrupt (resuming execution of B)
Figure 4.10(a) OS Initialization, services and scheduler
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IOINIT Set process status to Blocked (Waiting)
Initialize memory buffer address pointer and counter
Call device driver to initialize device and enable
interrupts in the device interface
Return from subroutine
IODATA Poll devices to determine source of interrupt
Call appropriate driver
If END = 1, then set process status to Runnable
Return from interrupt
Figure 4.10(b) I/O routines
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KBDINIT Enable interrupts
Return from subroutine
KBDDATA Check device status
If ready, then transfer character
If character = CR, then {set END = 1; Disable interrupts}
else set END = 0
Return from subroutine
Figure 4.10(c) Keyboard driver
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Figure 4.11. Low-order byte of the ARM processor status register.
7 6 5 4 3 2 1 0
M4 M0M1M2M3I F
CPSR: Current program status register
Mode bits: Five privileged modesInterrupt request disable
fast interrupt request disable
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ConditionCodesInterrupt
PrioritySupervisor
Trace
T S X N Z V C
012348101315
Figure 4.14. Processor status register in the 68000 processor.
mode
mode
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Figure 4.16. Part of the Pentium's processor status register.
15 14 13 12 11 10 9 8
TFIFIOPL
EFLAGS register
I/O Privilege
Level
Trace interrupt enable Flag
Interrupt enable Flag
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Direct Memory Access (DMA)
• Polling or interrupt driven I/O incurs considerable overhead– Multiple program instructions– Saving program state– Incrementing memory addresses– Keeping track of word count
• Transfer large amounts of data at high speed without continuous intervention by the processor
• Special control circuit required in the I/O device interface, called a DMA controller
• DMA controller keeps track of memory locations, transfers directly to memory (via the bus) independent of the processor
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DMA Controller
• Part of the I/O device interface– DMA Channels
• Performs functions that would normally be carried out by the processor– Provides memory address– Bus signals that control transfer– Keeps track of number of transfers
• Under control of the processor
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Direct Memory Access (DMA)• OS responds to a program’s system call for Disk
Read, for example
• OS puts the program in the “blocked” or “waiting” or “asleep” state
• Initiates the Disk Read
• Starts execution of another program
• When Read is completed, DMA controller sends an interrupt
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Done
IE
IRQ
Status and control
Starting address
W ord count
WR /
31 30 1 0
Figure 4.18. Re gisters in a DMA interf ace.Figure 4.18 Registers in a DMA interface
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Done
IE
IRQ
Status and control
Starting address
W ord count
WR /
31 30 1 0
Figure 4.18. Re gisters in a DMA interf ace.
42000
1200
1 01
Figure 4.18 Registers in a DMA interface
incremented each time a word is transferred
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Figure 4.19. Use of DMA controllers in a computer system.
memoryProcessor
Keyboard
System bus
Main
InterfaceNetwork
Disk/DMAcontroller Printer
DMAcontroller
DiskDisk
Figure 4.19. Use of DMA controllers in a computer system.
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DMA
• Processor and DMA controller(s) must “interweave” memory accesses
• DMA controllers have higher priority for obvious reason, i.e., higher speed devices need higher priority
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DMA• If DMA gets a cycle at a time, then
– CPU gets a memory cycle (uses bus)– CPU gets a memory cycle (uses bus)– CPU gets a memory cycle (uses bus)– CPU gets a memory cycle (uses bus)– DMA gets a memory cycle (uses bus)– CPU gets a memory cycle (uses bus)– CPU gets a memory cycle (uses bus)– CPU gets a memory cycle (uses bus)
processor gets most cycles
“cycle stealing”
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DMA• Or
– CPU gets a memory cycle (uses bus)– CPU gets a memory cycle (uses bus)– DMA gets a memory cycle (uses bus)– DMA gets a memory cycle (uses bus)– DMA gets a memory cycle (uses bus)– DMA gets a memory cycle (uses bus)
.
.
.– DMA gets a memory cycle (uses bus)– CPU gets a memory cycle (uses bus)
“burst mode”
to transfer a block of data without interruption
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Sharing the Bus
• Bus master: the device currently allowed to transfer data on the bus (CPU or DMA)
• Bus arbitration: choosing the next bus master
• Bus busy: BBSY set by current bus master to show that the line is in use
• Bus request: BR set when device wants to become bus master– When it gets BG (bus granted), waits for BBSY to
become inactive, then assumes mastership of the bus and sets BBSY
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Bus Arbitration
• Determination of the order in which requests for the bus are serviced– Fixed priority--each device has a priority rating– Rotating priority--devices are assigned a rotating
priority value
– Central arbitration--arbiter circuit determines– Distributed arbitration--all devices share in the
determination
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Processor
DMAcontroller
1
DMAcontroller
2BG1 BG2
BR
BBSY
Figure 4.20. A simple arrangement for bus arbitration using a daisy chain.
Centralized arbitration
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BBSY
BG1
BG2
Busmaster
BR
Processor DMA controller 2 Processor
Figure 4.21. Sequence of signals during transfer of bus mastership for the devices in Figure 4.20.
TimeDMA device 2 makes bus request ( BR)
Centralized arbitration
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BBSY
BG1
BG2
Busmaster
BR
Processor DMA controller 2 Processor
Time
Processor responds with Bus Granted ( BG), signal daisy-chained through device 1
Figure 4.21. Sequence of signals during transfer of bus mastership for the devices in Figure 4.20.
Centralized arbitration
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BBSY
BG1
BG2
Busmaster
BR
Processor DMA controller 2 Processor
Time
Processor releases bus, sets BBSY
Figure 4.21. Sequence of signals during transfer of bus mastership for the devices in Figure 4.20.
Centralized arbitration
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BBSY
BG1
BG2
Busmaster
BR
Processor DMA controller 2 Processor
Figure 4.21. Sequence of signals during transfer of bus mastership
for the devices in Figure 4.20.
TimeDMA device 2 removes bus request ( BR)
Centralized arbitration
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DMA device 2 assumes bus mastership sets BBSY
BBSY
BG1
BG2
Busmaster
BR
Processor DMA controller 2 Processor
Figure 4.21. Sequence of signals during transfer of bus mastership
for the devices in Figure 4.20.
Time
Processor turns off BG signals
Centralized arbitration
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BBSY
BG1
BG2
Busmaster
BR
Processor DMA controller 2 Processor
Figure 4.21. Sequence of signals during transfer of bus mastership
for the devices in Figure 4.20.
TimeDMA device 2 completes transfer, releases bus mastership
Processor resumes bus mastership
Centralized arbitration
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Figure 4.22. A distributed arbitration scheme.
Interface circuitfor device A
0 1 0 1 0 1 1 1
O.C.
Vcc
Start-Arbitration
ARB0
ARB1
ARB2
ARB3
puts its ID on the ARB lines
“sees” this value on the ARB lines
open collector ARB lines
Distributed arbitration
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• A transmits 0101 its ID• B transmits 0110 “
• Both “see” 0111
• Where device sees difference (between itself and ARB lines, it changes all its bits from there “down” to zero
• Thus, A changes to 0100, lines change to 0110, and B wins
• More reliable--doesn’t depend on any one device
• Highest number (device ID) = highest priority
OR’ed by theARB lines
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Synchronous Bus
• All devices clocked by a common clock line
• Signals sent or data transferred at equally spaced intervals
• Bus clock is not necessarily the same as the internal CPU clock (bus clock is slower, of course)
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Figure 4.23. Timing of an input transfer on a synchronous bus.
Bus cycle
Data
Bus clock
commandAddress and
t0 t1 t2
Time
some lines high, some low depending on bit pattern
indeterminate value
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Figure 4.23. Timing of an input transfer on a synchronous bus.
Bus cycle
Data
Bus clock
commandAddress and
t0 t1 t2
Timemaster puts address on bus, sends read signal at t0
device (slave) puts data on bus at time t1master strobes data into input buffer at time t2
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Clock cycle must be long enough to accommodate the slowest device
Bus cycle
Data
Bus clock
commandAddress and
t0 t1 t2
Time
time t2 - t1 must be longer than the maximum propagation delay and setup time for the buffer
time t1 - t0 must be longer than the maximum propagation delay between devices
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Figure 4.24. A detailed timing diagram for the input
transfer of Figure 4.23.
Data
Bus clock
commandAddress and
t0 t1t2
commandAddress and
Data
Seen by master
Seen by slave
tAM
tAS
tDS
tDM
T ime
propagation delays
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Figure 4.25 An input transfer using multiple clock cycles
1 2 3 4
Clock
Address
Command
Data
Slave-ready
Time
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Asynchronous Bus
• Use of “handshake” rather than fixed clock cycles• Timing control lines
– Master ready– Slave ready
• Master puts information on the bus, signals “ready”• Selected slave performs the requested operation,
then signals “ready”• Master removes signals and data
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Bus “Skew”
• Master puts address and read signal on the bus at time t0
• Waits (until time t1) to allow for address decoding and bus skew– (Not all lines have the same propagation speed)
• Master signals “master ready” at time t1
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Slave-ready
Data
Master-ready
and commandAddress
Bus cycle
t1
t2
t3
t4
t5
t0
Time
t2: slave device puts data on the data bus, signals slave ready
t3: master receives slave ready signal, waits (skew, setup) then takes the data and lowers the master ready
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Slave-ready
Data
Master-ready
and commandAddress
Bus cycle
t1
t2
t3
t4
t5
t0
Time
t4: master removes address and read signal
t5: device receives master ready “off” and removes data and slave ready signal from the bus
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Figure 4.27. Handshake control of data transfer during an output operation.
Bus cycle
Data
Master-ready
Slave-ready
and commandAddress
t1 t2 t3 t4 t5t0
Time
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Valid
Data
Keyboard
switches
Encoder
and
debouncing
circuit
SIN
Input
interface
Data
Address
R /
Master -ready
Slave- ready
W
DATAIN
Processor
Figure 4.28. Keyboard to processor connection.
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interface devicebus
“port”
Interface connects the device to the bus
Ports: parallel: 8 or 16 bits at a time from device
serial: 1 bit at a time from device but parallel to the bus
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Interface
• Provides storage for at least one word (or byte) of data
• Contains status flags accessible by processorbuffer full--for input device
buffer empty--for output device
• Contains address decoder
• Generates timing signals for bus control protocol
• Performs any required format conversion--e.g., serial to parallel
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determines whether, what, and when the device will be “read from”
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Address lines of system bus
A0 is used to determine whether status or data is to be read
Address decoder determines whether this device is being addressed
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Device number 2 address decoder
2 input, 1 output
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31 address lines of system bus carry device id
31 input, 1 output decoder
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A Read from the device will occur only when all four conditions are met
0 for read status, 1 for read data
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Figure 4.29 Input interface circuit
Master ready tri-state
buffers
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(b) Equivalent circuit
x f
e
(a) Symbol
x f
e = 0
e = 1x f
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Sends “Slave-ready” if either Read is detected
Puts SIN on the D0 data line if Read Status is detected
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Keyboard sends “valid” after data is ready in the buffer DATAIN
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D flip-flop
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D flip-flop
RS latch:
R S SIN
1 0 0
0 1 1
R
S
Read data tries to set SIN to 0, can’t while Master Ready (being read)
Valid sets D flip-flop to 1, changes latch, sets SIN to 1, but only if Master Ready is 0
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Sends “Slave-ready” if either Read is detected
Puts SIN on the D0 data line if Read status is detected
Puts data on the data lines if Read data is detected
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CPU SOUT
Outputinterface
Data
Address
Master-ready
Slave-ready
ValidR-W
DataDATAOUT
Figure 4.31. Printer to processor connection.
PrinterProcessor
Idle
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DATAIN
1
SIN
A31
A1
A0
D7
D0
R/ W
Figure 4.33. Combined input/output interface circuit.
A2
DATAOUT
Inputstatus
Bus
PA7
PA0
CA
PB7
PB0
CB1CB2
SOUT
D1
RS1
RS0
My-address
Slave Ready
Master Ready
Address Decoder
Handshake Control for output status
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memoryProcessor
Bridge
Processor bus
PCI bus
Main
memoryAdditional
controllercontrollerDisk
Disk 1 Disk 2
SCSIcontroller
USBcontroller
Video
Keyboard Game
diskIDE
SCSI bus
Figure 4.38. An example of a computer system using different interface standards.
ISAinterface
Ethernetinterface
CDROM
CDROM
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• Bridge: Connects buses with different characteristicsItems on PCI bus appear
as though on the system bus• PCI: Peripheral component interconnect—
processor independent• SCSI: Small Computer System Interface—SCSI controller
uses DMA approach
• USB: Universal Serial Bus• ISA: Industry Standard Architecture• EISA: 32 bit version of ISA• IDE: Integrated Device Electronics
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Figure 4.39. Use of a PCI b us in a computer system.
memory
Host
PCI bridge
EthernetPrinterDisk
interface
PCI b us
Main
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USB Interface
• Need for high transfer rates• Need devices at some distance
• High rate wide bus?– Problem over distance because of skew
• Serial transmission– Low cost and flexible– No skew, so high rates OK, distance OK
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USB Interface
• Hubs have multiple ports
• Devices connect to a port
• Hubs connect to a port
• “Tree structure”
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Host computer
Root Hub
Hub
Figure 4.43. Universal Serial Bus tree structure.
Hub
Hub
I/O device
I/O device
I/O device
I/O device
I/O device
I/O device
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USB Interface
• Message from host copied to all hubs, to all ports, to all devices
• Only the addressed device responds
• Message from device only goes “upstream”--up the tree
• Makes possible a large number of devices through a few ports at the root hub.
• High speed, long distances possible
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Host computer
Root Hub
Hub A
Device
Figure 4.44. Split bus operation
D
F / LS
HS HS
HS
HS - High speed
F / LS - Full/Low speed
Hub B
DeviceC
Message for D goes high speed to A, low speed to D
Hub A can operate in split traffic mode, alternately sending HS messages to C while sending parts of LS message to D
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USB
• Data is transmitted in packets of one or more bytes• First field is always a PID (packet id)
– A 4 bit ID plus the complement for verification– Therefore, 16 different packet types
• Control packets such as ACK are PID only• Token packets used for control• Data packets
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(a) Packet identifier field
ENDP CRC16
(b) Token packet, IN or OUT
PID CRC16
(c) Data packet
Figure 4.45. USB packet format.
PID0 PID1 PID3PID2 PID1 PID3PID0 PID2
PID ADDR
8 bits 7 bits 4 bits 5 bits
DATA
8 bits 0 to 8192 bits 16 bits
![Page 106: Chapter 4 Input/Output Organization. ProcessorMemory I/O device 1I/O device n Bus Figure 4.1. A single-bus structure.](https://reader035.fdocuments.net/reader035/viewer/2022081418/56649f425503460f94c616a6/html5/thumbnails/106.jpg)
• ADDR: The address, a 7 bit device address (address is local to the USB tree)
• ENDP: The endpoint, the location within the device (status register, data register, etc.)
• Data packet follows a token packet containing the address and endpoint of the device.
• Packet IDs contain bit that alternates between 0 and 1 to guard against lost packets
![Page 107: Chapter 4 Input/Output Organization. ProcessorMemory I/O device 1I/O device n Bus Figure 4.1. A single-bus structure.](https://reader035.fdocuments.net/reader035/viewer/2022081418/56649f425503460f94c616a6/html5/thumbnails/107.jpg)
ACK
TokenData0
TokenData1
Figure 4.46. An output transfer .
Host Hub I/O Device
TokenData0
ACK
ACK
TokenData1
ACK
Time
![Page 108: Chapter 4 Input/Output Organization. ProcessorMemory I/O device 1I/O device n Bus Figure 4.1. A single-bus structure.](https://reader035.fdocuments.net/reader035/viewer/2022081418/56649f425503460f94c616a6/html5/thumbnails/108.jpg)
USB
• Software (in host computer) sends packets to devices (hubs just forward them)
• Host software periodically polls each hub– New device when connected has address 0– If a new device has been added, host collects info
about the device from the memory of the device and assigns it a 7 bit address
• Locations within the device (registers) are identified by a 4 bit endpoint address