Chapter 4 Field-Effect Transistors

Microelectronic Circuit Design, 4E McGraw-Hill

Chap 4-1

Chapter 4Field-Effect Transistors

Microelectronic Circuit DesignRichard C. JaegerTravis N. Blalock


Chap 4-2

Chapter Goals

• Describe operation of MOSFETs.• Define FET characteristics in operation regions of cutoff, triode and

saturation.• Develop mathematical models for i-v characteristics of MOSFETs.• Introduce graphical representations for output and transfer characteristic

descriptions of electron devices.• Define and contrast characteristics of enhancement-mode and depletion-mode

FETs.• Define symbols to represent FETs in circuit schematics.• Investigate circuits that bias transistors into different operating regions.• Learn basic structure and mask layout for MOS transistors and circuits.• Explore MOS device scaling• Contrast 3 and 4 terminal device behavior.• Describe sources of capacitance in MOSFETs.• Explore FET modeling in SPICE.


Chap 4-3

4.1 MOS Capacitor Structure

• First electrode- Gate: Consists of low-resistivity material such as metal or polycrystalline silicon

• Second electrode- Substrate or Body: n- or p-type semiconductor

• Dielectric- Silicon dioxide: stable high-quality electrical insulator between gate and substrate.


Chap 4-4

Substrate Conditions for Different Biases

• Accumulation – VG << VTN

• Depletion– VG < VTN

• Inversion– VG > VTN

Accumulation Depletion

Inversion


Chap 4-5

Low-frequency C-V Characteristics for MOS Capacitor on P-type Substrate

• MOS capacitance is non-linear function of voltage.

• Total capacitance in any region dictated by the separation between capacitor plates.

• Total capacitance modeled as series combination of fixed oxide capacitance and voltage-dependent depletion layer capacitance.

Capacitors in series

• Capacitor C1 in series with Capacitor C2

• Q1 = C1 * V1

• Q2 = C2 * V2

• Totally Q = Ceq * V = Q1= Q2, V = V1 + V2

• Ceq = Q/V = Q/(V1 + V2) = Q/(Q1/C1 +Q2/C2)

• = 1/(1/C1 + 1/C2) = C1*C2/(C1 + C2)


Chap 4-6


Chap 4-7

4.2 NMOS Transistor: Structure

• 4 device terminals: Gate(G), Drain(D), Source(S) and Body(B).

• Source and drain regions form pn junctions with substrate.

• vSB, vDS and vGS always positive during normal operation.

• vSB always < vDS and vGS to reverse bias pn junctions


Chap 4-8

NMOS Transistor: Qualitative I-V Behavior• VGS <<VTN : Only small leakage

current flows.• VGS <VTN: Depletion region formed

under gate merges with source and drain depletion regions. No current flows between source and drain.

• VGS >VTN: Channel formed between source and drain. If vDS > 0,, finite iD flows from drain to source.

• iB=0 and iG=0.


Chap 4-9

NMOS Transistor: Triode Region Characteristics

iDKn vGS VTN vDS

2

vDS

where, Kn= Kn’ W/L

Kn’=nCox’’ (A/V2)

Cox’’=ox / Tox

ox= oxide permittivity (F/cm)

Tox= oxide thickness (cm)

for

vGS VTNvDS0


Chap 4-10

NMOS Transistor: Triode Region Characteristics (contd.)

• Output characteristics appear to be linear.

• FET behaves like a gate-source voltage-controlled resistor between source and drain with

RoniDvDS vDS 0

Q pt

1

1

Kn 'WL

VGS

VTN

VDS vDS 0

1Kn'WL VGS VTN


Chap 4-11

MOSFET as Voltage-Controlled Resistor

Example 1: Voltage-Controlled Attenuator

vovs Ron

RonR 11KnRVGG VTN

vovs 1

1500A

V22000

1.5 1

V0.667

To maintain triode region operation,

0.667vS(1.5 1)V or

vS0.750V

voVGG VTNor

vDSvGS VTN

If Kn= 500A/V2, VTN =1V, R = 2k and VGG =1.5V, then,


Chap 4-12

NMOS Transistor: Saturation Region

• If vDS increases above triode region limit, channel region disappears, also said to be pinched-off.

• Current saturates at constant value, independent of vDS.

• Saturation region operation mostly used for analog amplification.


Chap 4-13

NMOS Transistor: Saturation Region (contd.)

iDK'n

2

W

LvGS VTN

2 for

vDSvGS VTN

vDSAT vGS VTN is also called saturation or pinch-off voltage


Chap 4-14

Transconductance of a MOS Device

• Transconductance relates the change in drain current to a change in gate-source voltage

• Taking the derivative of the expression for the drain current in saturation region,

gmdiD

dvGS Q pt

gmKn'WL

(VGS VTN)2I

DV

GS V

TN


Chap 4-15

Channel-Length Modulation

• As vDS increases above vDSAT, length of depleted channel beyond pinch-off point, L, increases and actual L decreases.

• iD increases slightly with vDS instead of being constant.

iDKn '

2

W

LvGS VTN

2

1vDS

channel length modulation parameter


Chap 4-16

Depletion-Mode MOSFETS

• NMOS transistors with• Ion implantation process used to form a built-in n-type

channel in device to connect source and drain by a resistive channel

• Non-zero drain current for vGS = 0, negative vGS required to turn device off.

VTN0


Chap 4-17

Transfer Characteristics of MOSFETS

• Plots drain current versus gate-source voltage for a fixed drain-source voltage


Chap 4-18

Body Effect or Substrate Sensitivity

• Non-zero vSB changes threshold voltage, causing substrate sensitivity modeled by

where VTO= zero substrate bias for VTN (V)

body-effect parameter

F= surface potential parameter (V)

VTNVTO vSB2F 2F

V


Chap 4-19

NMOS Model Summary


Chap 4-20

4.3 Enhancement-Mode PMOS Transistors: Structure (11/14)

• P-type source and drain regions in n-type substrate.

• vGS < 0 required to create p-type inversion layer in channel region

• For current flow, vGS < vTP

• To maintain reverse bias on source-substrate and drain-substrate junctions, vSB < 0 and vDB < 0

• Positive bulk-source potential causes VTP to become more negative


Chap 4-21

Enhancement-Mode PMOS Transistors: Output Characteristics

• For , transistor is off.

• For more negative vGS, drain current increases in magnitude.

• PMOS is in triode region for small values of VDS and in saturation for larger values.

VGSVTP


Chap 4-22

PMOS Model Summary


Chap 4-23

4.4 MOSFET Circuit Symbols

• (g) and (i) are the most commonly used symbols in VLSI logic design.

• MOS devices are symmetric.

• In NMOS, n+ region at higher voltage is the drain.

• In PMOS p+ region at lower voltage is the drain


Chap 4-24


Chap 4-25


Chap 4-26

4.5 Internal Capacitances in Electronic Devices

• Limit high-frequency performance of the electronic device they are associated with.

• Limit switching speed of circuits in logic applications• Limit frequency at which useful amplification can be

obtained in amplifiers.• MOSFET capacitances depend on operation region and are

non-linear functions of voltages at device terminals.


Chap 4-27

NMOS Transistor Capacitances: Triode Region

Cox” = Gate-channel capacitance per unit area (F/m2).

CGC = Total gate channel capacitance.

CGS = Gate-source capacitance.

CGD = Gate-drain capacitance.

CGSO and CGDO = overlap capacitances (F/m).

CGSCGC

2 CGSOWCox"WL2 CGSOW

WGDOCWLoxCWGDOCGCCGDC 2"2


Chap 4-28

NMOS Transistor Capacitances: Triode Region (contd.)

CSB = Source-bulk capacitance.

CDB = Drain-bulk capacitance.

AS and AD = Junction bottom area capacitance of the source and drain regions.

PS and PD = Perimeter of the source and drain junction regions.

CSBCJASCJSW PS

CDBCJADCJSW PD


Chap 4-29

NMOS Transistor Capacitances: Saturation Region

• Drain no longer connected to channel

CGS23CGCCGSOW

CGDCGDOW


Chap 4-30

NMOS Transistor Capacitances: Cutoff Region

• Conducting channel region completely gone.

CGB = Gate-bulk capacitance

CGBO = gate-bulk capacitance per unit width.

CGDCGDOW

CGSCGSOW

CGBCGBOW


Chap 4-31

SPICE Model for NMOS Transistor

Typical default values used by SPICE:

Kn or Kp = 20 A/V2

= 0

= 0

VTO = 1 V

n or p = 600 cm2/V.s

2F = 0.6 V

CGDO = CGSO = CGBO = CJSW = 0

Tox= 100 nm


Chap 4-32

MOS Transistor Scaling

• Drain current:

• Gate Capacitance:

where is the circuit delay in a logic circuit.

nKLW

oxToxnL

WoxT

oxnnK

/

//

*

DiDSvDS

vTN

vGS

vL

WoxT

oxnDi

2*/

//

*

GC

CL

WoxT

oxLWoxCGCC //

/***)"(*

//

*

***

DiVGCC

DiV

GCC


Chap 4-33

MOS Transistor Scaling (contd.)

• Circuit and Power Densities:

• Power-Delay Product:

• Cutoff Frequency:

fT improves with square of channel length reduction

2***

PDiDDV

DiDDVP

AP

LWP

LWP

LWP

AP

)/)(/(

2/**

***

32***

PDPPPPDP

TNVGSVL

nGCCmg

Tf 221

21


Chap 4-34


• High Field Limitations:– High electric fields arise if technology is scaled down

with supply voltage constant.– Cause reduction in mobility of MOS transistor,

breakdown of linear relationship between mobility and electric field and carrier velocity saturation.

– Ultimately results in reduced long-term reliability and breakdown of gate oxide or pn junction.

– Drain current in saturation region is linearised to

SATvTNvGSvWoxCDi )(2

" where, vSAT is carrier saturation velocity


Chap 4-35


• Sub-threshold Conduction:– ID decreases exponentially for

VGS<VTN.

– Reciprocal of the slope in mV/decade gives the turn off rate for the MOSFET.

– VTN should be reduced if dimensions are scaled down, but curve in sub-threshold region shifts horizontally instead of scaling with VTN.


Chap 4-36

Process-defining Factors

• Minimum Feature Size, F : Width of smallest line or space that can be reliably transferred to wafer surface using given generation of lithographic manufacturing tools

• Alignment Tolerance, T: Maximum misalignment that can occur between two mask levels during fabrication


Chap 4-37

Mask Sequence for a Polysilicon-Gate Transistor

• Mask 1: Defines active area or thin oxide region of transistor

• Mask 2: Defines polysilicon gate of transistor, aligns to mask 1

• Mask 3: Delineates the contact window, aligns to mask 2.

• Mask 4: Delineates the metal pattern, aligns to mask 3.

• Channel region of transistor formed by intersection of first two mask layers. Source and Drain regions formed wherever mask 1 is not covered by mask 2


Chap 4-38

Basic Ground Rules for Layout

• F=2 • T=F/

2=could be1, 0.5, 0.25 m, etc.


Chap 4-39

MOSFET Biasing

• ‘Bias’ sets the DC operating point around which the device operates.

• The ‘signal’ is actually comprised of relatively small changes in the DC current and/or voltage bias.


Chap 4-40

Bias Analysis Approach

• Assume an operation region (generally the saturation region)

• Use circuit analysis to find VGS

• Use VGS to calculate ID, and ID to find VDS

• Check validity of operation region assumptions• Change assumptions and analyze again if required.

NOTE : An enhancement-mode device with VDS = VGS is always in saturation


Chap 4-41

Four-Resistor and Two-Resistor Biasing

• Provide excellent bias for transistors in discrete circuits.• Stabilize bias point with respect to device parameter and

temperature variations using negative feedback.• Use single voltage source to supply both gate-bias voltage

and drain current.• Generally used to bias transistors in saturation region.• Two-resistor biasing uses lesser components that four-

resistor biasing and also isolates drain and gate terminals


Chap 4-42

Bias Analysis: Example 1 (Constant Gate-Source Voltage Biasing)

Problem: Find Q-pt (ID, VDS , VGS)

Approach: Assume operation region, find Q-point, check to see if result is consistent with operation region

Assumption: Transistor is saturated, IG=IB=0

Analysis: Simplify circuit with Thevenin transformation to find VEQ and REQ for gate-bias voltage. Find VGS and then use this to find ID. With ID, we can then calculate VDS.


Chap 4-43

Bias Analysis: Example 1 (Constant Gate-Source Voltage Biasing)(contd.)

VEQIGREQVGS VGS

Since IG=0,

IDKn2

VGS VTN

2

2510 6

2AV2 3 1 2V250 A

VDDIDRDVDS

Check:VDS>VGS-VTN. Hence saturation region assumption is correct.

Q-pt: (50.0 A, 5.00 V) with VGS= 3.00 V

Discussion: The Q-point of this circuit is quite sensitive to changes in transistor characteristics, so it is not widely used.

VDS10V (50uA)(100K) 5.00 V


Chap 4-44

Bias Analysis: Example 2 (Load Line Analysis)

Problem: Find Q-pt (ID, VDS , VGS)

Approach: Find an equation for the load line. Use this to find Q-pt at intersection of load line with device characteristic.


Analysis: For circuit values above, load line becomes

VDDIDRDVDS

10ID100KVDSUse this to find two points on the load line.


Chap 4-45

Bias Analysis: Example 2 (Load Line Analysis)(contd.)

Check: The load line approach agrees with previous calculation. Q-pt: (50.0 A, 5.00 V) with VGS= 3.00 V

Discussion: Q-pt is clearly in the saturation region. Graphical load line is good visual aid to see device operating region.

@VDS=0, ID=100uA

@ID=0, VDS=10V

Plotting on device characteristic yields Q-pt at intersection with VGS = 3V device curve.

10ID100KVDS


Chap 4-46

Bias Analysis: Example 3 (Constant Gate-Source Voltage Biasing with Channel-Length Modulation)

Problem: Find Q-pt (ID, VDS , VGS) of previous example, given =0.02 V-1.



Analysis: Simplify circuit with Thevenin transformation to find VEQ and REQ for gate-bias voltage. Find VGS and then use this to find ID. With ID, we can then calculate VDS.


Chap 4-47

Bias Analysis: Example 3 (Constant Gate-Source Voltage Biasing with Channel-Length Modulation)

Check: VDS >VGS -VTN. Hence saturation region assumption is correct.

Q-pt: (54.5 A, 4.55 V) with VGS = 3.00 V

IDKn2

VGS VTN

2

1VDS

VDS VDD IDRD

VDS 10V (100K)(2510 6)2

3 1 2 10.02 VDS

4.55 V

ID(2510 6)2

3 1 2 10.02 (4.55) 54.5 A

Discussion: The bias levels have changed by about 10%. Typically, component values will vary more than this, so there is little value in including effects in most circuits.


Chap 4-48

Bias Analysis: Example 4 (Four-Resistor Biasing)

Problem: Find Q-pt (ID, VDS)


Assumption: Transistor is saturated, IG = IB = 0

Analysis: First, simplify circuit, split VDD into two equal-valued sources and apply Thevenin transformation to find VEQ and REQ for gate-bias voltage


Chap 4-49

Bias Analysis: Example 4 (Four-Resistor Biasing)

VEQVGSIDRSSince IG = 0,

VEQVGSKn2

VGS VTN

2

RS

4VGS2510 6

3.9104

2VGS 1

2

VGS20.05VGS 7.210

V66.2 ,V71.2 GSV

Since VGS<VTN for VGS= -2.71 V and MOSFET will be cut-off,

V66.2 GSV and ID= 34.4 A

Also,

VDDID(RDRS)VDS

VDS6.08V

VDS > VGS - VTN. Hence saturation region assumption is correct.

Q-pt: (34.4 A, 6.08 V) with VGS = 2.66 V


Chap 4-50

Bias Analysis: Example 5 (Four-Resistor Biasing with Body Effect)

• Estimate value of ID and use it to find VGS and VSB

• Use VSB to calculate VTN

• Find ID’ using above 2 steps

• If ID’ is not same as original ID estimate, start again.

Analysis with body effect using same assumptions as in example 1:

DISRDIEQVGSV 000,226

DISRDISBV 000,22

VTN VTO( VSB2F 2F )

VTN 10.5( VSB0.6 0.6)

ID'2510 6

2VGS VTN

2

Iterative solution can be found by following steps:


Chap 4-51

Bias Analysis: Example 5 (Four-Resistor Biasing) (contd.)

The iteration sequence leads to ID= 88.0 A, VTN = 1.41 V,

V48.6 000,4010)( DISRDRDIDDVDSV

VDS >VGS - VTN. Hence saturation region assumption is correct.

Q-pt: (88.0 A, 6.48 V)

Check: VDS > VGS - VTN, therefore still in active region.

Discussion: Body effect has decreased current by 12% and increased threshold voltage by 40%.

What if Veq = +4 V +- 1 Volt, Vds = ?An amplifier?


Chap 4-52


Chap 4-53

Bias Analysis: Example 6 (Two-Resistor Feedback Biasing)

Assumption: IG = IB = 0, transistor is saturated (since VDS= VGS)

Analysis:

VDSVDD IDRD

VGSVDD KnRD

2VGS VTN

2

VGS3.32.610 4

104

2VGS 1

2

V00.2 ,V769.0 GSV

Since VGS <VTN for VGS = -0.769 V and MOSFET will be cut-off,

VGS2.00V and ID= 130 A

VDS >VGS - VTN. Hence saturation region assumption is correct.

Q-pt: (130 A, 2.00 V)


Chap 4-54

Bias Analysis: Example 7 ( Biasing in Triode Region)

Assumption: IG = IB = 0, transistor is saturated (since VDS = VGS)

Analysis: VGS =VDD=4 V

ID2502

AV2(4 1)21.13mA

VDDID(RDRS)VDSAlso

VDS2.19V

But VDS <VGS - VTN. Hence, saturation region assumption is incorrect. Using triode region equation,

41600IDVDS

4 VDS16002502

AV2(4 1

VDS2

)VDS

VDS2.3V and ID=1.06 mA

VDS < VGS - VTN, transistor is in triode region

Q-pt: (1.06 mA, 2.3 V)


Chap 4-55

Bias Analysis: Example 8 (Two-Resistor biasing for PMOS Transistor)

Assumption: IG = IB = 0, transistor is saturated (since VDS= VGS)

Analysis:

VGS(470k)IGVDS0

Also

15V (220k)IDVDS0

15V (220k)502AV2 VGS2

2VGS0

V45.3 ,V369.0 GSV

Since VGS= -0.369 V is less than VTP= -2 V, VGS = -3.45 V

ID = 52.5 A and VGS = -3.45 V

Hence saturation assumption is correct.

Q-pt: (52.5 A, -3.45 V)

TPVGSVDSV


Junction Field-Effect Transistor (JFET) Structure

• Much lower input current and much higher input impedance than the BJT.

• In triode region, JFET is a voltage-controlled resistor,

= resistivity of channelL = channel lengthW = channel width between pn

junction depletion regionst = channel depth• Inherently a depletion-mode device

• n-type semiconductor block houses the channel region in n-channel JFET.

• Two pn junctions form the gate.• Current enters channel at the drain

and exits at source.

RCH t

LW

Chap 4-56


JFET with Gate-Source Bias

• vGS = 0, gate isolated from channel.

• VP < vGS < 0, W’ < W, and channel resistance increases; gate-source junction is reverse-biased, iG almost 0.

• vGS = VP < 0, channel region pinched-off, channel resistance is infinite.

Chap 4-57


JFET Channel with Drain-Source Bias

• With constant vGS, depletion region near drain increases with vDS.

• At vDSP = vGS - VP , channel is totally pinched-off; iD is saturated.

• JFET also suffers from channel-length modulation like MOSFET at larger values of vDS.

Chap 4-58


N-Channel JFETi-v Characteristics

Transfer Characteristics Output Characteristics

Chap 4-59


N-Channel JFETi-v Characteristics (cont.)

• For all regions :• In cutoff region: • In Triode region:

• In pinch-off region:

iG0 for vGS 0

iD0 for vGS VP VP0

iD2I

DSS

VP

2v

GS V

P

vDS

2

2

vDS for vGS VP and vGS VP VDS 0

iDIDSS 1v

GS

VP

2

1vDS

for vDS vGS VP 0

Chap 4-60


P-Channel JFET

• Polarities of n- and p-type regions of the n-channel JFET are reversed to get the p-channel JFET.

• Channel current direction and operating bias voltages are also reversed.

Chap 4-61


JFET Circuit Symbols

• JFET structures are symmetric like MOSFETs.• Source and drain determined by circuit voltages.

Chap 4-62


JFET n-Channel Model Summary

Chap 4-63


JFET p-Channel Model Summary

Chap 4-64


N-channel JFET Capacitances and SPICE Modeling

• CGD and CGS are determined by depletion-layer capacitances of reverse-biased pn junctions forming gate and are bias dependent.

• Typical default values used by SPICE: Vp = -2 V

= CGD = CGD = 0

Transconductance parameter BETA BETA = IDSS/VP

2 = 100 A/V2

Chap 4-65


Biasing JFET and Depletion-Mode MOSFET: Example

• Assumptions: JFET is pinched-off, gate-channel junction is reverse-biased, reverse leakage current of gate, IG = 0

N-channel JFET Depletion-mode MOSFET

Chap 4-66


Biasing JFET and Depletion-Mode MOSFET: Example (cont.)

• Analysis:

V1.13 ,V91.1 V5

11000A1051

V , Since2

3

2GS

GS

GS

P

GSSDSSGS

SDDS

V

VVVRIV

RIII

Since VGS = -13.1 V is less than VP= -5 V, VGS = -1.91 V and ID = IS = 1.91 mA. Also,

VDS VDD ID(RDRS)12 (1.91mA)(3k)6.27V

VDS > VGS -VP. Hence pinch-off region assumption is correct and gate-source junction is reverse-biased by 1.91V.

Q-pt: (1.91 mA, 6.27 V)

Chap 4-67


Chap 3 -68

End of Chapter 4

Chap 4-68

HW4

• 4.34• 4.79• 4.118


Chap 4-69

Coulomb’s law

• The torsion balance, also called torsion pendulum, is a scientific apparatus for measuring very weak forces, usually credited to Charles-Augustin de Coulomb, who invented it in 1777, but independently invented by John Michell sometime before 1783.

• Its most well-known uses were by Coulomb to measure the electrostatic force between charges to establish Coulomb's Law, and by Henry Cavendish in 1798 in the Cavendish experiment to measure the gravitational force between two masses to calculate the density of the Earth, leading later to a value for the gravitational constant.


Chap 4-70

• The torsion balance consists of a bar suspended from its middle by a thin fiber.

• The fiber acts as a very weak torsion spring.• If an unknown force is applied at right angles to the ends of

the bar, the bar will rotate, twisting the fiber, until it reaches an equilibrium where the twisting force or torque of the fiber balances the applied force.

• Then the magnitude of the force is proportional to the angle of the bar.

• The sensitivity of the instrument comes from the weak spring constant of the fiber, so a very weak force causes a large rotation of the bar.


Chap 4-71

• In Coulomb's experiment, the torsion balance was an insulating rod with a metal-coated ball attached to one end, suspended by a silk thread.

• The ball was charged with a known charge of static electricity, and a second charged ball of the same polarity was brought near it.

• The two charged balls repelled one another, twisting the fiber through a certain angle, which could be read from a scale on the instrument.

• By knowing how much force it took to twist the fiber through a given angle, Coulomb was able to calculate the force between the balls.

• Determining the force for different charges and different separations between the balls, he showed that it followed an inverse-square proportionality law, now known as Coulomb's law.


Chap 4-72

• To measure the unknown force, the spring constant of the torsion fiber must first be known.

• This is difficult to measure directly because of the smallness of the force.

• Cavendish accomplished this by a method widely used since: measuring the resonant vibration period of the balance.

• If the free balance is twisted and released, it will oscillate slowly clockwise and counterclockwise as a harmonic oscillator, at a frequency that depends on the moment of inertia of the beam and the elasticity of the fiber.

• Since the inertia of the beam can be found from its mass, the spring constant can be calculated.


Chap 4-73

• Coulomb first developed the theory of torsion fibers and the torsion balance in his 1785 memoir, Recherches theoriques et experimentales sur la force de torsion et sur l'elasticite des fils de metal &c.

• This led to its use in other scientific instruments, such as galvanometers, and the Nichols radiometer which measured the radiation pressure of light.

• In the early 1900s gravitational torsion balances were used in petroleum prospecting.

• Today torsion balances are still used in physics experiments.


Chap 4-74

• In 1987, gravity researcher A.H. Cook wrote:• The most important advance in experiments on gravitation

and other delicate measurements was the introduction of the torsion balance by Michell and its use by Cavendish.

• It has been the basis of all the most significant experiments on gravitation ever since.


Chap 4-75

Chapter 4 Field-Effect Transistors

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