MICROPROCESSOR INPUT/OUTPUT14.1 Introducton4.2 Smpe I/O Devces4.3 Programmed I/O4.4 Uncondtona and Condtona Programmed I/O4.5 Interrupt I/O4.6 Drect Memory Access (DMA)Summary of I/O2The technque of data transfer between a mcrocomputer and an externa devce s caed input/output (I/O).Peripherals are the I/O devces that connected to a mcrocomputer and provde an emcent means of communcaton between the mcrocomputer and the outsde word.3Because the characterstcs of I/O devces are normay dherent from those of a mcrocomputer ke (speed and word ength)we need nterface hardware crcutry betweenthe mcrocomputer and I/O devcesInterface hardware provde a nput and output transfers between the mcrocomputer and perpheras by usng an I/O bus. An I/O bus carres three types of sgnas: devce address, data, and command.4There are three ways of transferrng data between a mcrocomputer and physca I/O devces: programmed I/O, nterrupt I/Oand drect memory access.5ProgrammedI/O, the mcroprocessor executes a program to perform a data transfers between the mcrocomputer and the externa devce. The man characterstc of ths type of I/Otechnque s that the externa devce carres out the functons dctated by the programnsde the mcrocomputer memory. 6Interrupt I/O, an external device can force the microprocessor to stop executingthe current program temporary so that t can execute another program known as aninterrupt service routine. After competng ths program, a return from nterrupt nstructon can be executed at the end of the servce routne to return contro at the rght pace n the man program.7Drect memory access (DMA) s a type of I/O technque n whch data can be transferred between mcrocomputer memory and an externa devce such as the hard dsk, wthout mcroprocessor nvovement. A speca chp caed the DMA controller chip is typcay used wth the mcroprocessor for transferrng data usng DMA.8 or reading onl!9A mcrocomputer communcates wth an externa devce va one or more regsters caed I/O ports using programmed I/O. I/O ports are usuay of two types. 1. For one type, each bt n the port can be congured ndvduay as ether nput or output. 2. For the other type, a bts n the port can be set up as a parae nput or parae output bts. 10Command or data-direction register Is a regster used to congure each port as an nput or output port. "he port contains the actual input or output data. "he data direction regster s an output regster and can be used to congure the bts n the port as nputs or outputs.11As an example, f an 8-bt data-drecton regster contans 34H (34 Hex), the correspondng port s dened as shownn Fgure 4.4.12For parae I/O, there s ony one data drecton regster for a ports. A partcuar bt n the data drecton regster congures a bts n the port as ether nputs or outputs.13I/O ports are addressed usng ether standard I/O or memory-mapped I/O technques.#.$tandard I/O or port I/O (called isolated I/O %! Intel) uses an output pin such as the M / IO pn2. In memory-mapped I/O, the mcroprocessor does not use the M / IO contro pn. Instead, the mcroprocessor uses an unused address pn to dstngush between memory and I/O.1415There are typcay two ways n whch programmed I/O can be utzed: uncondtona I/O and condtona I/O. The mcroprocessor can send data to an externa devce at any tme usng unconditional I/O.In conditional I/O, the microprocessor outputs data to an externa devce va handsha&ing. "his means that data transfer occurs via the exchange of contro sgnas between the mcroprocessor and an externa devce.1617The concept of condtona I/0 w now be demonstrated by means of data transfer between a mcroprocessor and an anaog-to-dgta (A/D) converter.181920A dsadvantage of condtona programmed I/O s that the mcrocomputer needs to check the status bt (a converson compete sgna of the A/D converter) by watng n a oop.Interrupt I/O is a devce-ntated I/O transfer. The externa devce s connectedto a pn caed the nterrupt (INT) pn on the mcroprocessor chp.21How Interrupt work ??1. When the devce needs an I/O transfer wth the mcrocomputer, t actvates the nterrupt pn of the processor chp.2. The mcrocomputer usuay competes the current nstructon and saves the contents of the current program counter and the status regster n the stack.22How Interrupt work ??3. The mcrocomputer then oads an address automatcay nto the program counter to branch to a subroutne-ke program caed the interrupt service routine4. The ast nstructon of the servce routne s a RETURN, whch s typcay smar n concept to the RETURN nstructon used at the end of a subroutne.23Assume that the mcrocomputer s 68000 based and s executng the foowngnstructon sequence:24Assume that the address of service routine, s $4000 and that the user wrtes a servce routne to nput the A/D converters output as ollo!s"25There are typcay three types of nterrupts: externa nterrupts, traps or nterna nterrupts,and software nterruptsExterna nterrupts can be dvded further nto two types: maskabe and nonmaskabe. Nonmaskabe nterrupt cannot be enabed or dsabed by nstructons, whereas a mcroprocessors nstructon set contans nstructons to enabe or dsabe maskabe nterrupt26A nonmaskabe nterrupt s typcay used as a power faure nterrupt.27Internal interrupts, or traps, are actvated nternay by exceptona condtons such as overow, dvson by zero, or executon of an ega op-code. Many mcroprocessors ncude software nterrupts, or system cas. When one o these nstructons s executed, the mcroprocessor s nterrupted and servced smary to externa or nterna nterrupts.28Software interrupt nstructons are normay used to ca the operatng system.These nstructons are shorter than subroutne cas, and no cang program s needed to know the operatng systems address n memory. 29interrupt address vectorIs the technque used to nd the startng address of the servce routne30When a mcroprocessor s nterrupted, t normay saves the program counter (PC) andthe status regster (SR) onto the stack so that the mcroprocessor can return to the manprogram wth the orgna vaues of PC and SR after executng the servce routne. 31It s a speca mechansm necessary to hande nterrupts from severa devces that share one of these nterrupt nes. There are two ways of servcng mutpe nterrupts:1. Poed technque2. Dasy chan technque.32Polle# InterruptsThe mcroprocessor responds to an nterrupt by executng one genera servce routne for a devces. The prortes of devces are determned by the order n whch the routne pos each devce.33Polle# Interrupts34Polle# Interruptssevera externa devces (devce 1, devce 2,. . . , devce N) are connected to a snge nterrupt ne of a mcroprocessor va an OR gate When one or more devces actvate the INT ne HIGH, the mcroprocessor pushesthe PC and SR onto t$e stac%&The user can wrte a program at ths address to po each devce, startng wth the hghest-prorty devce, to nd the source of the nterrupt.35Polle# InterruptsSuppose that the devces n Fgure 4.10 are A/D converters.36Polle# Interrupts (exampe A/D converter)Suppose that the user assgns devce 2 the hgher prorty. 1. When the "Converson compete" sgnas from devce 1 and/or 2 become HIGH, the processor s nterrupted. 2. In response, the mcroprocessor pushes the PC and SR onto the stack and oads the PC wth the nterrupt address vector dened by the manufacturer.3. If ths devce 2 has generated an nterrupt, the output (PB 1) of the AND gate n Fgure 4.11 becomes HIGH37Polle# InterruptsPoed nterrupts are sow, and for a arge number of devces the tme requredto po each devce may exceed the tme to servce the devce. In such a case, a fastermechansm, such as the dasy chan approach, can be used.38Da's( C$a'n InterruptsDevces are connected n dasy chan fashon, as shown n Fgure 4.12, to set up prorty systems. Suppose that one or more devces nterrupt the processor. In response, the mcropro-cessor pushes the PC and SR onto the stack and, generates an nterrupt acknowedge (INTA) sgna to the hghest-prorty- devce (devce 1 n ths case). 39Da's( C$a'n InterruptsIf ths devce has generated the nterrupt, t w accept the INTA; otherwse, t w pass the INTA onto the next devce unt the INTA s accepted.Once accepted, the devce provdes a means for the processor to nd the nterrupt address vector by usng externa hardware.40Da's( C$a'n Interrupts41Da's( C$a'n Interrupts (exampe A/D Converter)42Da's( C$a'n Interrupts (exampe A/D Converter)1. When the "converson compete" sgna goes HIGH, the mcroprocessor s nterrupted through the INT ne.2. The mcroprocessor pushes the PC and SR. It then generates a LOW at the nterrupt acknowedge (INTA) for the hghest-prorty devce. Devce #1 has the hghest prorty; t s the rst devce n the dasy chan conguraton to receve INTA . 3. If A/D converter 1 has generated the "converson compete" HIGH, the output of the AND gate n Fgure 4.13 becomes HIGH.43Drect memory access (DMA) s a technque that transfers data between a mcrocomputersmemory and an I/O devce wthout nvovng the mcroprocessor.The DMA technque uses a DMA controer chp for the data transfer operatons.44DMA controller c$'p )unct'ons1. The I/O devces request DMA operaton va the DMA request ne of the controer chp.2. The controer chp actvates the mcroprocessor HOLD pn, requestng the mcroprocessor to reease the bus.3. The mcroprocessor sends HLDA (hod acknowedge) back to the DMA controer, ndcatng that the bus s dsabed. The DMA controer paces the current vaue of ts nterna regsters, on the system bus and sends a DMA acknowedge to the perphera devce. 45DMA controller c$'p T(pesThere are three basc types of DMA: 1. Bock transfer DMA2. Cyce steang DMA3. Intereaved DMA.46DMA controller c$'p T(pes *loc% transer DMAThe DMA controer chp takes over the bus from themcrocomputer to transfer data between the mcrocomputer memory and the I/O devce. The mcroprocessor has no access to the bus unt the transfer s competed.47DMA controller c$'p T(pes c(cle steal'n+ DMAData transfer between the mcrocomputer memory and an I/O devce occurs on a word-by-word bass48DMA controller c$'p T(pes c(cle steal'n+ DMAoThe mcroprocessor s generated by ANDng an INHIBIT sgna wth the system cock.o The DMA controer contros the INHIBIT ne.oDurng norma operaton, the INHIBIT ne s HIGH, provdng the mcroprocessor cock.oWhen DMA operaton s desred, the controer makes the INHIBIT ne LOW for one cock cyce. The mcroprocessor s then stopped competey for one cyce. oData transfer between the memory and I/O takes pace durng ths cyce. 49DMA controller c$'p T(pes c(cle steal'n+ DMAThs method s caed c!cle stealing %ecause the DMA controller ta&es a'a! or steals a c!cle 'ithout microprocessor recognton. Data transfer takes pace over a perod of tme.50DMA controller c$'p T(pes 'nterleave# DMA,The DMA controer chp takes over the system bus when the mcroprocessor s not usng t.The DMA controer chp dentes these cyces and aows transfer of data between memory and the I/O devce. Data transfer for ths method takes pace over a perod of tme.51DMA controller c$'p ,-o! 't !or%s.52DMA controller c$'p ,-o! 't !or%s.The DMA controer chp usuay has at east three regsters normay seected by the controer's regster seect (RS) ne: 1. An address regster, 2. A termna count regster,3. And a status regster. Both the address and termna counter regsters are ntazed by the mcroprocessor. The address regster contans the startng address of the data to betransferred, and the termna counter regster contans the bock to be transferred. Thestatus regster contans nformaton such as competon of DMA transfer. Note that theDMA controer mpements ogc assocated wth data transfer n hardware to speed up theDMA operaton.53DMA controller c$'p ,-o! 't !or%s.T$e a##ress re+'ster contans the startng address of the data to be transferred. T$e term'nal counter re+'ster contans the bock to be transferred. T$e status re+'ster contans nformaton such as competon of DMA transfer. Note that the DMA controer mpements ogc assocated wth data transfer n hardware to speed up the DMA operaton.5455