Chapter 3 Procedural Statements and Routines Topics 2014/Chap...Chapter 3 Procedural Statements and...

Chapter 3 Copyright 2012 G. Tumbush and C. Spear v1.3

Chapter 3 Procedural Statements and Routines Topics

•Procedural statement improvements •Task and function improvements •Local data storage •Time

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3.1 Procedural Statements •post increment (i++), pre increment (++i) •post decrement (i--), pre decrement (--i) •Loop enhancements

•locally defined index (for (int i=0;....) ) •continue •break

file = $fopen(“commands.txt”, “r”);

while (!$feof(file)) begin

c = $fscanf(file, “%s”, cmd);

case (cmd)

“” : continue;

“done”: break;

........

endcase

end

$fclose(file);

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Chris Spear’s file i/o web site: http://chris.spear.net/pli/fileio.htm


3.1 Procedural Statements (cont) •Verilog 1995 supported while loops •A while loop might never execute •SystemVerilog adds a do..while loop (similar to C) •A do..while loop always executes at least once •Control of the loop is tested at the end of each pass of the loop

while (count < 128) begin

$display(“Count = %d”, count);

count = count + 1;

end

do begin

$display(“Count = %d”, count);

count = count + 1;

end while (count < 128);

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3.1 Procedural Statements (cont) A case item can now be a range of values.

case (address) inside

[0:16’h1FFF]: $display(“Adddress in ROM”);

[16’h2000:16’h7FFF]: $display(“Adddress in SRAM”);

[16’h8000:16’hFFFF]: $display(“Adddress in DRAM”);

endcase

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3.2 Tasks, Functions, and Void Functions •In Verilog 2001 functions must specify a return value •System Verilog defines the void function •For functions that have no return value the return is void •Can ignore a tasks return value

function int func_2001(input integer new_int);

func_2001 = new_int;

endfunction

function void func_sv(input int new_int);

$display(“new_int = %d”, new_int);

endfunction

void’(func_2001(1));

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3.4 automatic tasks/functions • Tasks and functions without the keyword “automatic” are static

• Memory shared by all uses of tasks/functions concurrently

module auto_task();

task disp;

input integer a;

input integer d;

begin

#(d) $display("%t d is %d a is %d", $time,d,a);

end

endtask

initial

#10 disp(10,14)

initial

#14 disp(23,18);

initial

#4 disp(11,14);

endmodule

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task t3_2001();

input a, b;

output [15:0] u, v;

…

endtask

# 18 d is 18 a is 23 # 24 d is 18 a is 23 # 32 d is 18 a is 23


3.4 automatic tasks/functions • Tasks and functions with the keyword “automatic” are dynamically allocated

• Mapped to different exclusive locations on the stack

module auto_task();

task automatic disp;

input integer a;

input integer d;

begin

#(d) $display("%t d is %d a is %d", $time,d,a);

end

endtask

initial

#10 disp(10,14); // d = 14, time = 14 + 10 = 24, a = 10

initial

#14 disp(23,18); // d = 18, time = 18 + 14 = 32, a = 23

initial

#4 disp(11,14); // d = 14, time = 14 + 4 = 18, a = 11

endmodule

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task t3_2001();

input a, b;

output [15:0] u, v;

…

endtask

# 18 d is 14 a is 11 # 24 d is 14 a is 10 # 32 d is 18 a is 23


3.3 & 3.4 Routine Arguments •SystemVerilog

•begin/end not required •Argument to tasks/functions can be passed by reference.

• Not copied, a reference to original is passed and access to data is via the reference

• Arrays can be passed. • Large arrays would take too much time to copy

• Key word “const” prevents argument from being modified

function automatic void my_func(ref int func_array[1023:0]);

$display("func_array[0] = %h", func_array[0]);

endfunction

function automatic void my_func(const ref int func_array[1023:0]);

$display("func_array[0] = %h", func_array[0]);

endfunction

or

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3.4.4 Default value for Arguments •Suppose we have the following task which is called 100’s of times

•Now we want to pass in a string of what is being compared. •Use default values

task compare(input bit [7:0] expected, input logic [7:0] actual)

if (expected !== actual)

$display(“Error: Expect of %h != actual of %h”, expected, actual);

endtask

task compare(input bit [7:0] expected, input logic [7:0] actual,

input string compared = "NULL");

if (expected !== actual)

$display("Error: For %s expect of %0h != actual of %0h",

compared, expected, actual);

endtask

compare(8'h8, 8'h5);

compare(8'h8, 8'h5, "my_reg");

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# Error: For NULL expect of 8 != actual of 5

# Error: For my_reg expect of 8 != 5


3.4.5 Passing Arguments by name •Just like modules, specify task/function arguments by name instead of position. •Only pass those arguments that don’t match default

task many(input int a=1, b=2, c=3, d=4);

$display(“%0d %0d %0d %0d”, a, b, c, d);

endtask

initial begin

many(.d(6),.c(7),.b(8),.a(9));

many();

many (.c(5));

many(, 6, .d(8));

end

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# 9 8 7 6

# 1 2 3 4

# 1 2 5 4

# 1 6 3 8


Task and function Exercise

•Create a 512 location integer array •Create a 9-bit address variable to index into the array •Initialize the last location of the array to 5 •Call a task, my_task(), and pass it the array and the address •Create my_task() that takes two inputs, a constant 512-element integer array passed by reference, and a 9-bit address. The task calls a function, print_int(), and passes the array element, indexed by the address, to the function, pre-decrementing the address. •Create print_int() that prints out the simulation time and the value of the input. The function has no return value. 11


Task and function Exercise •Create a 512 location integer array

int my_array[511:0]; •Create a 9-bit address variable to index into the array

bit [8:0] addr; •Initialize the last location of the array to 5

my_array[511] = 5; •Call a task, my_task(), and pass it the array and the address

my_task(location, addr); •Create my_task() that takes two inputs, a constant 512-element integer array passed by reference, and a 9-bit address. The task calls a function, print_int(), and passes the array element, indexed by the address, to the function, pre-decrementing the address.

task automatic my_task(const ref int my_array[511:0], input bit [8:0] address); print_int(my_array[--address]); endtask // my_task

•Create print_int() that prints out the simulation time and the value of the input. The function has no return value.

function void print_int(input int input_val); $display("At %t input_val = %d", $time, input_val); endfunction // int

• // # Will print out “At 0 input_val = 5” because the address wraps from 0 to 0d511

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3.5 Returning from a Routine

•With Verilog-2001 no way to end a task/function early •SystemVerilog adds the return statement •Value returned by a function can be specified by return

task automatic my_task(ref int my_array[]);

if (my_array.size() == 0)

return;

$display("my_array = %p", my_array);

endtask

function [8:0] increment(input [8:0] address);

return ++address; // Equivalent

// increment = ++address; // Equivalent

endfunction

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3.6 Local Data Storage •With Verilog-1995 space for a task is allocated once. •All calls to a task use this single memory space. •Concurrent calls to a task will clobber each other.

int new_address1, new_address2;

initial begin

my_task(5, new_address1);

$display("new_address1 = %0d", new_address1);

end

initial begin



end

task my_task(input int address, output int new_address);

#5ns;

new_address = address;

endtask // my_task

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# new_address1 = 6

# new_address2 = 6


3.6 Local Data Storage (cont.) •With Verilog 2001 memory space can be allocated for each task call •Deallocated after each task call •Use the automatic keyword

• Default is static


initial begin



end

initial begin



end

task automatic my_task(input int address, output int

new_address);

#5ns;


endtask // my_task 15

# new_address1 = 5

# new_address2 = 6


3.6.2 Variable initialization Local variables are initialized before the start of simulation.

program initialization;

task check_bus();

repeat (5) @(posedge clock);

if (bus_cmd === READ) begin

logic [7:0] local_addr = addr<<2;

$display("Local Addr = %h", local_addr);

end

endtask

endprogram

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3.6.2 Variable initialization - solution Solution 1: Declare program as automatic

program initialization;

task check_bus();

repeat (5) @(posedge clock);

if (bus_cmd === READ) begin

logic [7:0] local_addr;

local_addr = addr<<2;

$display("Local Addr = %h", local_addr);

end

endtask

endprogram

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program automatic initialization;

...

endprogram

Solution 2: Separate variable declaration from assignment.


Local Data Storage Exercise What is displayed if my_task2 is automatic/not automatic?


bit clk;

initial begin

fork

my_task2(21, new_address1);

my_task2(20, new_address2);

join



end

initial begin forever clk=#50 !clk; end

task my_task2(input int address, output int new_address);

@(clk);


endtask

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3.7.1 Time units and Precision

•For Verilog 1995/2001 `timescale determines timescale/precision •Applies for files compiled after `timescale is encountered •SystemVerilog introduces the timeunit and timeprecision declarations

•Because these are local to a module must be declared in every module that has delay statements. •Overrides `timescale

module test;

timeunit 1ns;

timeprecision 1ps;

endmodule

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3.7.2 Time Literals • For Verilog 1995/2001 `timescale determined the units of #

• SystemVerilog allows specification of units. Units: fs ps ns us ms s

•Use the Verilog 2001 $timeformat to specify how time is displayed • Syntax:

• $timeformat(units_number, precision_number, suffix_string, minimum_field_width);

#5; // ns, ps, fs ???

timeunit 1ns; timeprecision 1ps;

initial begin

$timeformat(-9, 3, “ns”, 8);

#1 $display(“%t”, $realtime); // # 1.000ns

#2ns $display(“%t”, $realtime); // # 3.000ns

#0.1ns $display(“%t”, $realtime); // # 3.100ns

#41ps $display(“%t”, $realtime); // # 3.141ns

end

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3.7.3 Time and Variables

•Time values are scaled according to the current time unit and precision •time type is a 64-bit unsigned integer

timeunit 1ns;

timeprecision 100ps;

realtime rtdelay = 849ps;

time tdelay = 800ps;

initial begin

$timeformat(-12, 0, "ps", 5);

#rtdelay;

$display("@%0t, rtdelay = %t, %f", $realtime, rtdelay, rtdelay);

#tdelay;

$display("@%0t, tdelay = %t, %0d", $realtime, tdelay, tdelay);

end

# @800ps, rtdelay = 800ps, 0.800000

# @1800ps, tdelay = 1000ps, 1 21


3.7.4 $time vs $realtime •System task $time returns an integer scaled to the time unit •$realtime returns a real number scaled to the time precision


initial begin

$timeformat(-9, 3, “ns”, 8);

#1 $display(“%t”, $realtime);

#2ns $display(“%t”, $realtime);

#0.1ns $display(“%t”, $realtime);

#41ps $display(“%t”, $realtime);

end

initial begin

#1 $display(“%t”, $time);

#2ns $display(“%t”, $time);

#0.1ns $display(“%t”, $time);

#41ps $display(“%t”, $time);

end

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# 1.000ns

# 3.000ns

# 3.100ns

# 3.141ns

# 1.000ns

# 3.000ns

# 3.000ns

# 3.000ns


Time Exercise 1. Specify that the time should be printed in ps, 2 places to the

right of the decimal point and use as few chars as possible $timeformat(-12, 2, "ps", 0);

2. What is displayed by each of these initial blocks?


parameter real t_real = 5.5; parameter time t_time = 5ns;

initial begin

#t_time $display("1 %t", $realtime);

#t_real $display("1 %t", $realtime);

#t_time $display("1 %t", $realtime);

#t_real $display("1 %t", $realtime);

end

initial begin

#t_time $display("2 %t", $time);

#t_real $display("2 %t", $time);

#t_time $display("2 %t", $time);

#t_real $display("2 %t", $time);

end

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# 2 5000

# 2 11000

# 2 16000

# 2 21000

# 1 5000

# 1 10500

# 1 15500

# 1 21000

Backup

$display("<format>", exp1, exp2, ...); // formatted write to display format indication %b %B binary %c %C character (low 8 bits) %d %D decimal %0d for minimum width field %e %E E format floating point %15.7E %f %F F format floating point %9.7F %g %G G general format floating point %h %H hexadecimal %l %L library binding information %m %M hierarchical name, no expression %o %O octal %s %S string, 8 bits per character, 2´h00 does not print %t %T simulation time, expression is $time %u %U unformatted two value data 0 and 1 %v %V net signal strength %z %Z unformatted four value data 0, 1, x, z escape sequences, quoted characters in strings \n newline \t tab \\ backslash \" quote \ddd octal %% percent


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