Chapter 3 - Digital Logic B A. BYU CS/ECEn 124Chapter 3 - Digital Logic2 Success is not the key to...

Chapter 3 - Digital Logic

BA

BYU CS/ECEn 124 Chapter 3 - Digital Logic 2

Success is not the key to happiness.

Happiness is the key to success.

If you love what you are doing, you will be successful.


Concepts to Learn…

The Transistor Devices: Inverter, NAND, NOR, Drivers De Morgan’s Law Translations Decoders, Multiplexors, Adders, PLAs Logical Completeness Sequential Logic Latches Memory Finite State Machine


History of the Transistor

Around 1945, Bell Labs scientists discovered that silicon was comprised of two distinct regions differentiated by the way in which they favored current flow.

The area that favored positive current flow they named "p" and the area that favored negative current flow they named "n".

The Transistor


The Transistor Effect

The transistor effect describes the change from a condition of conductivity (switched “on”, full current flow) to a condition of insulation (switched “off”, no current flow).

The Transistor


Digital Logic Circuits

Computers = large number of simple structures Intel 4004 = 2,300 transistors Intel Pentium 4 = 42 million transistors Intel Core 2 Duo = 291 million transistors Intel i7 “Bloomfield” = 731 million transistors

The Transistor


Moore’s Law

Early 1900’s

1947

1950’s

Moore’s Law: The number of transistors per area doubles every 1.5 - 2 years.

1960’s

1970’s

1980’s

2000’s

1990’s

The Transistor


The MOS Transistor

A transistor acts like a switch conducts current only when "on"

gate

current flow

current flow

gate

MOS = metal-oxide semiconductorCMOS = complementary MOS with both N and P transistors

complementary

gate FET 0 off 1 on

N-type Transistor

gate FET 0 on 1 off

P-type Transistor

Off = open circuit

On = closed circuit

The Transistor


N type P type

S

D

G

S

D

G

Gate = Ground = ‘0’

Field Effect TransistorThe Transistor


N type P type

S

D

G

S

D

G

Gate = Vcc = ‘1’

Field Effect Transistor OperationThe Transistor


CMOS Gates

Pullup Structure

Pulldown Structure

Complementary

We want complementary pull-up and pull-down logic: the pull-down is “on” when the pull-up is “off”, and visa-versa.

F

The “C” in CMOS

Even in the digital world "EVERYTHING IS ANALOG"!

The Transistor


The Inverter

in

1

0

out 0

1

0

1

on

off

1

1

0

0

on

off

This is a truth-table. Ittells what the output will befor all combinations of the inputs.

Inverter Symbols

in out 0 1 1 0

Symbols are abstractions!

Digital Logic Devices


The NOR Gate (NOT-OR)

0

0

on

off off

on

1

1

0 0

0

1

off

off

on

on

0

1

0 0

NOR Symbols

a b nor0 0 10 1 01 0 01 1 0

a

b

1

0 0

nor



The OR Gate

How do you build an OR gate?

OR Symbol

a b or0 0 00 1 11 0 11 1 1

a

b

or

a

bor

0



The NAND Gate (NOT-AND)

on

off off

on

1

1

0

1 1

0

1

0

1

1 1

0

off

off

on

on

b

a

1 1

0

NAND

a b nand0 0 10 1 11 0 11 1 0 NAND Symbols



The AND Gate

How do you build an AND gate?

AND Symbol

and

a

bAND

b

a

a b AND0 0 00 1 01 0 01 1 1



Why Inverting Logic?

Why can’t we use N transistors to pull up to Vcc, and P transistors to pull down to ground?

Because N transistors do not pass good voltage levels for 1’s P transistors do not pass good voltage levels for 0’s

It just doesn’t work electronically! So… Only use P transistors in pull-up structures! Only use N transistors in pull-down structures!

??

Pullup Structure

Pulldown Structure

F



Drivers

Why can’t we use CMOS transistors to connect to a bus? P transistors to pull up to Vcc, and N transistors to pull down to ground

Because connecting Vcc to ground let’s the magic smoke out!

Solution: Tri-state driver



De Morgan’s Law

BABA

BABA

To distribute the bar, change the

operation.

NOR Symbols

NAND Symbols

De Morgan’s Law


De Morgan’s ProofDe Morgan’s Law

A B A + B A + B A B A B

0 0

0

0

1

1

1 1

0

1

1

1

1

0

0

0

1

0

0

0

1

1

0

0

1

0

1

0


Reading Functions from Symbols

The output will be low if all of the inputs are high...

The output will be high if any of the inputs are low...

a b out0 0 10 1 11 0 11 1 0

It’s just a NAND gatedrawn a different way!!!

The output will be high if the first input is low OR

the second input is high...

Translations


You Should Know How to Translate

LogicEquations

LogicGates

TruthTables

These are three different ways of

representing logical information

You can convert any one of them to any

other

Translations


From Equations to Gates

y = NOT(s) AND a AND NOT(b)

b

a

s y

s

a

b

y

Translations


From Equations to Gates

out

b

a

s

b

a

s

b

a

s

b

a

s

y = (~s a ~b)

+ (~s a b)

+ (s ~a b)

+ (s a b)

Translations


From Truth tables to Gates

Each row of truth table is an AND gate Each output column is an OR gate

s a b out0 0 0 00 0 1 00 1 0 10 1 1 11 0 0 01 0 1 11 1 0 01 1 1 1

out

When we write s we meanthe inverse of s or s after it hasgone through an inverter.

sab

sab

sab

sab

Translations


bas OR sabOR basOR abs

From Truth table to Equations

Write out truth table a combination of AND’s and OR’s equivalent to gates easily converted to gates

s a b out0 0 0 00 0 1 00 1 0 10 1 1 11 0 0 01 0 1 11 1 0 01 1 1 1

out =

Translations


as

Contains a don’t care - out is independent of b

There is a whole field of boolean minimization thatcapitalizes on this property.

You will learn this in the next class...

sbOR

sabbas OR

abs OR

bas OR

From Equations to Truth Tables

For each AND term fill in the proper row on the truth table

s a b out0 0 0 00 0 1 00 1 0 10 1 1 11 0 0 01 0 1 11 1 0 01 1 1 1

s a b out0 0 0 00 0 1 00 1 0 10 1 1 11 0 0 01 0 1 11 1 0 01 1 1 1

sabbasabsbasout sbasout

out

out

Translations


Laws (basic identities) of Boolean algebra.

Law OR ANDIdentity x 0 = x x 1 = x

One/Zero x 1 = 1 x 0 = 0

Idempotent x x = x x x = x

Inverse x x = 1 x x = 0

Commutative x y = y x x y = y x

Associative (x y) z = x (y z) (x y) z = x (y z)

Distributive x (y z) = (x y) (x z) x (y z) = (x y) (x z)

DeMorgan’s (x y) = xy (x y) = x y

Manipulating Logic ExpressionsTranslations

Some Special Function Blocks


Decoders

Decode the input and signify its value by raising just one of its outputs.

2-to-4Decoder

A B

W

X

Y

Z

DECODERSymbol

1 if A,B = 00

1 if A,B = 01

1 if A,B = 10

1 if A,B = 11

W

X

Y

Z

A

B

Circuits


Decoders

Write the truth table

A B W X Y Z0 0 0 1 1 0 1 1

1 0 0 00 1 0 00 0 1 00 0 0 1

W

X

Y

Z

A

B

Circuits


Multiplexors

Connect one of its inputs to its output according to select signals

Useful for selecting one from a collection of data inputs.

Usually has 2n inputs and n select lines.


A B

S

C

0 1

MULTIPLEXOR Symbol

A B

S

C

Circuits


Multiplexors

Write the truth table

A simpler way…A B S C0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 11 0 1 01 1 0 11 1 1 1

A B S C0 X 0 01 X 0 1X 0 1 0X 1 1 1

A B

C

S0 1

Circuits


Adders

At each digit position add together the 2 operands and the carry-in

FullAdder

a0b0

s0

c0Full

Adder

a1b1

s1

c1Full

Adder

a2b2

s2

c2Full

Adder

a3b3

s3

c3‘0’

Just like longhand additionexcept it’s in binary...

c 0110+0101 1011

Circuits


Full Adder Module Design

a b c cyout sum0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

cba

abccbacbacbasum

abccabcbabcacyout

Circuits


Programmable Logic Arrays

Programmable Logic Array (PLA) can be used to implement any logic function

Take truth table of any logic function Convert into equation (any truth table can be expressed as set

of “and” expressions “or”ed together) PLA programmed by making/breaking wire connections

?

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?

?

?

??

?

??

?

??

?

?

?

?

?

?

?

?

?

?

?

?

?

Inputs:

Outputs:

PLAs


PLA Example

A B C Out1 Out2 Out30 0 0 0 1 10 0 1 1 0 00 1 0 0 1 00 1 1 0 0 01 0 0 1 0 01 0 1 0 1 01 1 0 0 0 01 1 1 1 0 1

Out1 = ABC + ABC + ABCOut2 = ABC + ABC + ABCOut3 = ABC + ABC

Inputs

Outputs

?

?

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?

?

?

?

?

?

?

?

?

?

?

?

?

?

?

?

?

?

?

?

?

?

?

?

ABC

Out1

Out2

Out3

PLAs


Logical Completeness

What is the minimum set of gate types needed to implement any logic function?

AND gate, OR gate, INVERTER

BABABABA DeMorgan’s Theorem

AND gate, INVERTER OR can be replaced by an AND and three INVERTERS

BABABABA DeMorgan’s Theorem

OR gate, INVERTER AND can be replaced by an OR and three INVERTERS




NAND

INVERTER

AND

OR

NAND (by itself) is logically complete if you can implement an INVERTER, AND, and OR gate using only NAND gates.



Combinational vs. Sequential

Two types of “combination” locks

4 1 8 4

CombinationalSuccess depends only onthe values, not the order in which they are set.

30

15

5

1020

25

SequentialSuccess depends onthe sequence of values(e.g, R-13, L-22, R-3).

Sequential Logic


Storage Elements

Everything so far is called combinational the output is strictly a function of the current

inputs Real computing systems need storage

for holding previously computed values for remembering its place (state) in the middle

of a multi-step operation Storage elements remember what was

stored in them for later retrieval using feedback

Sequential Logic


Bi-Stability = Key to Memory

1 00

This is a stable state –it will sit like this forever

0 11

This is also a stable state –it will sit like this forever

When there are 2 stable states - a bi-stable circuit…

Sequential Logic


Signals s and r are active low they change the circuit when they go low

Output q goes high when s goes low Output q goes low when r goes low Output q remains the same otherwise

s

r

q

q

RS Latch

q

q

s

r

same

q

q

s

r

same

Cross-coupled NAND gates

Note the feedback

Sequential Logic


RS Latch – Bi-Stable Circuit

q

q

s

r

q

q

s

r

11

10

10

11

This is a stable state –it will sit like this forever

This is also a stable state –it will sit like this forever

Sequential Logic


RS Latch (continued)

1

1

0

1

q

q

s

r

0

1

1

0

1

1

1

0

1

0

0

1

1

1

0

1

Sequential Logic


RS Latch : Next State Table

Defines output as a function of inputs (s and r) and current output (q, its state)

s r q qnext0 0 0 x0 0 1 x0 1 0 10 1 1 11 0 0 01 0 1 01 1 0 q1 1 1 q

not allowed

set

reset

keep old state

Sequential Logic


Gated D Latch

Output q gets value from input d only when we is high we stands for write enable, think of it as a load signal

s

r

q

q

d

we

LATCH Symbol

WE

D QD-Latch


Latch


Quiz

1. What is a bi-stable circuit?

2. Draw a logic circuit (using N and P type transistors) for a 3 input NAND gate.

3. With a RS NAND latch, why can’t R and S be low at the same time?

4. How is Q set with the following latch?


Quiz (Answers)

1. What is a bi-stable circuit? When the circuit has 2 stable states

2. Draw a logic circuit (using N and P type transistors) for a 3 input NAND gate.


Quiz (Answers)

3. With a RS NAND latch, why can’t R and S be low at the same time? This state would force both outputs to a logic

1, overriding the feedback latching action. Outputs Q and Q' must have opposite logic

levels. Results in a “race” condition – final state of

the latch cannot be determined.


Quiz (Answers)

4. How is Q set with the following latch? Q is set by changing input S from a logic 0 to

a logic 1

0

0

1

01

0


Register

A computer register is a place to store a collection of bits

Very fast memory Numbered right to left (LSB on the right)

D-Latch

d0

q0

D-Latch

d1

q1

D-Latch

d2

q2

D-Latch

d3

q3

we

REGISTER Symbol

Register

d

q

we

Latch


Memory

A collection of addressable locations Address selects which location to read from

or write to

Memory

address

q

n

we

dm m

A memory with n address wires has 2n locations.

The number of data wires in equal the number of data wires out.

Memory is changed with we is asserted.

q always reflects the contents stored at the addressed memory location.

Memory can be viewed as a large collection of slower registers.

Memory


Memory Usage

addr value000 1001001 0000010 1111011 1011100 0000101 0011110 1010111 0101

Power-Up State(random bits)

addr => 101data => 0000we => 1

addr value000 1001001 0000010 1111011 1011100 0000101 0000110 1010111 0101

addr => 101data => 0000we => 0

addr value000 1001001 0000010 1111011 1011100 0000101 0000110 1010111 0101

addr => 111data => 1100we => 1

addr value000 1001001 0000010 1111011 1011100 0000101 0000110 1010111 1100

addr => 000data => 0000we => 1

addr value000 0000001 0000010 1111011 1011100 0000101 0000110 1010111 1100

addr => 000data => 0110we => 1

addr value000 0110001 0000010 1111011 1011100 0000101 0000110 1010111 1100

addr => 110data => 0110we => 0

addr value000 0110001 0000010 1111011 1011100 0000101 0000110 1010111 1100

Memory


Building a Memory From Latches

2-to-4Decoder

a1 a0

00

01

10

11

Register

Register

Register

Register

we

we

we

we

writeEnable d input

q output

This is a functional view.The key parts are: address decoder memory cells (registers) output selector (mux)

Memory

address

q

n

we

dm m

MEMORY Symbol

n = 2address

q0

q1

q2

q3

Memory


Address Space

When we say a computer has a 4GB (giga-byte) address space we mean it has enough address lines to address 232

address locations Kilobyte = 210 or 10241 bytes Megabyte= 220 or 10242 bytes Gigabyte = 230 or 10243 bytes Tera-byte = 240 or 10244 bytes Peta-byte = 250 or 10245 bytes

Memory


The MSP430You may not know how it works, but you know the parts its made from!

Memory

Program Counter Status Register

Lots of GatesInstruction Register

Multiplexor

Arithmetic Logic Unit

Register

16 16-bitRegisters

MemoryMapped I/O

Bus Driver

Finite State Machine

START HERE



Sequential State Machine

Another type of sequential circuit Combines combinational logic with storage “Remembers” state, and changes output (and state)

based on inputs and current state

State Machine

CombinationalLogic Circuit

StorageElements

Inputs Outputs



State of a System

The state of a system is a snapshot of all the relevant elements of the system at the moment the snapshot is taken.

Examples: The state of a basketball game can be represented by

the scoreboard (ie. number of points, time remaining, possession, etc.)

The state of a tic-tac-toe game can be represented by the placement of X’s and O’s on the board.



Combinational vs. Sequential

Two types of “combination” locks

4 1 8 4

30

15

5

1020

25

CombinationalSuccess depends only onthe values, not the order in which they are set.

SequentialSuccess depends onthe sequence of values(e.g, R-13, L-22, R-3).



State of Sequential Lock

Our lock example has four different states, labeled A-D:

A: The lock is not open, and no relevant operations have been performed.

B: The lock is not open, and the user has completed the R-13 operation.

C: The lock is not open, and the user has completed R-13, followed by L-22.

D: The lock is open.



State Diagram

Shows states and actions that cause a transition between states.

Open = 0

Open = 0

Open = 0Open = 1




A description of a system with the following components:

A finite number of states A finite number of external inputs A finite number of external outputs An explicit specification of all state transitions An explicit specification of what determines each

external output value

Often described by a state diagram. Inputs trigger state transitions. Outputs are associated with each state (or with each

transition).



The Clock

Frequently, a clock circuit triggers transition fromone state to the next.

At the beginning of each clock cycle, state machine makes a transition, based on the current state and the external (or internal) inputs.

“1”

“0”

timeOneCycle



FSM Implementation

Combinational logic Determine outputs and next state.

Storage elements Maintains state representation.

State Machine

CombinationalLogic Circuit

StorageElements

Inputs Outputs

Clock



Storage: Master-Slave Flipflop

A pair of gated D-latches isolates next state from current state.

During 1st phase (clock=1),previously-computed statebecomes current state and issent to the logic circuit.

During 2nd phase (clock=0),next state, computed bylogic circuit, is stored inLatch A.





“1”

“0”

time

HOLDSET/RESET




“1”

“0”

time

HOLD SET/RESET

Another view


Combinational Logic

Combinational Logic

MasterSlave

Input

LOW

Another view


Combinational Logic

Combinational Logic

MasterMasterSlave

Input

LOW

Another view


Combinational Logic

Combinational Logic

MasterMasterSlave

Input

HIGH

Another view


Combinational Logic

Combinational Logic

MasterMasterSlaveSlave

Input

HIGH

Another view


Combinational Logic


Input

HIGH

Another view


Combinational Logic


Input

LOW

Another view


Combinational Logic

MasterSlaveSlave

Input

LOW


Storage Elements

Each master-slave flip flop stores one state bit. The number of storage elements (flip flops) needed is

determined by the number of states (and the representation of each state).

Examples: Sequential lock

4 states – 2 bits Basketball scoreboard

7 bits for each score, 5 bits for minutes, 6 bits for seconds, 1 bit for possession arrow, 1 bit for half, …

Blinking traffic sign 4 states – 2 bits



A blinking traffic sign No lights on 1 & 2 on 1, 2, 3, & 4 on 1, 2, 3, 4, & 5 on

Repeat as long as switchis turned on

DANGERMOVERIGHT

1

2

3

4

5

Finite State Machine ExampleFinite State Machine


Traffic Sign State Diagram

State bit S1 State bit S0

Switch onSwitch off

Outputs

Transition on each clock cycle.



Traffic Sign Truth Tables

Outputs(depend only on state: S1S0)

S1 S0 Z Y X

0 0 0 0 0

0 1 1 0 0

1 0 1 1 0

1 1 1 1 1

Lights 1 and 2

Lights 3 and 4

Light 5

Next State: S1'S0'(depend on state and input)

In S1 S0 S1' S0'

0 X X 0 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 1

1 1 1 0 0

Switch

Whenever In=0, next state is 00.



Traffic Sign LogicFinite State Machine


From Logic to Data Path

The data path of a computer is all the logic used toprocess information. See the data path of the LC-3 on next slide.

Combinational Logic Decoders -- convert instructions into control signals Multiplexers -- select inputs and outputs ALU (Arithmetic and Logic Unit) -- operations on data

Sequential Logic State machine -- coordinate control signals and data

movement Registers and latches -- storage elements


STOP HERE



MSP430 Finite State Machine

DECODE:NOCLK:MOV||EVSRCEVDST:CLK1:MOV,Rd|D,ROX=Rd|STOREEVSRC:CLK1:MOV,Rs|S,ROX=Rs|EVDSTSTORE:CLK1:MOV,Rd|ALU,RWE,RIX=Rd|FETCH...


Review…


Signals, Logic Operators, Gates

x y

AND Name XOR OR NOT

Graphical symbol

x y

Operator sign and alternate(s)

x y x y xy

x y

x x or x

_

x y or xy Arithmetic expression

x y 2xy x y xy 1 x

Output is 1 iff: Input is 0

Both inputs are 1s

At least one input is 1

Inputs are not equal


Variations in Gate Symbols

Gates with more than two inputs and/or with inverted signals at input or output.

OR NOR NAND AND XNOR


Gates as Control Elements

An AND gate and a tristate buffer act as controlled switches or valves. An inverting buffer is logically the same as a NOT gate.

Enable/Pass signal e

Data in x

Data out x or 0

Data in x

Enable/Pass signal e

Data out x or “high impedance”

(a) AND gate for controlled transfer (b) Tristate buffer

(c) Model for AND switch.

x

e

No data or x

0

1 x

e

ex

0

1 0

(d) Model for tristate buffer.


Wired OR and Bus Connections

Wired OR allows tying together of several controlled signals.

e

e

e Data out (x, y, z, or high

impedance)

(b) Wired OR of t ristate outputs

e

e

e

Data out (x, y, z, or 0)

(a) Wired OR of product terms

z

x

y

z

x

y

z

x

y

z

x

y


Boolean Functions / Expressions

Ways of specifying a logic function

Truth table: 2n row, “don’t-care” in input or output

Logic expression: w (x y z), product-of-sums, sum-of-products, equivalent expressions

Word statement: Alarm will sound if the door is opened while the security system is engaged, or when the smoke detector is triggered

Logic circuit diagram: Synthesis vs analysis


Laws (basic identities) of Boolean algebra.

Name of law OR version AND versionIdentity x 0 = x x 1 = x

One/Zero x 1 = 1 x 0 = 0

Idempotent x x = x x x = x

Inverse x x = 1 x x = 0

Commutative x y = y x x y = y x

Associative (x y) z = x (y z) (x y) z = x (y z)

Distributive x (y z) = (x y) (x z) x (y z) = (x y) (x z)

DeMorgan’s (x y) = x y (x y) = x y

Manipulating Logic Expressions


Designing Gate Networks

AND-OR, NAND-NAND, OR-AND, NOR-NOR

Logic optimization: cost, speed, power dissipation

(a) AND-OR circuit

z

x y

x

y z

(b) Intermediate circuit

(c) NAND-NAND equivalent

z

x y

x

y z z

x y

x

y z

A two-level AND-OR circuit and two equivalent circuits.


BCD-to-Seven-Segment Decoder

The logic circuit that generates the enable signal for the lowermost segment (number 3) in a seven-segment display unit.

x 3 x 2 x 1 x 0

Signals to enable or turn on the segments

4-bit input in [0, 9] e 0

e 5

e 6

e 4

e 2

e 1

e 3

1

2 4

5

0

3

6


Useful Combinational Parts

High-level building blocks

Much like prefab parts used in building a house

Arithmetic components will be covered in Part III (adders, multipliers, ALUs)

Here we cover three useful parts: multiplexers, decoders/demultiplexers, encoders


Multiplexers

Multiplexer (mux), or selector, allows one of several inputs to be selected and routed to output depending on the binary value of a set of

selection or address signals provided to it.

x

x

y

z

1

0

x

x

z

y

x x

y

z

1

0

y

/ 32

/ 32

/ 32 1

0

1

0

3

2

z

y 1 0

1

0

1

0

y 1

y 0

y 0

(a) 2-to-1 mux (b) Switch view (c) Mux symbol

(d) Mux array (e) 4-to-1 mux with enable (e) 4-to-1 mux design

0

1

y

1 1

1

0

0 0

x x x x

1 0

2

3

x

x

x

x

0

1

2

3

z

e (Enable)


Decoders/Demultiplexers

A decoder allows the selection of one of 2a options using an a-bit address as input. A demultiplexer (demux) is a decoder that only

selects an output if its enable signal is asserted.

y 1 y 0

x 0

x 3

x 2

x 1

1

0

3

2

y 1 y 0

x 0

x 3

x 2

x 1 e

1

0

3

2

y 1 y 0

x 0

x 3

x 2

x 1

(a) 2-to-4 decoder (b) Decoder symbol (c) Demultiplexer, or decoder with “enable”

(Enable)


Encoders

A 2a-to-a encoder outputs an a-bit binary number equal to the

index of the single 1 among its 2a inputs.

(a) 4-to-2 encoder (b) Encoder symbol

x 0

x 3

x 2

x 1

y 1 y 0

1

0

3

2

x 0

x 3

x 2

x 1

y 1 y 0


Programmable Combinational Parts

Programmable ROM (PROM)

Programmable array logic (PAL)

Programmable logic array (PLA)

A programmable combinational part can do the job of many gates or gate networks

Programmed by cutting existing connections (fuses) or establishing new connections (antifuses)


PROMs

Programmable connections and their use in a PROM.

. . .

.

.

.

Inputs

Outputs

(a) Programmable OR gates

w

x

y

z

(b) Logic equivalent of part a

w

x

y

z

(c) Programmable read-only memory (PROM)

De

cod

er


PALs and PLAs

Programmable combinational logic: general structure and two classes known as PAL and PLA devices. Not shown is PROM with fixed AND

array (a decoder) and programmable OR array.

AND array (AND plane)

OR array (OR

plane)

. . .

. . .

.

.

.

Inputs

Outputs

(a) General programmable combinational logic

(b) PAL: programmable AND array, fixed OR array

8-input ANDs

(c) PLA: programmable AND and OR arrays

6-input ANDs

4-input ORs


Latches, Flip-Flops, and Registers

Latches, flip-flops, and registers.

R Q

Q S

D

Q

Q C

Q

Q

D

C

(a) SR latch (b) D latch

Q

C

Q

D

Q

C

Q

D

(e) k -bit register (d) D flip-flop symbol (c) Master-slave D flip-flop

Q

C

Q

D FF

/

/

k

k

Q

C

Q

D FF

R

S


Latches vs Flip-Flops

Operations of D latch and negative-edge-triggered D flip-flop.

D

C

D latch: Q

D FF: Q

Setup time

Setup time

Hold time

Hold time


R/W FFs in the Same Cycle

Register-to-register operation with edge-triggered flip-flops.

/

/

k

k

Q

C

Q

D FF

/

/

k

k

Q

C

Q

D FF

Computation module (combinational logic)

Clock Propagation delay


Finite-State Machines

State table and state diagram for a vending machine coin reception unit.

Dime Dime Quarter

Dime

Quarter

Dime Quarter

Dime Quarter

Reset Reset

Reset

Reset

Reset

Start Quarter

S 00

S 10

S 20

S 25

S 30

S 35

S 10 S 25 S 00

S 00

S 00

S 00

S 00

S 00

S 20 S 35

S 35 S 35

S 35 S 35

S 35 S 30

S 35 S 35

------- Input ------- D

ime

Qua

rter

Res

et

Current state

S 00 S 35

is the initial state is the final state

Next state

Dime Quarter

S 00

S 10 S 20

S 25

S 30 S 35


Register File and FIFO

Register file with random access and FIFO.

Dec

oder

/ k

/ k

/

h

Write enable

Read address 0

Read address 1

Read data 0

Write data

Read enable

2 k -bit registers h / k

/ k

/ k

/ k

/ k

/ k

/ k

/ h

Write address

Muxes

Read data 1

/

k

/

h

/

h /

h

/

k /

h

Write enable

Read addr 0

/

k

/

k

Read addr 1

Write data Write addr

Read data 0

Read enable

Read data 1

(a) Register file with random access

(b) Graphic symbol for register file

Q C

Q

D

FF

/ k

Q C

Q

D

FF

Q C

Q

D

FF

Q C

Q

D

FF

/

k

Push

/

k

Input

Output Pop

Full

Empty

(c) FIFO symbol


SRAM

SRAM memory is simply a large, single-port register file.

Column mux

Row

dec

ode

r

/ h

Address

Square or almost square memory matrix

Row buffer

Row

Column

g bits data out

/

g /

h

Write enable

/

g

Data in

Address

Data out

Output enable

Chip select

.

.

.

. . .

. . .

(a) SRAM block diagram (b) SRAM read mechanism


Programmable Sequential Parts

Programmable array logic (PAL)

Field-programmable gate array (FPGA)

Both types contain macrocells and interconnects

A programmable sequential part contain gates and memory elements

Programmed by cutting existing connections (fuses) or establishing new connections (antifuses)


From Components to Applications

Subfields or views in computer system engineering.

High-level view

Com

put

er d

esig

ner

Circ

uit

desi

gne

r

App

licat

ion

des

igne

r

Sys

tem

des

igne

r

Log

ic d

esig

ner

Software

Hardware

Computer organization

Low-level view

App

licat

ion

dom

ains

Ele

ctro

nic

com

pon

ents

Computer architecture


High- vs Low-Level Programming

Swap v[i]and v[i+1]

Very high-level languageobjectivesor tasks

More concrete, machine-dependent; error-prone, harder to write, read, debug, maintain

More abstract, machine-independent;easier to write, read, debug, maintain

Inte

rpre

ter

temp=v[i];v[i]=v[i+1];v[i+1]=temp;

High-levellanguagestatements

One task =Many instructions

Com

pile

r

MOV.B 0x0001(SP),R14MOV.W SP,R15INCD.W R15ADD.W R15,R14MOV.B @R14,0x0000(SP)MOV.B 0x0001(SP),R14INC.W R14MOV.W SP,R15INCD.W R15ADD.W R15,R14MOV.B 0x0001(SP),R13MOV.W SP,R15INCD.W R15ADD.W R15,R13MOV.B @R14,0x0000(R13)MOV.B 0x0001(SP),R15INC.W R15MOV.W SP,R14INCD.W R14ADD.W R15,R14MOV.B @SP,0x0000(R14)

Assemblylanguageinstruction,mnemonic

One statement =Several instructions

Ass

em

ble

r

415E 0001410F532F5F0E4EE1 0000415E 0001531E410F532F5F0E415D 0001410F532F5F0D4EED 0000415F 0001531F410E532E5F0E41EE 0000

Machinelanguageinstructionsbinary (hex)

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Chapter 3 - Digital Logic B A. BYU CS/ECEn 124Chapter 3 - Digital Logic2 Success is not the key to...

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