MICROPROCESSORMEMORY ORGANIZATION13.1 Introduction3.2 Main memory3.3 Microprocessor on-chip memory management unit and cache2A memory unit is an integral part of any microcomputer, and its primary purpose is to hold instructions and data.Memory system can be divided into three groups:1. Microprocessor memory2. Primary or main memory3. econdary memory3Microprocessor memory is a set of microprocessor registers, used to hold temporary resultsMain memory is the storage area in !hich all programs are e"ecuted, include #$M % #&Mecondary memory '(lectromechanical memory )devices such as hard dis*s, also called virtual memory.+he microcomputer cannot e"ecute programs stored in the secondary memory directly, so to e"ecute these programs the microcomputer must transfer them to its main memory by a program called the operating system.,Microprocessor memorymain memory Secondary memory+he fastest +he slo!er +he slo!est+he smallest +he -argest +he larger./-bit microprocessors:+he memory is divided into a number of /-bit units called memory words. An 8-bit unit of data is termed a byte. Therefore, for an 8-bit microprocessor,memory word and memory byte mean the same thing.010-bit microprocessors:+he memory is divided into a !ord contains 2 bytes '10 bits). & memory !ord is identi1ed in the memory by an address.2or e"ample, the Pentium microprocessor uses 32-bit addresses for accessing memory !ords.+his provides a ma"imum of 232 3 ,,24,,40,,240 3 , 56 of memory addresses, ranging from 77777777,, to 22222222,, in he"adecimal.8Intel Pentium microprocessors:+he memory is divided into segmentsegment 3 210 30,963 addressed by10bits/Intel Pentium microprocessors '1M6):4-$: bit for segment number;igh bit for addressI M6 memory 227 < 210 3 2,2or e"ample, the computer uses 2, address pins to address 224 !" M# o$ memory direct%y &it' addresses $rom 777777,, to 222222,,.17=o. of segment 3si>e of memory < si>e of one segment'210) &n important characteristic of a memory is !hether it is volatile or nonvolatile.+he contents of a volatile memory are lost if the po!er is turned o?. $n the other hand, a nonvolatile memory retains its contents after po!er is s!itched o?. #$M is a typical e"ample of nonvolatile memory. #&M is a volatile memory.11#$Ms can only be read, so is nonvolatile memory. @M$ technology is used to $a(ricate it#$Ms are divided to: mas* #$M and erasable P#$M'(P#$M), and ($M 'electrically alterable #$M)Aalso called ((P#$M or (2P#$M 'electrically erasable P#$M)B1213Mas) ROMs are pro*rammed (y a mas)in* operation per$ormed on a c'ip durin* the manufacturing process. +he contents of mas* #$Ms are permanent and cannot be changed by the user. (P#$Ms can be programmed, and their contents can also be altered by using special eCuipment, called an EPR! programmer. "hen designing a microcomputer for a particular application, permanent programs are stored in #$Ms. @ontrol memoriesused to microprogram the control unit are #$Ms.1,(P#$Ms can be reprogrammed and erased. +he chip must be removed from the microcomputer system for programming. +his memory is erased by e"posing the chip to ultraviolet light +ypical erase times vary bet!een 17 and 27 min. 1.($Ms can be programmed !ithout removing the memory from the #$MDs soc*ets. +hese memories are also called read-mostly memories '#MMs), because they have much slo!er !rite times than read times. +herefore, these memories are usually suited for operations !hen mostly reading rather that !riting !ill be performed. &nother type of memory, called 2lush memory'nonvolatile), is designed using a combination of (P#$M and (2P#$M technologies. 2lash memory can be reprogrammed electrically !hile embedded on the board. &n e"ample of Eash memory is used in cellular phones and digital cameras.10+here are t!o types of #&M: static #&M '#&M), and dynamic #&M 'F#&M).18SRAM +RAMstores data in Eip-Eops. stores data in capacitors.memory does not need to be refreshed.it can hold data for a fe! milliseconds, need to be refreshed have lo!er densities have higher densitiesF#&Ms are ine"pensive, occupy less space, and dissipate less po!er than #&Ms.+!o enhanced versions of F#&M are (F7 F#&M 'e"tended data output F#&M) and F#&M 'synchronous F#&M).T'e E+, +RAM provides fast access by allo!ing the F#&M controller to output the ne"t address at the same time the current data is being read.An S+RAM contains multiple F#&Ms 'typically, four) internally. F#&Ms utili>e the multiple"ed addressing of conventional F#&Ms.1/:e consider the instruction fetch, memory #(&F, and memory :#I+( timing diagrams1427REA+ timin* 1. +he microprocessor performs the instruction fetch cycle as before to #(&F the opcode.2. +he microprocessor interprets the op-code as a memory #(&F operation.3. :hen the cloc* pin signal goes ;I5;, the microprocessor places the contents of the memory address register on the address pins &7,-&1.,, of the chip.,. &t the same time, the microprocessor raises the #(&F pin signal to ;I5;... +he logic e"ternal to the microprocessor gets the contents of the location in the main #$MationF#&Ms are typically used !hen memory reCuirements are !"/ &ords or %ar*er- +RAM is addressed 0ia ro& and co%umn addressin*-2,F#&M $rgani>ation1 -Mb 'one megabit) F#&M reCuiring 27 address bits is addressed using 17 address lines and t!o control lines, #& 'ro! address strobe) and @& 'column address strobe). +o provide a 27-bit address into the F#&M, a -$: is applied to #& and 1 7 bits of the address are latched. +he other 17 bits of the address are applied ne"t and @& is then held -$:.2.+he addressing capability of the F#&M can be increased by a factor of , by adding ("ternal logic is reCuired to generate the #& and @& signals and to output the current address bits to the F#&M.20227 G,3227G22F#&M controller chips ta*e care of the refreshing and timing reCuirements needed by F#&Ms. F#&Ms typically reCuire a ,-ms refresh time, it sends a !ait signal to the microprocessor if the microprocessor tries to access memory during a refresh cycle28Memory &rray Fesign means:interconnecting several memory chips.& microprocessor can address directly a ma"imum of 210 3 0.,.30 or 0,9 bytes of memory locations.2/+he control line M e depends on the number of pages assigned to it..,+he Kirtual memory+he *ey idea behind the virtual memory is to allo! a user program to address more locations than those available in a physical memory. &n address generated by a user program is called a virtual address..+he performance of a microprocessor system can be improved signi1cantly by introducinga small, e"pensive, but fast memory bet!een the microprocessor and main memory..0.8a cache memory is very small in si>e and its access time is less than that of the main memory by a factor of .. +ypically, the access times of the cache and main memories are 177 and .77 ns, respectively. & cache hitmeans ' reference is found in the cache,& cache miss means : reference is not found in the cache, ./+he relationship bet!een the cache and main memory bloc*s is established using mapping techniCues. +hree !idely used mapping techniCues are direct mapping, fully associative mapping, and set-associative mapping..4Firect mapping, +irect mapping uses a RA! for the cache. The microprocessor,s -*-bit address is divided into t!o 1elds, an inde" 1eld and a tag 1eld. 6ecause the cache address is / bits!ide '2/ 3 2.0), the lo!-order / bits of the microprocessorDs address form the inde" 1eld, and the remaining , bits constitute the tag 1eld.In general, if the main memory address 1eld is m bits wide and the cache memory address is n bits !ide, the inde" 1eld !ill then reCuire n bits and the tag 1eld !ill be 'm - n )0701Firect mapping, Firect mapping, +he microprocessor 1rst accesses the cache. If there is a hit, the microprocessoraccepts the 10-bit !ord from the cache. In case of a miss, the microprocessor reads thedesired 10-bit !ord from the main memory, and this 10-bit !ord is then !ritten to thecache. & cache memory may contain instructions only 'Instruction cache) or data only'data cache) or both instructions and data 'uni1ed cache).0203Numerical example for Direct mapping("ample :+he content of inde" address 77 of cache is tag 3 7 and data 3 7 132. uppose that a microprocessor !ants to access the memory address 177. +he inde" address 77 is used to access the cache. Memory address tag 1 is compared !ith cache tag 7. +his does not produce a match. +herefore, the main memory is accessed and the data 28 1, is transferred into the microprocessor. +he cache !ord at inde" address 77 is then replaced by a tag of 1 and data of 28 1,.0,$ne of the main dra!bac*s of direct mapping is that numerous misses may occur if t!o or more !ords !ith addresses that have the same inde" but di?erent tags are accessed several times.0.2ully associative mapping+he fastest and most e"pensive cache memory(ach element in associative memory contains a main memory address and its content 'data). 002ully associative mapping:hen the microprocessor generates a main memory address, it is compared associatively 'simultaneously) !ith all addresses in the associative memory. If there is a match, the corresponding data !ord is read from the associative cache memory and sent to the microprocessor. If a miss occurs, the main memory is accessed and the address and its corresponding data are !ritten to the associative cache memory. 082ully associative mapping0/2ully associative mapping(ach !ord in the cache is a 12-bit address along !ith its 10-bit contents 'data). :hen the microprocessor !ants to access memory, the 12-bit address is placed in an address register and the associative cache memory is searched for a matching address. uppose that the content of the microprocessor address register is ,,.. 6ecause there is a match, the microprocessor reads the corresponding data $2&l into an internal data register.04et-associative mapping.a combination of direct and associative mapping.cache !ord stores t!o or more main memory !ords using the same inde" address. (achmain memory !ord consists of a tag and its data !ord. &n inde" !ith t!o or more tags and data !ords forms a set87et-associative mapping.:hen the microprocessor generates a memory reCuest, the inde" of the main memory address is used as the cache address. +he tag 1eld of the main memory address is then compared associatively 'simultaneously) !ith all tags stored under the inde". If a match occurs, the desired data!ord is read. If a match does not occur, the data !ord, along !ith its tag, is read from main memory and !ritten into the cache81et-associative mapping.82et-associative mapping.+he si>e of a set is de1ned by the number of tag and data items in a cache !ord. & set si>e of 2 is used in this e"ample. (ach inde" address contains t!o data !ords and their associated tags. (ach tag includes , bits, and each data !ord contains 10 bits. +herefore, the !ord length 3 2 x (4 + 16) = 40 bits. An index address of 8 bits can represent 2.0 !ords. ;ence, the si>e of the cache memory is 2.0 " ,7. It can store .12 main memory !ords83;o! to !rite on cache :+here are t!o !ays of !riting into cache: the !rite-bac* and !rite-through methods.8,+he write-bac# methodwhenever the microprocessor writes something into a cache !ord, a LdirtyM bit is assigned to the cache !ord. :hen a dirty !ord is to bereplaced !ith a ne! !ord, the dirty !ord is 1rst copied into the main memory before it is over!ritten by the incoming ne! !ord. +he advantage of this method is that it avoids unnecessary !riting into main memory.8.+he write-through method, whenever the microprocessor alters a cache address, the same alteration is made in the main memory copy of the altered cache address. +his policy is easily implemented and ensures that the contents of the main memory are al!ays valid. +his feature is desirable in a multiprocesssor system, in !hich the main memory is shared by several processors. 80A 0a%id (itused to ensures proper utili>ation of the cache. It is an e"tra bit contains in the tag directory"hen the power is turned on, the valid bit corresponding to each cache bloc* entry of the tag directory is reset to >ero. +his is done to indicate that the cache bloc* holds invalid data. :hen a bloc* of data is transferred from the main memory to a cache bloc*, the valid bit corresponding to this cache bloc* is set to 1. 882inally, microprocessors such as the Intel Pentium I1 support t!o levels of cache, -1 'level 1) and -2 ' level 2) cache memories. +he -1 cache 'smaller in si>e) is containedinside the processor chip !hile the -2 cache 'larger in si>e) is interfaced e"ternal to the microprocessor.8/+he - 1 cache normally provides separate instruction and data caches. +he processor can access the -1 cache directly and the -2 cache normally supplies instructions and data to the -1 cache.+he -2 cache is usually accessed by the microprocessor only if - 1 misses occur. +his t!o-level cache memory enhances microprocessor performance.84