Chapter 2 Textbook 8086

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Software rchitectureof rhe B0BB nd 8086

Microprocessors

._RODUCTION

Thischapter egins ur study ofthe 8088 nd 8086 micfoprocessors nd hejr assembly:iguage programming- o program ither he 8088or 8086 sing assembly 3nguage, e'nust understand ow the microprocessor nd r! mcrnory nd nput/output ubsystemsrDeraterom a sofiware oint of view.For this reason. n this chapter. e will eramine'.1:loltwarcdrchitecture fthe 8088 nd 8086 microprocesso.s he material hat ollou's:=quently efers nly o the 8088 microprocessor, ut evefything hal s described or lhe:,188also applies o lhe 8086. This s because he softwarc rchitecture f the 8086 s:1.'iical lo that of the 8088.The ollowing opics re covered ere:

2-1 Microarchitecture f the 8088/8086 icroprocessor2.2 SoftwareModelofthe 8088/8086 iffoproceslor2.3 Memory Addrcss pace nd Data Organization2.4 Data Types1.5 \egnenr Re- i . .e - JrJ \4eno^ Sermen' : ' r '2.6 Dedicated, Reserved, nd General Use Memory2.7 InstructionPointer2.8 Drta Regislels2.9 Poinrer nd ndex Registers2.10 Status Registcr

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2.ll Generating Menory Address2.12 The Stack2.13 lnput/Output ddress pace

2.I MICROARCHITECTUREF THE8088/8086 MICROPROCE5S0R

The microarchitecture f a Focessor s its intemal architecture-ihat is, dle circuit build-ing blocks that implement the softwlre and hardware archiiectures of ihe 8088/8086microprocessor's. ue to the need for additional fbatures and higher perfbrmance, hemicroarchitecture of a microprocessor amily evolves over time, In facl, a new micro-architecnrre s introduced or Intel's 8086 anily every ew yea$. Each new genemtion fprocesso$ rhe 8088/8086, 0286, 80386, 80846, and Penrium rocessors) epresenrs

signi6cant hanges n the microarchilecture f the u086.The microarchitectures f the 8088 and 8086 icroprocessors rc simildr.Theyboth el|.ploy arallel mcerrirg-that is, they re iDrple e ted with several imulla e-ously operaling rocessing nits.Figure2-l(a) illustrates he Dtemal rchitecture f the8088 and 8086 mjcroprocssors. hey contain wo pro.essing ux,ils:he bus nterlace unh\BIU) and he execution ri l (EU).Each unit has dedicated unclions nd bothoperate tthe same ime, n essence, his palallel rocessing lTeclively akgs he etch and execu-lion of instruclionsndepeodenl perations, his esults n efficient se ofthe system usand higher erformance or 8088/8086 icrocomputer ystems.

The bus nterface nit s he 8088/8086's onnection o the outsideworld.By inter-face,we mean he path by whioh h connects o external evices. he BIU is responsiblfor performing ll external us operations, uchas nstruction etching, eading nd w,it-ing of data operands or memory and nputting r outputtlng ata or input/output ei -pberals, hese nlbrmadon ranslers ake placeover be system us, This bus ncludes n8-bit bidirectional atabus or the 8088 16 bits or the 8086), 20-bit address us, andlhe signals eeded o contlol ansfers over he bus. The BIU is not only responsible orperlbrming bus operations, t also performs ofier lunctions related o instruction and dataacquisidon, or nstance, t is responsible or instruction ueuing ndaddress ederaiion,

To implemenr hese irnctions. he BIU contains he segment egisters, ie instruc-tion pointer, he address eneration dder, us controi ogic, and an nstruction ueue.Figwe 2 l(b) shows he bus nterface nit ofthe 8088/8086 n more detail. he BIU usesa mechanism nownas an nttruction ue e ta lmplement pipelined rchitecture. hisqueue permits the 8088 to prefetch up to 4 bytes (6 bytes for the 8086) of instmctioncode. Whenever he queue s not irl-that is, t has oom or at east 2 more bytes, nd.ai the same ime, the execution unit is not asking t to read or write data rom memory-the BIU is free to iook ahead n the program by Fefbtching the next sequential nstruc-tions.Prefetched nstructions re held n the first-in irst out (FIFO)queue. henever

byte is loaded at the input end of the queue. t is autonaticdily shifted up through theFIFO to the empty location nearest he output. Here the code s held until dre executionunit is ready to accept t. Since nstructions are nomally waiting in the queue, he timeneeded o felch n1sny nstructions of the microcompuier's progam is etiminated. f thequeue s full and he EU is not requesting ccess o data n memory, he BIU does not

28 Software Architecture of the 8088 and 8086 MicroDrocessors Chao. 2


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INSTRUCTIONPIPELIIIE

SYSTEM US

(a)

lus ||{iEaFlcc xrr rru)

{b t

Figurc 2-1 (a) Pipelined echitecture of the 8088/8086 microlrocessors (RePrtutedwiih pemi$ion of l;tel Corloration. Copltisht/Intel Corp 1981) b) E\ecution dd businterlace uits. (Reprinted with permission of Intl Corp . ColyriShvlntel Corp l98t)

2l)


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rcd 10 prform atry bus opflations. These ntervals of no bus activity, which occurbtwen bus opemtions, are k'rc.itn as dle states.

The execution unit is responsible o. decoding and executing nstructions. Notice nFig. 2-1(b) that it consists of ile arithmetic loqic unit (ALID, status and control flags,general-purpose egisters, and emporary-operand egisters. The EU accesses nstuctionsftom the output end of the instuction queue and data rom the general-purpose egistersor memory. t reads one instuction byte after the other liom the output of the queue,decodes hem, generales

ata addresses f necessary,asses

hem to ihe BIU and requestsit to perform the read or write operations o memory or I/O, and pefolms the operationspecified by the instruction- The AIU perfoms the arithmetic, ogic, and shift opemrionsrequircd by an instruction. During execution of the instruction, he EU may test the status and contlol flags, md updates hese lags based on the results of exe.uting he instruction. If the queue s emptt the EU wairs for ihe nexr nstrucrion byte to be fetched andshifted to the toD of the oueue.

l' 2,2 SOFTWARE ODEL OF THE8088 808 6 MTCROPROCESSOR

The pwpose of developing a soltuate model s to aid the Fograrnmer n understandingthe operation of the mioocomputer system rom a software point of view To be able toFogram a microprocesso! one does not need o krow all of its hardware architecturalfeatures. For instance, we do not necessarily eed o know the functjon of the signals atits vrrio s pjns, their electrical connections, r their electrical switching characterisrics.

The function. nterconnection, nd opemtion of the ntemal circuits of the microFocessoralso may not ned o be considered. Wlat is important o the progammer is to know thevarious egisters within rhe device and to undefitand heir purpose, unctions, operatingcapabiiiries, and initations. Fudhemore, it is essential hat the Fogrammer knows howextemal memory and nput/outpur peripherals are organized, ow info.mation s anangedin registers, memory and nput/ouFul and how mernory and I/O are addressed o obraminstuctions and data. This information represents he software archilecture of the processor. UDlike the miffoarchitecture, the software architectdre changes only sllghtly liomgeneration o generaiion of processor

The software nodel in Fig. 2 2 illusaa&s the software archiiecrure of rhe 8088microprccessor Looking at this diagam, we see hat t includes 13 16-bit ntemal reg1s-te'the instruction ointer lP), ow tta fgisten (AX, BX. CX, and DX), two pdl"re.r'sirt?r'r BP and SP), two inder leqistets (SI nd DD, and four r"grnt resisreff (CS.DS, SS, and ES). In addition, here s another egister called he rtdrrr /e8trt / (SR), withnine of its bits implemented as status and control flags.

Figure 2-2 shows hat the 8088 architect$e mplemenfs ndependent memory andinpui/ouQut address spaces. Notice that the memory addrcss space s 1,048,576 bytes(lMbyte) in length and the I/O address pace s 65,536 byres (64Kbyret in length. Our

concem here s what can be done with this software architecture nd how to do it duoughsofrware. For this purpose, we wil now begin a derailed srudy of the elements of rhemodel and heir relationship o software.

30 Software Architecture or the 8088 and 8086 Microorocessors Chao. 2


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------__-lrp

_lD5ss

SI

OI

:rtl]

Figurc 2-2 Sotrde model of the

I.'EMORYADDRESS PACE]ATA ORGANIZATION

lar; ':harwe have nhoduced he idea of a softwa:,:. iu.h as numbers, haracters, nd nstrucnon-j: l-j. fie 8088 microcomputer uppods Mb)ra: rr orgrnized rom a software point of view as


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00008H

00007H

00006H

00005H

00004H

00003H

00002H

oooolH

00000H

Byre

B!1e7

Byre

Byls 5

Byre

Byre

Blt 2

Bis 1

By,le

_l5

I

-l

1_lt\4isaligned Figure 2-5 Examples of aligned and

wods misaligned data words

EXAMPLE.I

Wlat is the data word shown n FiS 2 4(b)? ExFess the result n hexadecimal orm lsit stored at an even- or odd-addressed ord boundary? s it an aligned or misaligned word

of data?

SolutionThe most significant byte of the word is stored at address 072Cr6 and equals

111 r 11 0 1 , = F D r 6 = F D H

Its least signifiant byte is stored at address 072816 nd s

1 0 1 0 1 0 1 0 r = A A 1 6 = A A H

Together he two b''tes give the word

1111110110101010,FDAAT6 FDAAH

Expressing he address f the east signiicant byte in binary form gives

0072BH 00728t6 = 0000000001110010101l'z

Because he dghtmost bjt (lJB) is logic I' the word is storcd at an odd-address ound-

ary in memory; herefore, t is a misaligned word of data'

; .6

;.

il.2

;,.0

I

5ec. 2.3 Memory ddress pace nd Data Organization 33


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Aigned

-l

Doubl

I

0

T\e double wod is af'ofier data form that can be Focessed by the 8088 miclo-computer. A double word conesponds o four consecutrve ytes of data stored n mem-ory; an example of double-word data s a /oint,: A pointer s a two-word address lement

that is used o access data or coden rnemory The word of this pointer that is srored at

the higher address s cale.d the se7ment ase addres8 and the word at the lower addressis called the o.frt

Just ile for words, a double word of data can be aligned or misaligted. An aligneddoubleword s located t an address hat s a multiple of4 (e.g., 000016, 000416, nd0000816). A number of aligned and misaligned double words of data are shown inFig. 2 6. Of tbese six examples, nly double words 0 and 4 are aligned double words.

An example showing he storage of a pointer in memory s given in Fig. 2-7(a).Here the higher-addressed o.d. which represents he segment base adalress, s stored

Figure 2-6 Examples of atgned mdmissligned double words of daia.

00008H

00007H

00006H

00005H

00004H

00003H

00002H

00001H

00000H

Byte8

Byre

Byts 6

Byle 5

Byle 4

Byre3

Byle 2

By,le1

By,te

lDoubl

"g'd--l

i-- || | Ddbre

I oo,ur" sDoubie 2

I __ll

| 38 J 00008,6| ao I

t-. "--loooor,.frr- ooloooos,"l---il

fi- 5_l ooooe,"f--;_l

Figure 2-7 (a) Storilg a 32-bit pointei in nenory. (b) An examlle.

software Architecture of the 8088 and 8086 Microprocessors Chap. 24


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I

:iaiing at even-ad&ess oundry 0000616. he most significant byte of tbis word is at:ddress 000716 nd equals 0111011, 38!6. is least sig.iGcanl yte s at addressr]10616 ndequals 1001100, 4C16. ombining hese wo valucs, e get he segment

rlrle addrcss. hjch cqmls 0011101101001100, 3B4Cr6The o$set paft of the pointer is the lower addressed word. Its leasl significant

r\re is stored t address 000416; his location oniains 1100i01, = 6516 The nost!:gnificanr yte s at address 0005 6, which contains 0000000' 0016. he resulting

rr'-ser s 0000000001100101, 006516. he complete ouble word is 384C006516.S:nce his double word stads ar address 000.116, t is an example f an aligned ouble

.XAMPLE2.2

ir{ should he pointer with segment base address equal to A00016 and o11iet addrcss

::FFr6 be siored at an even-ad&ess ounday starling at 0000816? s the double wodr::ned or nisalisned?

:J lution

::.age of fie two word pointer equires our consecutive yte ocations n memory, ta(:: al address 0000816. The ler.st signilicant byte of the offset is stored at address 0tl008r,jr: ii shown as FF16 n Fig. 2 7(b). The most significant byle ofiheoffset,5516, s stored. =idress 0000916. hese wo bytes fe folowed by the lcast significant byte of lie seg--.:ri base address, 0016. at address 0000A16, and its most signilicant byte, A016, qt

:i-3,s 0000816. Since he double word is slored n memory starting ai address 000816,: r- Jrgned.

-=ATA yPES

::E ti..eding section dentified the fundanental data fonnats of the 8088 as the byteI :'j,. $ord (16 bits). a.d double word (32 bits). lt also showed how each of these ele--i.-i ii llored in memory. The next step is to examile the rypes of dalr ihat can be codedn r?rP f^m 'R lnr nrn.Pccino

The 8088 rnicroFocessor dirdtly processes ata exprcssed n a number of differ-:E :r riprs. Let us begin with the inteser ttuta tlpe. The 8088 can process daia as-::::c:. ahsigned ot signed trtg?r' numbeN; each type of integcr can be either byte'wide:' :::i-\\ide. Figure 2 8(a) reFesents an unsigned b$e irteger; this data type can ber-: :'represent decimal numbers n the range 0 tkough 255 The unsigned word inie

E r: .ir)$ n in Fig.2

8(b);il cm be used o represent ecinlal numbers n the range 0

F:!= 6:.535.

Dat Types 35


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MSe

Figure 2-8 (a) Ursisnod byteinteger b) Unsigned ord Dtcgi

EMMPLE2.3

What valuedoes he unsigned ord nteger 100016egesent?

Solution

Fint, the hexadecimal nteger s convcrted o binary fom:

100016 0001000000000000,

Nex1.we tind the value or the binary number:

000r000oooooo00012''z 4096

The signed yte nteger nd signedword nteser n Fiss. 2-9(a) and b) are similar

to the unsigned nteger ata ypes ust intoducedi however here he most signilicant itis a sign bit. A zero n this bit position dentifies positive umber For his reason, iesigned nteger byte can reFesent decimal nunbers in the range + 127 to 128. and ihesigned nlegerwordpcrmits umbers n tbe range +32,767 o 32,768, espe.tively. orexample. he nnmber +3 exprcssed sa signed ntegcr yte s 0000001l, 0316). n iheother hand, he 8088 always expresses egaiive umbers n 2's-complemenl otationTheretbe. 3 is coded s 11lll10l, (FDLJ.

I'igure 2-9 (a) Siged byre .teger(b) Signed word integer

36 software Architecture of the 8088 and 8086 Mjcroprccessors chap. 2


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qAMPLE 2.4

-{ ngned word integer equals FEFFT6 W}at decimal number does t represent?

Solution

E\pre-mg fie he(adecimal umbe' n binary onn gives

F E F F T 6 1111111 0 1111111 l ' ?

Since he most significant bit is 1, the number s negative and s in 2.s complemenr orm.Converting o its binary equivalent by subracting 1 ftom rhe east significant bit and rhencomplementing ll bits gives

FEFFT6 - 0000000100000001'z

The 8088 can also process data hat is coded as ,l ary-coded decinal (BCD) num-,"ru. Figure 2-10(a) lists the BCD values or decimal numbers 0 thmush 9. BCD data

BCO

123

6I3s

00{x)00010010001101000101

0 1 1 1r000100!

MSB

BCOOigh

BcDDisit BcDDieiro FiguE 2-I0 (a) BCDnubers. (b) AnUnpacked CD digit. (c) Pacted BCD

(c) digirs.

D,

Sec. 2.4 Data Types 37


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can be stored n eithr unpacked or packed orm. For instance, he unpacked BCD bvie inFig 2. r0{br howi lhara ,ingle BCD digir \ jrored n rhe our teasr ignificanr ir:.andthe upper oul bits are set o 0. Figure 2-t0(c) shows byte wirh pa"Lea nCl atgitr.H-re wo BCD numbers are srored n a byre. The upper our bits repiesent he mostiig_nificant igjtof a rwo-digirBCD number.

EMMPLE .5

The packed CD data stored t byre address 100016 qual 10010001r. hat s the rwo_digit decirnal number?

SolutionWdting he value 0010001, ssepamte CDdigits ives

10010001, 100lBcD000lBcDglro

. Information xpressed n ASC (Ane can Standad Code br Inlothlation nter-c/r.up?) an alsobe direcrly hcessed ) fie 80ggmicroprocessor.he cban n Fig.z-rla) snous how numbers.etters. ndcontrol haracters re coded n AscI. Forinslance,henumber is coded s

H rH o 0 11 0 1 0 1 , 3 5 H

where denoteshat heAscll-coded umbers n hexadecimalorm.As shownn Fig.2-ll(b), ASCIId6ta restored sone haractef erDvre.

EXAMPLE,6

Byreaddresses 110016hrough 110416ontainhe ASCIIdata tOOO001,l010Oll,01000011. 1001001,nd 01001001,specrively, ha! o he data tandor?

SolutionUsing he charr n Fig. 2-11(a), he data are converted o ASCII as ollowsl

(01100H) 01000001Asc! A

(01101H) 0101001l^scl l s

(01102H) 0100001lAscl c

(01103H) 01001001Ascr I

(01r04H) = 0100100lAsctr I

3A software rchitecture f the 8088 and 8096 Microprocessors Chao.


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0 10

N 0 5 70 0 0 0 DLE0 0 0 1 soN DCT

2 STX ac2 2 B

0 0 1 1 3 ETX sEOT T

0 1 0 1 5 ENO E

0 t 1 0

B E L

r 0 o o HH T E]VI I

1 o l 0 SUB zES C

L

1 1 0 1 G S

1 1 1 0 E

1 1 1 1 SI 7 o O E L

ASCII0 s r

{b)

Figue 2-11 (a) ASCI lable. (b ) ASCII digir.

MSB

I : 5 SEGMENT EGISTERSND..,iMORYSEGMENTATION

Even hough he 8088 has a lMbyre addrels pace, ot altthis memory s active ar oneune. Actually. the lMbytes of memory are paririoned into 64Kbyte (65,536) segnents.

{ segment epresenls n independently ddressable ni t of memory onsisring t 64K.onsecutrve byte wide storage ocarions. Each segrnent s assigned a l7ar dddr,rr haridentifiests st:rting point-rhal is, h lowest ddress yte-storageocation.

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Only four of these 64Kbyte segments re active at a tinet the code segmenL tacksegmenL 1ta segment, and ertu segmen' The segments f memory that are active, asshowninFig.212,areidentif iedbythevaluesofadalressesheldinthe80S8'sfnal segment egisters: CS (code segment). SS (stack segment), S (dala segment), nd EJ(extra segment). Each of these egisters contains a 16-bit base address hat points to the

lowest addressed yte of the segment n memory Four segments give a ma-\imum of256Kbytes of active memory Of this, 64Kbytes are or p tognn storuqe code), 64KBresare o{ a rtarl, and l28Kbytes arc for data storage.

The values held in these egisters are referred o as he carrcnt-segment egktet wl',l$ for example, he value n CS points to the fust word-wide stoBge ocation n the cur-rcnt code segment. Code s always elched rom memory as words, not as bytes.

Figure 2 13 iluslJates the se?mentation f memory In this diagram, he 64Kbytesegments re dentified with letters such as A, B. and C. The data segment DS) registercontains he value B. Therefofe, he second 64Kbyte segment of memory iom the top,labeled B, acts as lle curcnt data-storage egment. This is one of the segments n whichdaaa hat are to be pmcessed y the miqocomputer are stored. For this rcason, his part

__rJ--- L-

Slack

8088/8086

csssDS

Enra

Figurc 2-12 Active segments f memory

00000H

40 software Architecture of the 8088 and 8oa6 Microprocessors ChaD.


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-^-E1----* *l--}-r

"^'"EF-*- "Eh FFl"E- Figure 2-13 ContiSuous. djeent,

disjoirted, and overlapping segnells.(Reprinted by permission of IntelCorp., Copyright/hiel Corp. 1979)

of the midocomputer's memory address pace musr contain ead/write storage ocationsdat can be accessed y instructions as storage ocations for sou.ce and destinationoperands. CS selects segment E as he code segment t is lhis segment f memory romqhich instuctions of ihe program are currently being fetched or execution. The stackiegnlent (SS) egister contains H, thereby selecting he 64Kbvte segment abeled s H forllr as a stack. Finally, the extra segment ES) register s loaded with value J such hat

.egment J of memory unctions as a second 64Kblae data stonge segment.The segment egisters are sedd o be user accessible. his means bal the program-

rer can change heir contents hrough software. Tberefore. or a program o gzrn access_roanother part of memory one simply has o change he value of the apFopriate register.r rcgisters. For instance. a new data space, with up to l28Kbytes, is brought n simplyi'! changing he values n DS and ES.

There s one reslriction on tl alue assigned o a segment s a base addrcss: t must6ide on a l6-blte address oundary. his is because rcreasing he 16-bit v,lue in a seg-r.rr register y I actually ncreases he conesponding memory address y 16i examples f

ru.lidbase addresses re0000016, 00101 ,and 00020i6. ther than his restriction. egments:a be sel up to be contiSuous. djacent, disjointed, or ever overlapping; or example' mFS. 2 13, segnents A and B are contiguous, whereas egments and C are overlappitrg'

I Z6 DEDICATED, ESERVED,I'{D GENEML-USEMET,4ORY

rnl p3rt of the 8088 miclocomputer's Mbl'te address pace an be mplenented br the

r's access: howeve( some address ocations have dedicated ctions utd sharld not!E u-ed as general memory or storage of data or instmclions of a progam. Let us nowil\.t ar these eserved, edicated se, and general-use arts of memory.

-EHE-n-E

:t 26 Dedicated, Reserved, nd Genfafuse Memory 4 l


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Figure 2-14 shows the ,'ererye4 dedicated-use, afi seneruI-use parts of the8088/8086\ dddrff space. Norice rhat storage ocations iom address 000016 o 0001316are dedicated, nd hose tom address 001416o 0007Fr6 re eserved. hese 28 bytesof memory are used or siorage of pointers o inielrupt sgrvice routines. The dedicaredpait is used o store he pointers or the 8088's ntemal intenupts and exceptions. On theoiher hand, he reserved ocations are saved o srore pointers rhat are used by the user-defined interruprs. As indicated earlier, a pointer is a rwo-word address elemqnt andrequires 4 byies of memory. The word of this pointer at rhe higher address s caled thesegment ase adahess nd

the word ar rhe ower ad&ess s rhe otrset. Therefore. his seution of memory contains up ro 32 pointers.The part of the address pace abeled dp?,? n Fig. 2 11 s general- :e memoryr r:d

is where data or instructions of the program are srored. Notice that ihe genefal use areaof memory s the range hom addresses 016 hrough FFFEFT6.

At the high end of the nemory address pace s anorher eserved ointer area, ocatedfromaddrcss FFFCr6hrough FFFFT6. hese our memory ocations re ese edforusewidr tuture products ard should nor be used. nrel Corporarion, he original manufacturerof the 8088, has dentified he 12 storage ocations rom address FFF0 6 hrough FFFFB .,as dedicated or functions such as storage of the hardware eset ump instruction.

Forinstance, addrcss FFF0I6 s $here the 8088/8086 egins execurion Jter eceiving a reser.

2.7 INSTRUCTION OINTER

The rcgister hat we will consider next n the 8088's softwa.remodel shown n Fie. 2-2 isthe nntu. t ;un viater lPr.LP rr*, lb oits n elgrh nd idenrjhe5 he ocario; , Lhenext word of instfuction code o be fetched rom rhe cunent code segment f memory. TheIP is similar to a progran counter: however, t contains ahe offset of the nexr word of

instruction code nstead ofits actual address. his is because p and CS are both 16 birs nlength, but a 20-bit address s needed o access memory. nremal to the 8088. he offset nIP is conbined with the currenr vaiue n CS to generate he address f the nsrrucrion code.Therefore, he value of the address or the next code access s ofte, deDoted s CS:I?_

rigue 2-14 Dedicated use,eseredi and general-use memory(Repdnted by lermission of IntelCorp.,Copyrightl el Corp. 1979)

42 software A/chitecturc of the 8088 and 8086 MicroDrocessors ChaD. 2


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During nom1al operation, he 8088 fetches nstructions iom the code sesmenr ofmemor). ore. rhem n L5nst uclior qL,eue. nde\ecuLe\ nemone aller he olh;r Eve^rjnred $ord ol code \ lelched rom memo,). tre8088 upddres }le alue " Ip.,.h r; ;it points to the firsr byte of the nexr sequenriat word of c;de_that is, Ip is incrememedby 2. Actilally, Lhe8088 preferches p to four b],tes of insrruction code nto its intemalcode queue and holds

them there waiting for execution.A1teran nstrucrion s read rom ihe outpur of the ns!.udion queue, t is decoded: fnecessaq. perand. re ead om eithefL}edfla.egn.n, or..rno.1 or i emal egisrers.Next, he operation pecilied n the nstrucrion s performed on f]le operands nd thirasultls written back b either an ntemal regisrer or a srorage ocatiod n memory The 808g snow ready o execute he nexi instruction n the code queue.

fxecurin8 an in,rrl,crior$ar toad" a neu ratui inro rhe CS regisler hatrges heactive code segmenL hus, any 64Kb],,resegmenr of memory can Ulsea to stire rnemsruc[on code,

. 8 DATA REGISTERS

As Fig. 2-2 shows, he 8088 has fow generat_purpose ata registers. During plogramirecution. they hold temporary values of frequently used ntermediate esults. oftivare.an read..load, or modii, rheir conrents. ny of the general-purpose ata egisre$ can beusd as rhe souce or destination of an opemnd during an arithmeti; operarion such as{DD or a logic operarion such as AND. For instance, he values of tw; pieces of data,a and B. could be moved ron memory nto separate ata registers and operations suchas addition, subtraction, and muttiplication performed on them. The advaniage f storingiiese data n internal regisrers nsread of memory during processing s that they can b!accessed uch fasrer

The four rcgisterc, known as the data rcgiste$, are shown n more detail in Fig.l-15(a). Notice hat they are rcfened o as the accumulator e|ister (A). the base regis;;rB),the count egister C),^\dtt)e data cgister D).These ames mply speciat irnJriors

t5

axBH BI

C H i C L

DXDH DI

BX

ctDX

Word ultipl,, *ord divid.,

Byt. oulriplr, bytgdivjd.,byt.I/O, ranslate, .c j al uirhmcricByt. muhiply. yredivid.

Word ujtiply,yo.d dirid.,

Figum^2-15_ra, Ceremt-purpo\e oraegr.LeF ,Repinred ) prmNjo) ^l

In f , (o rp . Cop)r igh . / tn re torp ta-or ,b , DeJi ;ared eg i ,Lr :mron .r


18/31

they are meant o perform for the 8088 nicropmcessor Figure 2 15O) summarizes heseoperations. Notice bal slring and oop operations se he C register. For example, he vatuein the C register s the number of bytes o be processed n a string operation. This s the rea-son t is given he nane co&nr e3drrer Another example of the dedicated se of data egis-ters s drat all input/output operations must use accumulalor egister AL or AX lbr dala.

Each of these egisters an be accessed ither as a whole (16bits) fot word dala oper-ations or as wo 8-bit registers or byte-wide data opemtions. An X alter the register etteridentifies he reference l a register as a word; for inslance, he l6-bit accumulator s ref-erenced s AX. Similady, he other hre word registen are eferred o a-s X, CX, and DX.

On the other hand, when referencing one of these egisters on a byte wide basis,following the register name with ihe letter H or L. respectively. dentifies he high byteand low byte. For the A register the most significant byte is refered to as AH and theleast significant byte as AL: the otber byte-wide register pairs are BH and BL, CH andCL, and DH and DL. When software places a new value in one byte of a register, br

instance AL. rhe vatue n the other byte (AH) does not change. This ability to processinformation in either byte location permits more efficient use of the limited registerrcsources f the 8088 microprocessor

Actually, some of the data registers may also store address nformanon such as abase address r an nput/output address;for example, BX could hold a 16-bitbase address.

2.9 POINTER ND INDEXREGISTERS

The software nodel in Fig. 2-2 has our other geneml purpose egisters: wo/o,r?ter'l8irte6 and two index resisters. They siore what are called olfiz dddrei.!?r. An offsetaddress epresents he displacement f a siorage ocation in meruory hom ihe segmentbase address n a segment egister that is, it is used as a pointer o. index to select a spe-ci{ic storage ocatron within a 64Kbyte segment f memory. Software uses he value heldin an ndex register o reference ata n memory elative o the data segmeft or extra seg-mert registet and a pointer register o access memory ocations elative o the siack seg-ment register. Just as for the data egisters, he values held in these egisters an be read,loaded, or nodilied ttuough software- This is done prior to executing he instructioD hatreferences he reglster or address offset. Unlike the general-pui?ose ata regisie|s, hepointer and ndex rcgisters are only accessed s words. To use he offset address n a registet the nstruclion simply specifies he rcgister hat contains he v21ue.

Figure216showsthat thetwopointerregistersarethestoxkpointer(SP)poirter (BP). The values n SP and BP are d as offsets rom the currenr value of SSduring the executior of instructions hat nvolve he stack segment f memory and permiteasy access o storage ocations n the stack part of memory. The value n SP always cp-resents he offset of the next stack ocation that is lo be accessed. hat is, combining SPwith the value n SS (SS:SP) esults n an address hat points o the top ,/tftc rtdct (TOS).

BP also epresenls noffset elative o the SS; howevet t is used o access ata withinthe siack segment f memory To do this, t is employed as he offset n an addressing modecalled he b6ed aAiressinq ?,ode.One common use of BP is to reference arameten hatare passed o a subroutine y way of the stack. n ihis case, nstructions are ncluded n thesubroutine hat use based addressing o access he values of parameters rom the stack.

44 Software Architecture of the 8088 and 8086 Microprocessors chap. 2


19/31


20/31

resuli of executing an instruction-that is. after executing an instruction, such as ADD,specific lag bits are resel (logic 0) or ser (logic 1) based on the result that is produced.

l,et us fifft summarize he operation of these lags:

l. The carry a| GF): CF is set f there s a carry-our or a bonow-in for the most sig'nificant bit of the result during the execution of an nstruction. Otherwise. CF s reset

2. The paity fag (PF): PF is set l the result Foduced by ihe instruction has evenpariry-that is, if it contains an even number of bils at dre I logic level If pariry isodd. PF s reset.

3. The auaiLia,J ca a frag (AF)r AF is set f there s a cany-out from the low nibbleiDto the high nibble or a bolrow-in ftom the high nibble into the iow nibble of drelower byte in a l6-bit word. Otherwise, AF is resel.

4, The zero ag (ZF): ZF is set f the resulr produced bv an nstruction s zero Other-wise.ZF is reset.

5. The sign tag 6F): The MSB of the result s copied nto SF Thus, SF is set f the

resuh s a negative number or rcset f it is positrve6, The owdow fag (OF): When OF is set. t indicates hat the signed esult s out of

range. f the result s not out of range, OF rernains cset

For example, at the completion of execution of a b)'te_additlon nstruction, he carryflag (CF) could be set o indicate hat he sum of the operurds caused carry out conditionThe auxiliary crry flag (AF) could also set due to the execution of the instruction Thisdepends n whether or not a carry-out occuned rom the east significantnibble o the mostsignificantnibble when he byte operards are added. he sign lag (SD'is also affected' and

it reflects he ogic 1evel f the MSB of the resultThe oYerflow lag (OF) is ser f there s

a carry-our of the sign bit, but no carry nto the si8:n ii (an ndication of overltow).The 8088 provides nstructions wlthin its instruclion sei ihat are able to nse these

flags to alter lhe sequence n which the program is executedi or inslance. a jump toanothei palt of lhe program could be conditionally initiated bv testing for ZF equal tologic.Thi. operarion ' ca\led np aa .cto

The other hree mplemented lag bits-the diz.rion fraB (DF), ttje intempt enabte

f"tLs0F), ad the rap ias GFFarc untrol fags'I'nese thrce lags provide contol func-

tions of the 8088 as ollows:

l. The trap fag (TF): If TF is set, he 8088 goes nto the rinSl r/ep ,rod? of opera-tion. When n the single-step mode, t executes n instruction and then umps to aspecjal seflice routine that may deter rine the effect of executing he instructionThis type of operation s very useful ror debugging Fograms

2. Th? nte tru!f"B tl Forrhe8088rorecogni /ena\ \ablc ,nrcr 'uPt 'c , |uc \t \a t i t 'interrupl (INT) input, the IF flag must be set. When IF is reset, equests t INT areignored and the maskable nterupi intedace s disabled

3. The dircctinn ag @F)r The logic level of DF detemines the direction in whichsrring operaiions will occur When set, the slring instruction automatically decre-

ments he address; herefore, he string data transfers Foced from high addressto low address. On the other hand, resetting DF causes he string address o beincremented thal is. daia transfers proceed rom low address o high ad&ess

46 Soft\rare Architecture of the 8088 and 8086 [4icroprocessoG Chap. 2


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The instruction set of the 8088 ncludes nstruclions or saving, oading, or manip-ulating the flags; or instance, pecial nstuctions are provided o pemit user software oset or rcset CF, DF, aDd F at any point in the program e.g., ust pdor to the beginnin-q fa slring operation, DF is reset so that the string address utomatically nffements).

2,iI GENEMTING IV]EMORYDDRESS

A segment ase and an offset descibe a logicaL addless n the 8088 microcomputer ys-tem. As Fig. 2-18 shows, both the segment ase and offset are 16-bit quantities, since allregisters and memory ocations used n address alculations are 16 bits long. However,rhepbsical a&lrcss that s used o access memory s 20 bils in length. The generation fthe physical address nvolves combining a 16-bit offset value hat s located n the nstruc-iion pointet a base egister, an index register, or a pointer register and a 16-bit segmentbase value hat is Iocated n one of the segment egisters.

The source of ihe offset value depends n which type of memory eference s tal_

ing p1ace. t can be the basepointer (BP) rcgisier, stack pointer (SP) register, base BX)

regisrer, source ndex (SI) register, destination ndex (DI) regjster, or instruction poinrer(IP). An offset can even be fonned from the contents of several of these egisren On theoiher hand, he segment ase value always esides n one of the segnent egisten: CS, DS,SS. or ES.

For instance. when an nstruciion acquisition sLes place, he source of the segmentbase value s always he code segment CS) register and tbe source of the offset value s

15

f@orrser

SEGMENTADOEESS

FigE 2-18 Generatine hysicaladdres. (Repnnbd by pemission ofIntel Cory., Copyrighl/Iltel Corp. 1981)

3 7 ceneratjng Memory ddress 47


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always he nstruction pointer (IP). This physical addrcss an be denoted as CS:IP. On theother hand, l the value of a variable s written to memory durirg executior of an nsiruc-tion, typicaly the segment ase value s specified by the data segnent (DS) register andthe offset value by the destination ndex (DI) register-that is. the physical address sgiven as DS:DI. A provision c^lled the seqment-o)e//ide lerr is used o change he seg-

ment ftom which ihe variable s accessed; or example, a prefix could be used o make adrra access ccm in which the segment ase s in the ES rcgister.

Another example s the stack ad&ess hat is needed when pushing parameters ntothe srack. This physical address s lbrned fton dle values of the segment ase n the stacksgment SS) egister and offset n dre stack pointer (SP) cgister and s described s SS:SP.

Remember hat the segmeni base address eFesents the starting location of the64Kb''te segrnent n menory-that is, the owest address yte n the segment. igure 2 19shows hat the offset identifies dre distance n b)1es hat the storage ocation of interestrcsides toln dis starting address. herefore, he lowest add.ess l4e in a segment as anoffset of000016, and the highest addrcss yte has an offset of FFFFI6.

Figure 2-20 shows how a segment base value n a segment egister and an offsetvalue are combined o form a physical address. he value n the segment egister s shiftedleft by four bit positions, with its LSBS illed with zeros. This gives a regnrt dddrrr thelocation where the segment tarts. The offset value s then added o the 16 LSBS of thesbifte.d egment alue. The result of this addition s the 20-bit physical address.

TIIe example n Fis. 2-20 rcpresents sesmetrt ase value of 123416 nd an offsetvalue of 002216. irst, let us exFess he segment ase value n binary folm. This gives

123416 0001001000110100,

8088/8086

B x -

f ;c l-

DS:BX

Data

DSr0000H

Highgsr ddressed yle

Lowstaddrssd yl

Figure 2-19 Boundariei of a sgnent.

Soih,fr'are fchitecture of rhe 8088 and 8086 l',4icroprocessors Chap. 28


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i t33i",i,

Figure 2-20 Physicai address alcurauon xam!ie. Reprinred r pemrs$on oftntet Corp..Copyngbrtnlel

axA IPLE2.7

Sbifting efr four positions and fiiling wirh zeros esutts n rhe segment ddress

00010010001 01000000, 12340i6

The offser n binary form is

002216 0000000000100010,

\dditrg the segmenr ddress nd the offset gives

0o01001000101000000, 00000000001000102 00010010001101100010,- 1236216: 12362H

11i. addrcss alcularion s done automarically within the 8088 microprocesso. ach ine: :.Fmory access s initiared.

.I:,-:"-:lo !" ".*::,,equired {o map o physicat ddress ocarion 02c3r6 f rhecon_=:'j oi .he correspo.ding egment egister re002A,"?

_'

-- nrT.t alue cdn be oblajned ) .hrlriog he conlerr\ ot rhe.'- Fflpo\ '^n\ and hensubLracringrum he phy,icai addre*.

002A0,6

\:-- i{5racdng. we ger the value of rhe offset:

002c3r6 02A016 002316

,\.ruly, many dilTerent ogical addresses map rc me same plysical address oca_:.:!: - m.nory. Simply changing he segment ase *1"" i, Ar",.g-*t *gi"r", _; il

segment egister efr byShifting left gives

z- i :.1 Generating a Memory Addfess 49


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corresponding ffset does his. The diagram n Fig. 2-21 demonsrrares his idea. Noricethat segment ase 002B16with otrset 001316maps o physical address 02C3r6 n mem-ory. However if rhe segment ase s changed o 0O2Cr6 wirh a new offset of 000316, hephysical address s stin 002C3 16.We see har rle physical address 02BH:0013H s equalto the physical address 02CH:0003H.

A 2, 12 THE SIACK

As indicaied earlier, he rrac* is implenented n the memory of the 8088 micfoprocessor.and it is used for temporary storage of information such as dara or adajresses. orinstance, when a call njfd.r'oa is execured, he 8088 automarically pusbes he currenrvalues n CS and IP onto the stack. Ar pan of rhe subrourirc, rhe contents of oiher regis,ters may also be saved otr the stack by execuritrg 6ft insfucrrorr (e.g., when the nst uc-tion PUSH SI is executed, t causes he conGnts of SI to be pushed onto the stack). Nearthe end of the subroutine, op i'Ltttucnons arcircftded.o pop vatues iom the stack backinto then conesponding ntemal registers e-g., POP SI causes he value at the rop of thestack o b popped back nto SI). At rhe endof the subrouine, a retum instructio catfsesthe values of CS and IP to be popped off $e srack and put back nto ihe intemal registerwhere they ofiginaly resided.

iII

____lFigurc 2-21 Reladonship betw@D ogical dd phyrical addresses-

(Reprinied by pmisior of Imel Corp., Copldeht/Inrel Corp. t9?9)

Software Architecture of the 8088 and 80a6 Microprocessors0 Chap. 2


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The stack s 64Kbytes ong and s organized rom a software point of view as 32Kwords. Figure 2-22 shows hat the segment base value in the SS register points to rhelowest address word in the cunent stack. The contents of rhe Sp and Bp register ofiserinto the stack segment f memory.

Looking at Fig. 2 22, we see hat SP contains an offset vatue har points ro a sror-

age ocation ir the cunent siack segmenr. he address btaind rom the contenrs of SSand SP (SSTSP) s the physical adihess of the last stonge location in the stack ro whichdata were pushed. This memory address s known as the top d the stoxk. At 6e ricro-computer's startup, he value n SP s initialized to FFFq6. Conbining this value with thecurrent value n SS gives he highest-addressed ord locarion n the srack SS:FFFEHFl]:.at s.6e bottom of the stack.

The 8088 can push data and address nfomation onto rhe srack rom its inremalregisters or a storage ocation n memory Data ransferred o and iom the srack are word-wide, not byte-wide. Each ime a word is to be pushed onro he top of rhe stack, he valueitr SP s first automatically decremented y two, and then the contents of the register arewritten into the stack part of memory. Therefore, he srack grows down in memory iomthe bottom of the stack, which conesponds o the physical address SS:FFFEH, oward heend of the stack, which corresponG o the physical address btained rom SS and offserfiXjor6 SS:0000H).

When a value is popped iom the rop of rhe stack. the revene of this sequenceocculs. The physical address efined by SS and SP points ro the ocarion of the ast valuepushed onto the stack. ts contents are first popped off rhe stack and put inro ihe specificregister within the 8088; then SP is

automatically ndemented by two. The top of thenack then corresponds o the address f the previous value pushed onro he stack.

SS:FFFEH

4088/8046

T_ ^: --_l

r ^------

SS:SP

SS:0000H

-*. Z.l2 ihe stack

Figu.e 2-22 Stack segEent ofmemory.

5 l


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27/31

. .kt us next ook ar an example n which srack data are popped iom the stack backI: l..l:cl:'. ff"TI il.chhe] ere ushed. igr,. _z+ t,ioa|* *,. .p.,"i,""--r"r r g . - 1 4 t , ) . L n e ( l a c k i ' c b o q n r o b e i a r h e , t l e L l a r r e . u t r e d o u e r o o u r p r i o i p t S

llTlli:].h" '' l" .q,n. 0006,". s equal, 0s ". fie ddre$ ar he ,p or,r,. ".requals_ru)6rb- nd he wordat the op ol Ue suck equaL 2J4r6.Figure 2-24(b) shows what happens when thelnsmction; pop

AX andpop

Bxare executed n that order Execution of the first instrucrion causes dre 80g8 to read theyalue from rhe op of the stack and put ir into the AX ..gir,", * f Z:+,". r.l"rr, Sp i, ln"*-menred o gi\e0008 6 and dnolber eadoperar;on \ in;riarea rom Lteyact. fn ."efonieao on^espond,o lhe pop BX in5rucrioo. nd r causes he alue BB{A-6ro be oadedtnto the BX regisrer. Sp is incremented nce more and r"* eqr"ts 00OA,r. h";f;;;new rop of stack s at address 105A,..

In Fig.2-24rbrwe.ee rhar re latues erd our ot addre.ses O5o, . nd 1058,"Rmain at rhese ocalions, urosy, 1s";6.u, locdlionc hal are dbove h. iq;""il. ;;i:derefore, they no longer representatid stack dara. f new infonnation is^pustea oGsiack. hese vaiues are written over,

I

II

II

II

J

exl-iT3.l-1

1062

r060

i05c

105A105l

axfi-fi]..--.I

s'f;T;l-r iiir062?060

l05E

106C

Figure 2-X .. , Srd.t iJst pnor o pop opetulion.ReDrinred ) pemi$ion orInrelCorp-Coplriehutnr, Corp tets;ft)Srskafte, rheercu;i;norlllepop

m,?'.ffi"3i^*"*^ rxepirredv emi"'onf ntercorPopvrshr/

:E 2 t2 ft e Stack

00

66

a8 99

12

89 AB

c0

5t


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t l

I l:qolf ffiili Figure -2s Ioaodre"""pee1l | , RepruLed) pemi* ,on or bat 1---------------Jor ( o!.. cop)ri8h,/tnret orp. o-ar

Any number of stacks may exist in an 8088 nicrocomputer. Simply changing hevalue in the SS register brings in a new stack. For instance, executing he instructionMOV SS, DX loadsa new value iom DX into SS. Althoughmany stacks an exist,onlyone can be active at a time.

A 2.I3 INPUT/OUTPUTDDRESS PACE

The 8088 has separate memory and npuroutput (UO) ad&ess spaces. The 1/o adl"Jjrydce it the place where I/O interfaces, such as pdnter and nonitor ports, are imple-mentd. Figure 2-25 shows a map of dle 8088's I/O ad&ess space. Notice that ihisaddress ange s from 000016 o FFFFI6. This represents ust 64Kbyte addresses; here-fore, unlike memory, /O addresses re only 16 bits long. Each of these addresses orre-sponds o one byte wide I/O port.

The part of the map from address 00016 hrough 00FFr6 s referred o as pdSe 0.Ce.tain of the 8088's I/O instructioDs can perform only input or outpul data-tansferoperations o l/O devices ocated n this part of rhe I/O ad&ess space. Other /O instruc-tions can nput or outpul data or devices ocated anywhere n the I/O address pace. /Odata transfers can be byte-wide or $,ord wide. Notice that the eight locations fromaddress 0F816 hrough 00FFr6 are specified as reserved by lntel Corporation and should

REVIEW ROBLEMS

Section .I1. Name he two intemal Focessing units of the 8088.2. Wlich processing unit of the 8088 s the interface o the outside world?3. wllat arc ihe length of the 8086's address us and data bus?

4, How large s the nstruction queue of the 8088? The 8086?5. List the elements of the execution unit.

Section .26, Wlat is the pur?ose of a software model for a microprocessor?7. Wllat must an assembly-language ograr ner know aboui the rcgisren within the

8088 miffoprocessor?

54 Softwarc Architecture f the 8088 and 4086 MicroDfocessors Chao. 2


29/31

8. How rnany registers are ocated widrin the 8088?9. How arge s the 8088's memory ddress pace?

10. How arge s the 8086's /O address pace?

Section .311. What s the highest address n rhe 8088's memory address pace? he owesr address?D. fs memory n the 8088 microprocessor rganized as byts, words. or double words?13, The contenls f memory ocarion 000016 re FFr6,and hose r 8000116 re 0016.

wllat is .he data word stored a1address 000016? s the word ali$ed or misaligned?11. Wlat is the value ol the double word srored n nemory starting at address 000316

if the contents f mernory oca.ions 0003r5, 000416, 0005 6, and 8000616 re1116, 216, 316, nd4416, espectively?s this an exampie f an aligned ouble vordor a misaligned double word?

15. Showhow he word ABCD16s srored n memory tarring t address A00216.s theword aligned r misaljgned'i

16. Show how the double word 123,1567816s srored n memory starring t addressA00l16. s the doubleword aligned r misaligned?

i:ct ion 2.4:- . Lisi fivedata ypes Focessed irectlyby rhe 8088.:( E\press

each of the signed decimal ntegers hat fo1low as eirher a blre- or wordle\adecimal number use 2\-complemenr notation or negative nurnbers).,at + 121, b r 1 0' c ) - 1 2 8' d r + 5 0 0

:r . io\. would he nteger n problem 18(d) be siored n memory starring r address\r:llor6?

L :rn soutd the decimal umber 1000 e expressed or processing y the 8088?::, :!:rejs the decimal nurnbers hat follow as unpacked nd packed BCD bytes.

a , t 9b . ! s

: i-; liould the BCD number n problen 21(a) be srored n memory srarring l.i-..-, 0800016? Assune hat the leasi significant igir is stored a1 rhe lower

= :-::i srarements coded nASClI by the ollowing binary rrings?

t 0 0 l 1 l 01000101101100010101000100000i00t001

t 5


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24. How would the decirnal number 1234 be coded n ASCII and stored n memory start_ing at address C00016? Assume hat the least significant digit is storcd at the oweraddressed memory ocation.)

Section .525. How large s a memory segment n the 8088 midoprocessor?26. W}ich of the 8088's ntemal registe$ are used or memory segmentation?27. Whar register defines he beginning of the cunent code segment n memory?28. Wtat is the ma-dmum amount of memory hat can be active at a given trme in the

8088 microprocessor?29. How much of the 8088's active memory s available as general-purpose ata storage

Section .630. Wlut is the dedicated use of the part of the 8088's address space ton 0000016though 0007F16?

31. What is the address ange of the general-use art of the memory adahess pace?

32. Which part of the 8088's memory address pace an be used o siore he nstruciionsof a Plogram?

33. what is stored at address !FF0r6?

Section .734. What is the function of the instruction pointer register?35. Provide an ovefliew of the fetch and the execution of an nstruction by the 8088.36. What happens o the value n IP each ime the 8088 completes an insruction fetch?

Section .837. Make a list of the general-pur?ose ata egisters of the 8088.

Al8.Ho\ ie $e word valueof a data esister abeled:

- - 39. Hou ire the upper nd ower byres f a dala egister noledl40. Name wo dedicated perations assigned o the CX register.

Section .941. Wlat kind of inforrnation s slored n the pointer and ndex registers?42. Name he two pointer registers.43. For which segment egister are he contents of the pointer registen used as an offset?,l4. For which segment egister are he contents of fhe index registen used as an offset?45, what do Sl and DI stand or?46. Wlat is the difference between SI and Dl?

Sect ion .1047. Categorize ach lag bit of the 8088 as either a contol flag or a flag that monitors he

status due to execution of an nsiluctlon.48. Describe he function of each status lag.

Software rchitecture f the 8088 and 8086 Microprocessors chap. Z6


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49. How does software use a status lag?50. W}lat does TF stand or?51. Which flag determines whether he adairess or a srring operation s incremented or

52. Can the state of the flags be modified rhrough so{tware?

Section . I53, What s the word ength ofthe 8088's hysical ddress?54. Wlat rwo adalrcss lements are combined o form a physicat adahess?55. Calculate he value of each of the physicat addresses har fo ows. Assume alt num,

bers are hexadecimal umbe$.(a) 1000:i234(b) 01oo:ABCD

(c) A200|12CF(d) B2C0:FAI256. Find the unknown value for each of the following physical addresses. ssume all

numbers are hexadecimal umben.(a) A000:? A0123(b) ?:r4DA = 23sDA(c) D765:? = DABCo(d) ?tCD2l : 32D21

5t. If ihe current values n the code segment egister and rhe instrucrion pointer are0200i6 and 0lAC16. espectively, whar physical ad&ess s used n the next nstrucrionfetch?

3 A data segmenr s ro be located tom address A000016 o AFFFFT6.Wh;i vatue mustb loaded nto DS?

3). If the data segment egister contains he value ound n problem 58, what value mustbe toaded nto DI if it is to point ro a destinarion perand tored n memory at addressr.12346'l

Section . 2aa- What is the function oi the stack?aL lf the curent vatues n the stack segmenr egister and srack pointer are C000r6 and

FF00r6, espectively, what s the address f the current oD of the srack?C1 For the base and offser addresses n p.oblem 61, how many words of data are cur,

Eotly held in the s.ack?af. Show how the value EEl Ir6 ftom register AX would be pushed onto the rop of rhe

sack as t exists n Foblem 61.

Section 2.13al kr fte 8088 microprocessor are the inpu/ourput and memory addrcss paces om,

ffi or sepamte?G- Haa lnge is the 8088's yO address pace?5, E tE n3me s given ro rhe pan of ihe I/O add.ess pace tom 000016 brough 00IrF16?

Chapter 2 Textbook 8086

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