Chapter 12 Field-Effect Transistors 場效電晶體
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Transcript of Chapter 12 Field-Effect Transistors 場效電晶體
Chapter 12Field-Effect Transistors 場效電晶體
Field-Effect Transistors (FETs)•FET (場效電晶體 ) 是利用電場來控制電
流的大小,而且組成電流的載子僅限一種極性,即電洞或 是自由電子 。•Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET, 金氧半場效電晶體)可分為 NMOS ( 以電子為電流載子 )與PMOS( 以電洞為電流載子 ) 。•MOSFET 包含 source ( 源極 )、 gate (閘極 )、 drain( 汲極 )及 body( 基座 ) 。
12.1 NMOS AND PMOS TRANSISTORS
NMOS Transistor (n-p-n)
(M, 金 ) (O, 氧 )
(S, 半 )
(source 源極 )(gate 閘極 ) (drain 汲極 )
(Body 基板 )
氧化物為絕緣體,沒有電流能進入閘極端;控制閘極電壓能夠調整汲極到源極的電流場效
NMOS (n-channel MOS)
n-p-n
•NMOS 之 source ( 源極 )與 drain( 汲極 )為 n-type 半導體, body( 基座 ) 為 p-type 半導體, gate ( 閘極 ) 為導體 。
NMOS 的運作 (Operation)•NMOS 的運作可分為三區 (region)
•Cutoff Region ( 截止區 )
•Triode Region ( 三極區 ) or Linear Region ( 線性區 )
•Saturation Region ( 飽合區 )
toGS Vv
toGS Vv toGSDS Vvv and
toGS Vv toGSDS Vvv and
Operation in the Cutoff Region•當閘極 (gate) 與源極 (source) 間電壓 vGS =0 ,兩個 pn接面 (body-source) 與 (body-drain) 可視為兩個方向相反的二極體,此時 MOSFET 為截止 (cutoff) 。
•當閘極 (gate) 與源極 (source) 間電壓 vGS 逐漸上升到>Vto (threshold voltage, 臨限電壓 ) 時,則 NMOS 才會開始導通。
toGSD Vvi for 0
Operation in the Triode RegiontoGS Vv toGSDS Vvv and
•當閘極 (gate) 帶正電時,可逐漸吸引自由電子聚集在絕緣層的下方, 並將電洞推離絕緣層下方。
toGSDS
DS
toDSGS
DS
toGD
Vvv
vVvv
vVv
0
00
Operation in the Triode RegiontoGS Vv toGSDS Vvv and
•當閘極 (gate) 與源極 (source) 間電壓 vGS 逐漸上升到>Vto (threshold voltage, 臨限電壓 ) ,,且在 drain和 source之間加有電壓 vDS ,則形成 n-type 通道 (channel) ,,通道中的自由電子受到外加電場的驅動,形成汲極電流(drain current)iD ,其方向從 drain 流向 source ,和通道中的電子流方向相反。•當 vDS 很小時, iD與 vDS 成正比, 亦與 vGS - Vto 成正比。•由於有氧化絕緣層,故閘極電流 iG = 0。
toGDtoDSGStoGSDS VvVvvVvv
Operation in the Triode Region•In the triode region, the NMOS behaves as a resistor connected between drain and source, but the resistance decreases as vGS increases.
,2 2DSDStoGSD vvVvKi 2
KPL
WK
Device parameter
0, if vDS~0
Operation in the Saturation Region
•當 drain和 source 之間電壓 vDS≥ vGS - Vto(or vGD≤ Vto) 則n-type 通道在 drain 端寬度變為 0 , vDS 再變大, iD 不再上升, 稱為飽合區。
toGS Vv toGSDS Vvv and
Operation in the Saturation Region
2toGSD VvKi
Boundary between Triode and Saturation Regions
At boundary, 使得 n-type 通道在 drain 端寬度剛好為 0
toGD Vv
toDSGS Vvv
代入 I-V equation in saturation region 2toGSD VvKi 2DSD Kvi )( DStoGS vVv
Boundary between Triode and Saturation Regions
將 代入 I-V equation in triode region
DStoGS vVv
22 DSDStoGSD vvVvKi
2222 DSDSDSD KvvvKi
兩者結果一樣。
boundary
Example 12.1
A NMOS transistor W=160um, L=2um, KP=50uA/V2, and Vto=2 V. Plot the drain characteristic curves to scale for vGS=0, 1,2, 3, 4, and 5 V.
1. 求 K2/2
2)( VmAKP
LWK
2. 求 boundary
232 102 DSDSD vKvi
3. 求 saturation currents
232 )2(102)( GStoGSD vVvKi
Vvmi GSD 5for A 18
Vvmi GSD 4for A 8 Vvmi GSD 3for A 2
Vvmi GSD 2for A 0
4. Plot characteristics in the triode region (parabola 拋物線 ). ,2 2
DSDStoGSD vvVvKi
PMOS•PMOS 之 source 與 drain為 p-type 半導體, body為 n-type 半導體, gate ( 閘極 )為導體 。•以電洞為電流載子。
MOSFET Summary
12.2 LOAD-LINE ANALYSIS OF A SIMPLE NMOS
AMPLIFIER
12.2 LOAD-LINE ANALYSIS OF A SIMPLE NMOS
AMPLIFIER•VGG (dc source) 對 NMOS 產生偏壓(bias) ,決定操作點, 當 ac input 在操作點附近隨時間變化,導致 vGS, iD 亦隨時間改變。
•iD 隨時間改變,導致 RD 亦上的壓降隨時間改變, 使得 vDS 產生 ac output 。4)2000sin()()( tVtvtv GGinGS KVL
Load-line equation )()( tvtiRv DSDDDD
)()A)((20 tvmti DSD
)A20,V0( miv DDS )A0,V20( miv DDS
Load-line 兩端點
•Quiescent operation point (Q point) is at vin=0.
V4 GGGS Vv
A9mIDQ
4)2000sin()()( tVtvtv GGinGS
B)V(point 3A)V(point 5
min
max
GS
GS
VV
VDQ=115 V
7 V
Distortion ( 變形 )
1 VVGSQ=4
Distortion
Distortion is due to that the characteristic curves for the FET are not uniformly spaced.If a much smaller input amplitude was applied we would have amplification without appreciable distortion.
Amplifier AnalysisAmplifier analysis has two steps: 1. Determine the Q point. 2. Use a small-signal equivalent circuit to determine impedances and gains.
12.3 Bias Circuits
The Fixed- Plus Self-Bias Circuit
GV ?DSv
The Fixed- Plus Self-Bias Circuit1. Thévenin equivalent
21
2
RRRVV DDG
GV
21
21
RRRRRG
2. KVL
DsGSG iRvV
GSv
Di)0( Gi
3. Usually, transistor operates in saturation region
2)( toGSD VvKi
4. Load Line Analysis iD vs. vGS
DsGSG iRvV
2)( toGSD VvKi saturation toGS Vv
offturn toGS Vv
5. Determine vDS
Di
DsDDDDS iRRvv )(
Example 12.2
Analyze the following circuit. The transistor KP=50uA/V2, Vto=2 V, L=10um, W=400um
1. Determine K
2/12
)( VmAKPL
WK
2. Thévenin equivalent
VRR
RVV DDG 513
12021
2
3. Determine VGSQ
DQsGSQG IRVV
2)( toGSQsGSQG VVKRVV
2)( toGSQDQ VVKI
0)21( 22 KR
VVVVKR
Vs
GtoGSQto
sGSQ
0148.2630.32 GSQGSQ VV
744.0or 886.2GSQV×
4. IDQ & VDSQ
mAVVKI toGSQDQ 784.0)( 2
VIRRVV DQsDDDDSQ 2.14)(
12.4 SMALL-SIGNAL EQUIVALENT CIRCUITS
tiIti dDQD
tvVtv gsGSQGS
Small signal (ac)
Small signal (ac)
satutationfor )( 2toGSD VvKi
2])([)( togsGSQdDQ VtvVKtiI
)()()(2)( 22 tKvtvVVKVVK gsgstoGSQtoGSQ
To determine vgs(t) vs. id(t)
SMALL-SIGNAL EQUIVALENT CIRCUITS
)()()(2)()( 22 tKvtvVVKVVKtiI gsgstoGSQtoGSQdDQ
2)( toGSQDQ VVKI
At Q point
)()()(2)()( 22 tKvtvVVKVVKtiI gsgstoGSQtoGSQdDQ
))()()(2 ( 2 tKvtvVVK gsgstoGSQ 0
DQ
DQ
toGSQm
ILWKP
KI
VVKg
/2
2
)(2
)()()(2)( tvgtvVVKti gsmgstoGSQd
2KP
LWK