Chapter 11: System Design Methodology

Chapter 11: System Design Methodology

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 11-1


Prof. Soo-Ik Chae



Objectives

After completing this chapter, you will be able to: Describe the features of finite-state machines (FSMs) Understand how to model FSMs Describe basic structures of register-transfer designs Describe basic structures and features of algorithmic-state

machine (ASM) charts Understand how to model ASMs Describe the features and structures of datapath and control

designs Describe the realizations of RTL designs Understand the relationship between iterative logic and

FSMs



Finite-State Machines (FSMs)

A finite-state machine (FSM) M is a quintupleM = (I, O, S, δ, λ)

where I, O, and S are finite, nonempty sets of inputs, outputs, and states, respectively.

δ: Ι × S → S is the state transition function;λ is the output function such that

λ : I × S → O for Mealy machine;λ : S → O for Moore machine.

The design issues of a finite-state machine used in digital systems are to compute both the state transition and output functions from inputs and (present) states.



Types of Sequential Circuits

Mealy machine

Moore machine

Combinationalcircuit

DCK

Q

Q'

DCK

Q

Q'

DCK

Q

Q'

OutputsInputsCombinational

circuit

Clock

Next state

Present state


DCK

Q

Q'

DCK

Q

Q'

DCK

Q

Q'

OutputsInputs


Clock

Next state

Present state



State Encoding

Common FSM encoding options: One-hot code Binary code Gray code Random code

AState

BC

Binary000110

D 11

Gray One hot00011110

1000010000100001

One-hot encoding is usually used in FPGA-based design, because there are a lot of registers in theses devices.



How to Realize an FSM?

Explicit fsm: States are declared explicitly. It is so easy to write clearly and correctly. Every synthesis tool supports this type FSM. Almost all FSMs are written in this type.

Implicit fsm: States are not declared explicitly. The synthesis tools infer the state from the activity within a cyclic (always …) behavior. It is so hard to write clearly and correctly. Not every synthesis tool supports this type FSM.



(Explicit) FSM Realization

An explicit fsm is usually called FSM for short. Two major realization issues:

• state-register declaration and update• the computation of both next-state and output functions

State register can be declared as one register: harder to follow and model. two registers: easier to follow and model.

Output and next state functions: continuous assignment function always block a combination of the above



FSM Modeling Styles

Style 1: one state register part 1: initialize and update the state register

always @(posedge clk or negedge reset_n)if (!reset_n) state <= A;else state <= next_state (state, x) ;

part 2: determine next state using functionfunction next_state (input present_state, x)

case (present_state ) … endcase endfunction

part 3: determine output functionalways @(state or x) case (state) … or

assignment statements



FSM Modeling Styles

Style 2: two state registers part 1: initialize and update the state register

always @(posedge clk or negedge reset_n)if (!reset_n) present_state <= A; else present_state <= next_state;

part 2: determine next statealways @(present_state or x) case (present_state ) … orassignment statements

part 3: determine output functionalways @(present_state or x) case (present_state ) … orassignment statements



An FSM Example --- A 0101 Sequence Detector

Design a finite-state machine to detect the pattern 0101 in the input sequence x. Assume that overlapping pattern is allowed.

A B C D

1/0

0/0

0/0

1/0

1/0

0/0

1/1

0/0

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11

Clock

Input

Output

0 1 0 1 0 0 1 0 1 0 1 0

0 0 0 1 0 0 0 0 1 0 1 0

Sequencedetector Output (z)

clock (clk)

Input (x)

State diagramTiming chart

Block diagram

0 01 010



An FSM Example --- The Sequence Detector: Style 1a// a behavioral description of 0101 sequence detector – style 1a// Mealy machine example --- Using only state register and one always block.module sequence_detector_mealy (clk, reset_n, x, z);input x, clk, reset_n;output wire z;reg [1:0] state; parameter A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11;// the body of sequence detector --- Using only one always block.always @(posedge clk or negedge reset_n) begin

if (!reset_n) state <= A; else state <= fsm_next_state(state, x); endfunction [1:0] fsm_next_state (input [1:0] present_state, input x);reg [1:0] next_state;begin case (present_state)

A: if (x) next_state = A; else next_state = B; B: if (x) next_state = C; else next_state = B; C: if (x) next_state = A; else next_state = D; D: if (x) next_state = C; else next_state = B;

endcasefsm_next_state = next_state;

end endfunctionassign z = (x == 1 && state == D);endmodule



An FSM Example --- The Sequence Detector: Style 1a

un1_x

un1_x_2 z

un1_state_1

fsm_next_state_0.un12_state

fsm_next_state_0.un18_state

un1_x_3

un1_un12_state

un1_x_4

un1_un18_state

state_3[1]

edededededed

state[1:0]

R

[0] [0][1]

[0]

[0][1]

[0][1]

0

0

1

0

0

1

[1:0]Q[1:0]D[1:0]z

reset_nclk

x



An FSM Example --- The Sequence Detector: style 1b// a b ehavioral description of 0101 sequence detector: style 1b // Mealy machine example --- Using only one state register and two always blocks.module sequence_detector_mealy (clk, reset_n, x, z); input x, clk, reset_n;output reg z;// Local declarationreg [1:0] state; parameter A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11;// the body of sequence detector --- Using two always blocks.always @(posedge clk or negedge reset_n) begin

if (!reset_n) state <= A; else state <= fsm_next_state(state, x); endfunction [1:0] fsm_next_state (input [1:0] present_state, input x);

…. Same as that of style 1a end endfunction// evaluate output function zalways @(state or x) case (state)

A: if (x) z = 1'b0; else z = 1'b0; B: if (x) z = 1'b0; else z = 1'b0;C: if (x) z = 1'b0; else z = 1'b0; D: if (x) z = 1'b1; else z = 1'b0;

endcaseendmodule



An FSM Example --- The Sequence Detector: style 2

// a behavioral description of 0101 sequence detector: style 2// Mealy machine example --- using two state registers and three always blocks.module sequence_detector_mealy (clk, reset_n, x, z);input x, clk, reset_n;output z;// local declarationreg [1:0] present_state, next_state; // present state and next statereg z;parameter A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11;// initialize to state A and update state registeralways @(posedge clk or negedge reset_n)

if (!reset_n) present_state <= A;else present_state <= next_state; // update present state




// determine next statealways @(present_state or x)

case (present_state)A: if (x) next_state = A; else next_state = B;B: if (x) next_state = C; else next_state = B;C: if (x) next_state = A; else next_state = D;D: if (x) next_state = C; else next_state = B;

endcase// evaluate output function zalways @(present_state or x)

case (present_state)A: if (x) z = 1'b0; else z = 1'b0;B: if (x) z = 1'b0; else z = 1'b0;C: if (x) z = 1'b0; else z = 1'b0;D: if (x) z = 1'b1; else z = 1'b0;

endcaseendmodule




un1_x

z

un1_present_state_1

un1_present_state_2 un1_present_state_3

un1_present_state_4

un1_present_state_5

next_state[1]

ededed

present_state[1:0]

R

[0][1]

[0][1]

[1][0]

0

[0]

1

[1:0]Q[1:0]D[1:0] z

reset_n

clkx



An FSM Example --- The Sequence Detector

Both modeling styles, using one state register or two state registers, yield the same circuit as shown below.

Gate-level result

INV

reset_c_i

LUT1_L_1

x_c_i

LUT3_L_C2

G_10_0

0

1

LUT3_80

z_0_and2

BUFGP

clk_ibuf

OBUF

z_obuf IBUF

reset_ibuf

IBUF

x_ibuf

FDC

present_state_h.present_state[0]

FDC

present_state_h.present_state[1]

I O

[1]

[0]

[1]

[0]I O I O

I O

I O

DCCLR

[0]Q DCCLR

[1]Qz

reset

clk

x

statemachine

present_state[3:0] z

I[3:0]Q[3:0]C

R[3]

zresetclk

xRTL result

Although we declare two state registers, the synthesis tool only yields one state register.

Use Synplify with FSM compiler option.



Coding Style

State name should be described using parameters: parameter or localparam.

Combinational logic for computing the next state should be separated from the state registers, i.e., using its own always block or a function.

The combinational logic of the output function should be implemented with a case statement.



Example: An Implicit FSMs

// an implicit FSM examplemodule sum_3data_implicit(clk, data, total);parameter N = 8;input clk;input [N-1:0] data;output [N-1:0] total;reg [N-1:0] total;// we do not declare state registers.always begin

@(posedge clk) total <= data;@(posedge clk) total <= total + data;@(posedge clk) total <= total + data;

endendmodule

Due to the difficulty of writing a correct implicit FSM program, it is not suggested to use this method to realize an FSM circuit.



Example: An Implicit FSMs

[1:0][2]

un1[2:0]

un1_total[7:0] +

total_9[7:0]

0

1 total[7:0]

[2:0]Q[2:0]D[2:0]

[7:0][7:0]

[7:0]

[0]

[7:0][7:0]

[7:0][7:0]Q[7:0][7:0] D[7:0] total[7:0][7:0]

data[7:0] [7:0]

clk



Example: An Explicit FSMs

// an explicit FSM examplemodule sum_3data_explicit(clk, reset, data, total);parameter N = 8;input clk, reset;input [N-1:0] data;output [N-1:0] total;reg [N-1:0] total;reg [1:0] state; // declare state registers explicitlyparameter A = 2'b00, B =2'b01, C = 2'b10;always @(posedge clk)

if (reset) state <= A; elsecase (state)

A: begin total <= data; state <= B; endB: begin total <= total + data; state <= C; endC: begin total <= total + data; state <= A; end

endcaseendmodule



Example: An Explicit FSMs

Both implicit and explicit fsm have the same synthesized results.

statemachine

state[2:0]

un1_total[7:0] +

total_8[7:0]

0

1

total[7:0]

I[2:0]Q[2:0]C

0 R

[7:0][7:0]

[7:0]

[0]

[7:0][7:0]

[7:0][7:0]Q[7:0][7:0] D[7:0]

Etotal[7:0][7:0]

data[7:0] [7:0]

resetclk



Register-Transfer-Level Design

Features of register-transfer-level (RTL) designs1. are sequential machines.2. are structural.3. concentrate on functionality, not details of logic design.

Two types of register-transfer-level design are ASM (algorithmic-state machine) chart Datapath and controller (DP + CU)



ASM Charts (or SM charts)

ASM (algorithmic state machine) charts specify RTL operations on the per-cycle basis. show clearly the flow of control from state to state. are very suitable for data path-controller architectures.

An ASM chart is composed of State block Decision block Conditional output block



ASM State Blocks

A state block specifies a machine state and a set of unconditional RTL

operations associated with the state. may execute as many actions as you want and all actions

in a state block occur in parallel. occupies a clock period along with its related operations.

Output or operations

StateassignmentState name



Decision Blocks

A decision block describes the condition under which ASM will execute

specific actions. selects the next state based on the value of primary input

or present state. can be drawn in either two-way selection or multi-way

selection.

Two-way selection Multi-way selection

Condition10

(Valid)(invalid) Condition

Condition10

(Valid)(invalid)



Conditional Output Blocks

A conditional output block describes the RTL operations executed under conditions

specified by one or more decision blocks. receives signals from the output of a decision block or the

other conditional output block. can only evaluate present state or primary input value on

present cycle.

Output or operation



ASM Blocks

An ASM block has exactly one entrance path and one or more exit paths.

Serial testing Parallel testing

B00A

← B + 3

x1 x2

c ← 0 d ← 5

0

1

1

0

B

x1

1

00A

x2

c

0

← 0

← B + 3

d ← 5

1

0



ASM Charts --- ASM Blocks

ASM blocks An ASM block contains one state block and a serial-

parallel network of decision blocks and conditional output blocks.

Each ASM block describes the operations executed in one state.

The basic rules for constructing an ASM chart1. Each state and its associated set of conditions must

define a unique next state.2. Every path of the network of conditions must terminate

at a next state.3. There cannot exist any loop in the network of conditions.



Invalid ASM Blocks

Undefined next state: why? Try to explain it!

Undefined exit path: why? Try to explain it!

B00A

← B + 3

x1

x2c ← 0

d ← 50

1

1 0

01B10C

B00A

← B + 3

x1 x2

c ← 0 d ← 5

0 1 1 0

01B10C

Rule 1?

Rule 3?



ASM Modeling Styles

Style 1a: one state register and one always block. (Not a good style!!!) part 1: initialize, determine, update the state register, and

determine RTL operations.always @(posedge clk or negedge start_n)

if (!start_n) state <= A; else state <= …; Style 1b: one state register and two always blocks part 1: initialize, determine, and update the state register.

always @(posedge clk or negedge start_n)if (!start_n) state <= A; else state <= …;

part2: determine RTL operationsalways @(posedge clk) case (state ) … or

assignment statements



ASM Modeling Styles

Style 2: two state registers and three always blocks (the best style !!!!) part 1: initialize and update the state register

always @(posedge clk or negedge start_n)if (!start_n) present_state <= A; else present_state <= next_state;

part 2: determine next statealways @(present_state or x) case (present_state ) … orassignment statements

part 3: determine RTL operationsalways @(posedge clk) case (present_state ) … orassignment statements



An ASM Example --- Booth Serial Multiplier

Problem Specification: Booth multiplication algorithm

At ith step:

Assume that: 0121 xxxxX nn −−=

0121 yyyyY nn −−=

• Add 0 to partial product P if• Add Y to partial product P if• Subtract Y from partial product P if• Add 0 to partial product P if

001 =−ii xx

111 =−ii xx

011 =−ii xx101 =−ii xx




mcand = 13Hmp = 77H 0 0 0 00 0 0 0 0 1 1 10 1 1 1

acc mp mp(0)

0

cnt

7 acc acc - mcand0 0 1 10 0 0 1-

1 1 0 11 1 1 01 1 0 11 1 1 01 0 1 1 10 1 1 1 7 right shift acc:mp

1 1 0 11 1 1 01 0 1 11 0 1 1 1 61 1 0 11 1 1 01 0 11 1 0 1 1 1 5

0 0 1 10 0 0 1+

0 0 0 00 0 0 1

acc acc +mcand

0 0 0 00 0 0 1 1 0 10 00 1 1 1 4

32

0 11 0

1 1 0 11 0 1

110 1 1 1

1 0 1 01 1 1 0 1 0 111 0 1 11

0 0 1 10 0 0 1-

1 1 0 11 1 1 1 0 1 0 1 0 1 0 11 10 0 1 10 0 0 1+

0 0 10 0 1 0000 0 10 0 1 00 1 0 1 0 1 0 1 0008D5H

right shift acc:mpright shift acc:mp

right shift acc:mp

right shift acc:mpright shift acc:mpright shift acc:mpacc acc +mcand

right shift acc:mp

1 01 1 1 011




ASM chart approach

finish1

mcand multiplicand0

idle

load

mp multiplieracc 0cnt w - 1

cnt != 01

mp[1:0]

acc acc + mcand acc acc - mcand

cnt cnt - 1{acc, mp} {acc[n-1], acc, mp}shift_right

01 10

0011

0

compute

finish 1



An ASM Example --- Booth Serial Multiplier: Style 2 (1/3)// Booth multiplier: style 2 --- using three always blocksmodule booth (clk, start_n, multiplier, multiplicand, product, finish);parameter W = 8; // word size parameter N = 3; // N = log2(W)input clk, start_n;input [W-1:0] multiplier, multiplicand;output [2*W-1:0] product;wire [2*W-1:0] product; reg [W-1:0] mcand, acc; reg [N-1:0] cnt; reg [W:0] mp; // one extra bitreg [1:0] present, next;output reg finish; // finish flagparameter idle = 2'b00, load = 2'b01, compute = 2'b10, shift_right = 2'b11;// the body of the w-bit booth multiplier// initialize to state idlealways @(posedge clk or negedge start_n)

if (!start_n) present <= idle; else present <= next;



An ASM Example --- Booth Serial Multiplier: Style 2 (2/3)

// determine next statealways @(*) case (present)

idle: if (!finish) next = load; else next = idle;load: next = compute;compute: next = shiftright;shiftright: if (cnt == 0) next = idle; else next = compute;

endcase// execute RTL operationsalways @(posedge clk) begin

if (!start_n) finish <= 0;case (present)

idle: ;load: begin

mp <= {multiplier,1'b0}; mcand <= multiplicand; acc <= 0; cnt <= W - 1;

end



An ASM Example --- Booth Serial Multiplier: Style 2 (3/3)

compute: begincase (mp[1:0])

2'b01: acc <= acc + mcand;2'b10: acc <= acc - mcand;default: ; // do nothing

endcase endshift_right: begin

{acc, mp} <= {acc[W-1], acc, mp[W:1]}; // arithmetic shift rightcnt <= cnt - 1; if (cnt == 0) finish <= 1;

endendcase

endassign product = {acc, mp[W:1]};endmodule



An ASM Example ---Booth Serial Multiplier

[7:0][8:1]

[7:0]=0

[0][8:1]

[7][7:1]

mcand[7:0]

acc16

acc15 mp_5[8:0]

0

1

un1_acc15

un1_acc15_1[0]

0

1

un1_mcand_1[7:0]

0

1

un1_state[0]

edededed

mp[8:0]

un1_state_1

un3_cnt[3:0] +

un1_state_2

cnt_5[3:0]

0

1

cnt[3:0] finish9

un1_acc[7:0]

+

un1_state_4 finish

R

statemachine

state[3:0]

acc_9[7:0]

ededed acc[7:0]

[7:0]Q[7:0][7:0] D[7:0][1] E

[0][1]

[1][0]

[1]

[8:0]1

0

[7:0][7:0]

[7:0]

[0]0

[1]1

[2]0

[3]1

[8:0]Q[8:0][8:0] D[8:0]E

[2]

[3:0][3:0]

1111

[0]

[1]

[3:0][3:0]

1000

[3:0]Q[3:0][3:0] D[3:0]E

[0][1][2][3]

[7:0]

[7:0][7:0]

[3] Q1 DE

I[1:0][3:0]Q[3:0]C

R

[1]0*8

[2][7:0]

[7:0]

[3]

[7:0]Q[7:0][7:0] D[7:0]E

finish

product[15:0]

ultiplicand[7:0] [7:0]

multiplier[7:0] [7:0]

start

clk



An ASM Example ---Booth Serial Multiplier



dp+cu Architecture Design

clk

Data output

DataRead/write

Datapath

Controller

Control signals Status

Data input

Memory



dp+cu Architecture Design

A digital system can be considered as a system composed of three major parts: data path performs all operations that are required in the

system. memory temporarily stores the data used and generated

by data path unit. control unit controls and schedules all operations

performed by the data path unit.



A dp+cu Approach --- Booth Serial Multiplier

Datapath and controller units can be easily derived from ASM chart (ASM modeling style 2). Datapath part corresponds to the registers and function

units in RTL operation block (part 3). Controller corresponds to the first and second always

blocks (part 1 and 2), which determines the next state function, and the control signals in the RTL operation block (part 3).



A Three-Step Paradigm of DP+CU design

1. Model the design (usually described by an ASM chart) using any modeling style described above as a single module.

2. Extract the datapath from the module and construct it as another independent module.

3. Extract control-unit module and construct top module. Convert the first module to the control module Add a top module that instantiates both datapath and

control-unit



An ASM Example --- Step 1// Step 1: modeling the problemmodule booth (clk, start_n, data_a, data_b, total, finish);parameter W = 8; // word size parameter N = 3; // N = log2(W)input clk, start_n;input [W-1:0] data_a, data_b;output reg [W-1:0] total;reg [N-1:0] cnt; reg [1:0] present, next;output reg finish; // finish flaglocalparam idle = 1'b0, add = 1'b1;// the body of the w-bit booth multiplier// part 1: initialize to state idlealways @(posedge clk or negedge start_n)

if (!start_n) present <= idle; else present <= next;



An ASM Example --- Step 1

// part 2: determine next statealways @(*) case (present)

idle: if (!finish) next = add; else next = idle;add: if (cnt == 0) next = idle; else next = add;

endcase// part 3: execute RTL operationsalways @(posedge clk or negedge start_n) begin

if (!start_n) begin finish <= 0; total <= 0; endcase (present)

idle: cnt <= N - 1;add: begin

if (data[cnt] == 1) total <= total + data_b;cnt <= cnt - 1;if (cnt == 0) finish <= 1; end

endcase endendmodule



An ASM Example --- Step 2: extract datapath

// Step 2: data path structure is extracted from part 3module booth (clk, start_n, data_a, data_b, total, finish);..output wire [N-1:0] total;wire load; // ..datapath #(8) dp (.clk(clk), .acc_reset_n(start_n), .acc_load(load),

.acc_data_b(data_b), .acc_total(total));// part 1 is the same as in step 1// part 2 is the same as in step 1




// part 3: execute RTL operationsalways @(posedge clk or negedge start_n) begin

if (!start_n) begin finish <= 0; total <= 0; endcase (present)

idle: cnt <= N - 1;add: begin

if (data[cnt] == 1) total <= total + data_b;cnt <= cnt - 1;if (cnt == 0) finish <= 1; end

endcase endassign load = (present == add) && (data[cnt] == 1);endmodule




// define the datapath modulemodule datapath (clk, acc_reset_n, acc_load, acc_data_b, acc_total);paramenter N = 8;input clk, acc_reset_n, acc_load;input [N-1:0] acc_data_b;output reg [N-1:0] acc_total;always @(posedge clk or negedge acc_reset_n)

if ( !acc_reset_n) acc_total <= 0;else if (acc_load) acc_total <= acc_total + acc_data_b;

endmodule



An ASM Example --- Step 3: convert the 1st module

// converting the first module to the control modulemodule controller (cu_clk, cu_reset_n, cu_data_a, cu_load, cu_finish);parameter W = 8; // word size parameter N = 3; // N = log2(W)input cu_clk, cu_reset__n;input [W-1:0] cu_data_a;output reg [W-1:0] total;reg [N-1:0] cnt; reg [1:0] present, next;output reg finish; // finish flaglocalpram idle = 1'b0, add = 1'b1;// the body of the w-bit booth multiplier// part 1: initialize to state idlealways @(posedge clk or negedge start_n)

if (!start_n) present <= idle; else present <= next;….endmodule



An ASM Example --- Step 3: construct top module

// converting the first module to the control modulemodule top (clk, start_n, data_a, data_b, total, finish);parameter W = 8; // word size parameter N = 3; // N = log2(W)input clk, startt__n;input [W-1:0] data_a, data_b;output wire [W-1:0] total;wire load; output wire finish; // finish flaglocalpram idle = 1'b0, add = 1'b1;// datapathdatapath #(8) dp (.clk(clk), .acc_reset_n(start_n), .acc_load(load),

.acc_data_b(data_b), .acc_totla(total));// controllercontroller cu (.cu_clk(clk), .cu_reset_n(start_n), .cu_data_a(data_a),

.cu_load(load), .cu_finish(finish));endmodule



A dp+cu Approach --- Booth Serial Multiplier

mpaccacc_rso

mcand

Control unit

sum_out

acc_qout

mcand_qout

add_subadd_sub

acc_qout[w-1]

mp[1:0]start_nacc_mode

start_nmp_mode

mcand_loadstart_n

start_nfinish

3 3

datapath



Realization Options of RTL Design

The rationale behind these options is a tradeoff among performance (throughput, operating frequency), space (area, hardware cost), and power consumption.

Single cycle uses combinational logic only to realize the required functions. It may require a quite long propagation time to finish a

computation of required functions.

D Q

CK




Multiple cycle executes the required functions in consecutive clock cycles. Linear structure performs straightforward the required

functions without sharing resources.

D Q

CK

D Q

CK

D Q

CK




Nonlinear (feedback or feed-forward) structure performs the required functions with sharing resources by using feedback or feed-forward connection.

D Q

CK

D Q

CK

D Q

CK

D Q

CK

Single-stage nonlinear structure

Multiple-stage nonlinear structure




Pipeline is also a multiple cycle structure in which a new data can be fed into the structure at each clock cycle. Hence, it may output a result per clock cycle after the pipeline is fully filled.

clk

Input OutputD Q

CK

D Q

CK

D Q

CK



A Single-Cycle Example

un2_total[7:0] +

total_1[7:0]

+ total[7:0]

[7:0][7:0]

[7:0]

[7:0]

[7:0][7:0]

1

[7:0]Q[7:0][7:0] D[7:0] total[7:0][7:0]

data_c[7:0] [7:0]

data_b[7:0] [7:0]

data_a[7:0] [7:0]

clk

// a single-cycle examplemodule single_cycle_example(clk, data_a, data_b, data_c, total);parameter N = 8;input clk;input [N-1:0] data_a, data_b, data_c;output reg [N-1:0] total;// compute total = data_c - (data_a + data_b)always @(posedge clk) begin

total <= data_c - (data_a + data_b); endendmodule



A Multiple-Cycle Example

// a multiple cycle example --- an implicit FSMmodule multiple_cycle_example(clk, data_a, data_b, data_c, total);parameter N = 8;input clk;input [N-1:0] data_a, data_b, data_c;output reg [N-1:0] total;reg [N-1:0] qout_a, qout_b;// compute total = data_c - (data_a + data_b)// a, b, and c are sampled once in three clock edgesalways @(posedge clk) begin

qout_a <= data_a;@(posedge clk) qout_b <= qout_a + data_b;@(posedge clk) total <= data_c - qout_b;

endendmodule



A Multiple-Cycle Example

[1:0][2]

un2[2:0] qout_a[7:0] qout_b_1[7:0]

+ qout_b[7:0] total_1[7:0]

+ total[7:0]

[2:0]Q[2:0]D[2:0][7:0]Q[7:0][7:0] D[7:0]

[0] E

[7:0][7:0]

[7:0][7:0]Q[7:0][7:0] D[7:0]

[1] E

[7:0]

[7:0][7:0]

1

[7:0]Q[7:0][7:0] D[7:0][2] E

total[7:0][7:0]

data_c[7:0] [7:0]

data_b[7:0] [7:0]

data_a[7:0] [7:0]

clk



Pipeline Principles

Pipelining: a pipeline is composed of several stages with each stage consisting of a combinational logic circuit and a register, called pipeline register.

Pipeline latency: the number of cycles between the presentation of an input value and the appearance of its associated output.

Pipeline depth0 5 64321

clock period

latency



Pipelined Systems

The pipelined clock fpipe is set by the slowest stage and is larger than the frequency used in the original cascaded system.

For the ith-stage, the smallest allowable clock period Ti is determined by the following condition:

The pipelined clock period for an m-stage pipeline is chosen to be:

clk

Input Output

Inpu

t reg

iste

r

Logi

c

Inpu

t reg

iste

r

Logi

c

Inpu

t reg

iste

r

Logi

c

Inpu

t reg

iste

r

Logi

c

1,, +−++> iskewidsetupFFi ttttT

} ,... ,2 ,1|max{ miTT ipipe ==



A Simple Pipeline Example --- Not a Good One:why?

// a simple pipeline example --- Not a good onemodule simple_pipeline(clk, data_a, data_b, data_c, total);parameter N = 8;input clk;input [N-1:0] data_a, data_b, data_c;output reg [N-1:0] total;reg [N-1:0] qout_a, qout_b;// compute total = data_c - (data_a + data_b)always @(posedge clk) begin

qout_a <= data_a;qout_b <= qout_a + data_b;total <= data_c - qout_b; // t(n) = c(n-1) – (b(n-2) + a(n-3))

endendmodule



A Simple Pipeline Example --- Not a Good One:why?

qout_a[7:0] qout_b_1[7:0]

+ qout_b[7:0]

total_1[7:0]

+ total[7:0]

[7:0]Q[7:0][7:0] D[7:0]

[7:0][7:0]

[7:0][7:0]Q[7:0][7:0] D[7:0]

[7:0]

[7:0][7:0]

1

[7:0]Q[7:0][7:0] D[7:0] total[7:0][7:0]

data_c[7:0] [7:0]

data_b[7:0] [7:0]

data_a[7:0] [7:0]clk



A Simple Pipeline Example

// a simple pipeline examplemodule pipeline_example(clk, data_a, data_b, data_c, total);parameter N = 8;input clk;input [N-1:0] data_a, data_b, data_c;output reg [N-1:0] total;reg [N-1:0] qout_a, qout_b, qout_c, qout_d, qout_e;// compute total = data_c - (data_a + data_b)always @(posedge clk) begin

qout_a <= data_a; qout_b <= data_b; qout_c <= data_c;qout_d <= qout_a + qout_b;qout_e <= qout_c;

total <= qout_e - qout_d;endendmodule



A Simple Pipeline Example

qout_a[7:0]

qout_b[7:0] qout_c[7:0] qout_e[7:0]

qout_d_1[7:0] +

qout_d[7:0]

total_1[7:0]

+ total[7:0]

[7:0]Q[7:0][7:0] D[7:0]

[7:0]Q[7:0][7:0] D[7:0][7:0]Q[7:0][7:0] D[7:0] [7:0]Q[7:0][7:0] D[7:0]

[7:0][7:0]

[7:0][7:0]Q[7:0][7:0] D[7:0]

[7:0]

[7:0][7:0]

1

[7:0]Q[7:0][7:0] D[7:0] total[7:0][7:0]

data_c[7:0] [7:0]

data_b[7:0] [7:0]

data_a[7:0] [7:0]

clk



FSM vs. Iterative Logic

An iterative logic can be considered as an FSM expansion in time. At each time step, the combinational logic part of the FSM is duplicated and the memory element part is ignored.

An example of 1-D iterative logic

Combinationallogic

x z

ps nsFFs

Combinationallogicps[i] ns[i]

FFs

z[i]x[i]

Comb.logic

ps[0]

ns[0]

z[0]

x[0]

ps[1]

Comb.logic

ns[1]

z[1]

x[1]

ps[2]

Comb.logic

ps[i]

ns[i]

z[i]

x[i]

ps[i+1]

Comb.logic

ps[n-2]

ns[i]

z[n-2]

x[n-2]

ps[n-1]

Comb.logic

ns[n-1]

z[n-1]

x[n-1]

A nonlinear structure may be transferred into a linear one.



An FSM Example --- A 0101 Sequence Detector

Design a finite-state machine to detect the pattern 0101 in the input sequence x. Assume that overlapping pattern is allowed.

A B C D

1/0

0/0

0/0

1/0

1/0

0/0

1/1

0/0

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11

Clock

Input

Output

0 1 0 1 0 0 1 0 1 0 1 0

0 0 0 1 0 0 0 0 1 0 1 0

Sequencedetector Output (z)

clock (clk)

Input (x)

State diagramTiming chart

Block diagram



An Iterative Logic --- A 0101 Sequence Detector

PSNS, zixi

0 1A

B

C

D

B,0

B,0

D,0

B,0

A,0

C,0

A,0

C,1

0 100

01

10

11

01

01

11

01

00

10

00

10

0 10

0

0

0

0

0

0

1

yi1 yi2

Yi1 Yi2xi xi zi

Yi1 = xiyi2 + x'iyi1y'i2 Yi2 = x'i zi = xiyi1yi2

0

0

0

0

0 0

1 0

yi1yi2

xi00 01 11 10

0

1

0 2 6 4

1 3 7 5

1

0

1

0

1 1

0 0

yi1yi2

xi00 01 11 10

0

1

0 2 6 4

1 3 7 5

0

0

0

1

0 1

1 0

yi1yi2

xi00 01 11 10

0

1

0 2 6 4

1 3 7 5

xi

ith stageyi1

yi2

Yi1

Yi2

zi

001010



An Iterative Logic --- A 6-bit 0101Sequence Detector

xi

yi1

yi2

Yi1

Yi2

zi

x1y11

y12

Y11

Y12z1

x2y21

y22

Y21

Y22z2

x3y31

y32

Y31

Y32z3

x4y41

y42

Y41

Y42z4

x5y51

y52

Y51

Y52z5

x6y61

y62

Y61

Y62z6

1 2 3 4 5 6

0

0

0

0

1

0

11

0

1

1

1

0

1

1

1

0

0 1 0 1

0 0 1 0 1

A B C D

1/0

0/0

0/0

1/0

1/0

0/0

1/1

0/0

State diagram



An Iterative Logic --- A Sequence Detector

// Behavioral description of 0101 sequence detector --- An iterative logic version.module sequence_detector_iterative (x, z);parameter n = 6; // define the size of 0101 sequence detectorinput [n-1:0] x;output wire [n-1:0] z;// Local declaration.wire [n-1:0] next_state_1, next_state_0 ;parameter A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11;// Using generate block to produce an n-bit 0101 sequence detector.genvar i;generate for(i = 0; i < n; i = i + 1) begin: detector_0101

if (i == 0)begin: LSB // describe LSB cellbasic_cell bc (x[i], A, z[i], {next_state_1[i], next_state_0[i]}); end

else begin: rest_bits // describe the rest bitsbasic_cell bc (x[i], {next_state_1[i-1], next_state_0[i-1]}, z[i], {next_state_1[i],

next_state_0[i]}); endend endgenerateendmodule



An Iterative Logic --- A Sequence Detector

// Determine next state using function next_state.module basic_cell (x, present_state, output_z, next_state);input x; input [1:0] present_state; output reg [1:0] next_state;output reg output_z;parameter A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11;// Determine the next statealways @(present_state or x) case (present_state)

A: if (x) next_state = A; else next_state = B; ……

endcase// Determine the output valuealways @(present_state or x) case (present_state)

A: if (x) output_z = 1'b0; else output_z = 1'b0;……

endcaseendmodule

Exactly the same as the next state logic of FSM.

Exactly the same as the output logic of FSM.



A 2D-Iterative Logic --- Booth Multiplier

CTRL

xi-1

xi

add_sub_sel

add_sub_en

FA

Pin

Pi

CinCout

yi

yi

add_sub_sel

add_sub_en

CAS

xi xi - 1

0 00 11 01 1

Shift only

Shift only

Add and shiftSubtract and shift

Operationadd_sub_sel add_sub_en

01

01

φ0

φ1

add_sub_sel(i)add_sub_en(i)

C0,i



A 2D-Iterative Logic --- Booth Multiplier

CTRL CAS CAS CAS CAS



CTRL CAS CAS CAS CAS0

x3

x2

x1

x0

P3

P2

P1

P0

y3 y2 y1 y00000

P4P5P6P7

add_sub_sel

add_sub_en

0 1 1 1

1

1

1

0

1

1

0

1

0

1

1

1

1

0

0

1

0000

0 1 1 11 10 0

1

1 0 011

0 1 1 1

0 1 1 11

00

11

10

10

10

10

00

11

0

0 000C0,1

C0,0

C0,2

C0,3 add_sub_sel(i)add_sub_en(i)

C0,i

m

n

Chapter 11: System Design Methodology

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Transcript of Chapter 11: System Design Methodology