Chapter 1: Diode circuits...

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.inAnalog Electronics Circuits

Chapter 1: Diode circuits

• Objective

• To understand the diode operation and its equivalent circuits

• To understand various parameters of diodes

• Load line analysis

• Diode applications in rectifiers; HWR,FWR

• Diode testing

• Zener diode

• Diode data sheets and specifications

• Diode applications in clipper circuits

• Numerical

Semiconductor diode

Fig – a semiconductor diode symbol

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.inBasic operation

Fig – b Vi characteristics of a dioden-type versus p-type

• n-type materials make the Silicon (or Germanium) atoms more negative.

• p-type materials make the Silicon (or Germanium) atoms more positive.

• Join n-type and p-type doped Silicon (or Germanium) to form a p-n junction.

p-n junction

• When the materials are joined, the negatively charged atoms of the n-type doped side

are attracted to the positively charged atoms of the p-type doped side.

• The electrons in the n-type material migrate across the junction to the p-type material

(electron flow).

• the ‘holes’ in the p-type material migrate across the junction to the n-type material

(conventional current flow).

• The result is the formation of a depletion layer around the junction.

Depletion region

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.inOperating conditions

• No Bias

• Forward Bias

• Reverse Bias

No bias condition

• No external voltage is applied: VD = 0V and no current is flowing ID = 0A.

Only a modest depletion layer exists

Reverse bias condition

External voltage is applied across the p-n junction in the opposite polarity of the p- and n-

type materials.

• This causes the depletion layer to widen.

• The electrons in the n-type material are attracted towards the positive terminal and the

‘holes’ in the p-type material are attracted towards the negative terminal.

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.inAvalanche breakdown

Avalanche breakdown occurs when a high reverse voltage is applied to a diode and large

electric field is created across the depletion region. The effect is dependant on the doping

levels in the region of the depletion layer. Minority carriers in the depletion region

associated with small leakage currents are accelerated by the field to high enough energies

so that they ionise silicon atoms when they collide with them. A new hole-electron pair are

created which accelerate in opposite directions causing further collisions and ionisation and

avalanche breakdown

Zener breakdown

Breakdown occurs with heavily doped junction regions (ie. highly doped regions are better

conductors). If a reverse voltage is applied and the depletion region is too narrow for

avalanche breakdown (minority carriers cannot reach high enough energies over the distance

traveled ) the electric field will grow. However, electrons are pulled directly from the

valence band on the P side to the conduction band on the N side. This type of breakdown is

not destructive if the reverse current is limited.

Forward Bias Condition

• External voltage is applied across the p-n junction in the same polarity of the p- and n-

type materials.

• The depletion layer is narrow.

• The electrons from the n-type material and ‘holes’ from the p-type material have

sufficient energy to cross the junction.

• Actual v-i characteristics is as shown in fig below

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.inDiode current expression:

ID = Is( eVD / VT-1)• Is : Reverse saturation current• q : Charge of an electron• k : Boltzman constant 11600/η• T : Environment temperature in °K[ °K = °C + 273 ]• η =2 for silicon , η=1 for Germanium

Majority and Minority Carriers in Diode

A diode, as any semiconductor device is not perfect!

There are two sets of currents:

• Majority Carriers

The electrons in the n-type and ‘holes’ in the p-type material are the source of the

majority of the current flow in a diode.

• Minority Carriers

Electrons in the p-type and ‘holes’ in the n-type material are rebel currents. They produce

a small amount of opposing current.

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.inZener Region

Zener regionZener diode operation:

• The diode is in the reverse bias condition.

• At some point the reverse bias voltage is so large the diode breaks down.

• The reverse current increases dramatically.

• This maximum voltage is called avalanche breakdown voltage and the current is

called avalanche current.

Forward Bias Voltage

• No Bias condition to Forward Bias condition happens when the electron and ‘holes’

are given sufficient energy to cross the p-n junction.

• This energy comes from the external voltage applied across the diode.

The Forward bias voltage required for a

• Silicon diode VT ≅ 0.7V

• Germanium diode VT ≅ 0.3V

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.inTemperature Effects on performance of diode

• As temperature increases it adds energy to the diode.

• It reduces the required Forward bias voltage in Forward Bias condition

• It increases the amount of Reverse current in Reverse Bias condition

• It increases maximum Reverse Bias Avalanche Voltage

• Germanium diodes are more sensitive to temperature variations than Silicon Diodes.

Resistance Levels

• Semiconductors act differently to DC and AC currents.

There are 3 types of resistances.

• DC or Static Resistance

• AC or Dynamic Resistance

• Average AC Resistance

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.inDC or Static Resistance

RD=VD / ID

DC or static resistance

• For a specific applied DC voltage VD, the diode will have a specific current ID,

and a specific resistance RD.

• The amount of resistance RD, depends on the applied DC voltage.

AC or Dynamic Resistance

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.inForward Bias region:

• The resistance depends on the amount of current (ID) in the diode.

Rd=∆vd/ ∆Id

• The resistance depends on the amount of current (ID) in the diode.

• The voltage across the diode is fairly constant (VT = 26mV for 25°C).

• Reverse Bias region:

Rd=∞

The resistance is essentially infinite. The diode acts like an open.

Average AC Resistance

Rac=∆Vd/∆Id Point to point

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.inDiode equivalent circuits

• An equivalent circuit is a combination of elements properly chosen to best represent

the actual terminal characteristics of a device, system or such a particular operating

region.

• Then device symbol can be replaced with the equivalent circuit which makes the

analysis of the circuit easy and straight forward.

Piece wise linear equivalent circuit

One technique for obtaining equivalent circuit is to approximate the characteristics of the

device by straight line segments

• Rd defines the resistance level of the device when it is in the ON state.

• Ideal diode is included to establish that there is only one direction of conduction

through the device.

• Since silicon semiconductor diode does not conduct until VD of 0.7V is reached, a

battery opposing the conduction direction is included.

Simplified equivalent circuit

• In most of the applications, resistance rav is very small in comparison to the other

elements of the network.

• Removal of this rav from the network makes a simplified equivalent circuit.

• And an ideal diode will start conduction for zero applied voltage.

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.inTransition and diffusion capacitance

• The figure shows the capacitance v/s applied voltage across the diode.

• Shunt capacitive effects that can be ignored at very lower frequencies since Xc=1/2πfc

is very large (open circuit)

• However this can not be neglected in very high frequencies since it introduces a low

reactance (shorting) path.

• Two types of capacitive effects to be considered in FB and RB condition.

• In RB region transition or depletion region capacitance CT in FB diffusion

capacitance CD or storage capacitance.

• W.k.t C=εA/d.

• ε is the permittivity of dielectric between tow plates of area A separated by distance d.

• In RB, depletion region which is free of carriers that behaves essentially like an

insulator between the layers of opposite charges. This depletion region width increase

with increase in RB potential.

• Since d is increasing, capacitance effect is more in FB.

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.inDiode characteristics

Diode characteristics

Reverse recovery time

• Denoted by trr.

• In FB condition, large number of electrons from n-type progressing through p-type

and large number of holes in p-type is a requirement for conduction. The electrons in

p-type and holes progressing through n-type establish a large number of minority

carriers in each material.

• Now if the diode is changed from FB to RB

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.in• The diode will not instantaneously react to this sudden change. Because of the large

number of minority carriers in each material, the current sustains in diode for a time ts

storage time which is required for minority carriers to return to their majority carrier

state in the opposite material.

• Eventually current will reduce to non conduction levels.

• This time is tt transition interval

• Hence trr= ts + tt

• This is very important consideration in high frequency operation.

• Commercially available diodes have reverse recovery time of few nano seconds to

1micro second.

Load line Analysis

• The applied load will normally have an important impact on region of operation of

device.

• If analysis is done in graphical approach, a line can be drawn on the characteristics of

the device that represents applied load.

• The intersection of load line with the characteristics will determine the point of

operation.

• Such an analysis is called as load-line analysis.

• The intersection point is called ‘Q’ point or operating point.

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.in• Its very simple as compared to the non-linear analysis of diode which involves heavy

maths……

Both KVL and KCL must be satisfied at all times

i-v curves plotted for diode (energised by Vss)

i-v curves plotted for resistor

iD

iR

DR

DDSS

ii:KCLBy

vRiV:KVLBy

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.inWe can combine these curves on one plot to do a load line analysis

Load line analysis

R

VWhen SS RD i;0 v

R

vVi DSSD

0i; v RD SSVWhen

DR

DDSS

ii:KCLBy

vRiV:KVLBy

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.inExample on load line analysis

iR

iD

iD = 0

iD = 12.5mAvD = 1.25V

Operating Point:KVL and KCL

satisfied

iD = VSS/R = 20mA

0i

: v

20i

:0When v

.150Rand

3V:

R

D

R

D

SS

D

SS

SSD

i

VWhen

mAR

Vi

VAssume

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.inDiode approximations

In the approximate model of diode, the rav is not used since the value of this rav is

much less than other series elements of the network.

This model results in less expenditure of time and effort to obtain results.

Unless otherwise mentioned this approximate model is used hereforth…

Series diode configuration with DC inputs

• When connected to voltage sources in series, the diode is on if the applied voltage is

in the direction of forward-bias and it is greater than the VT of the diode

• When a diode is on, we can use the approximate model for the on state

Series diode configuration

Here, VD = VT, VR = E - VT

ID = IR = VR / R

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.inParallel diode configuration

Determine I1 , VD1 , VD2 and V0 for the parallel diode circuit in below figure

Here, VD = E, VR = 0, ID = 0

Keep in mind that KVL has to be satisfied under all

conditions

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.inSolution

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.inExamples1. Find diode current and output voltage

Solution:

2. Solve for I , v1,v2 and vo

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.in3.Determine unknown parameters

4.Determine unknown parameters

5.Determine unknown parameters

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.inRectifiers :

Half wave rectification

For the half-wave rectified signal:

Vdc = 0.318 Vm

If the effect of VT is also

considered, the output of the

system will as below

Vdc = 0.318 (Vm- VT)

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.inEffect of VT on half-wave rectified signal

PIV rating of Half-wave Rectifiers

PIV rating is very important consideration for rectifier circuits

For the half-wave rectifier must be equal or must not exceed the peak value of the applied voltage

PIV ≥ Vm

This is the voltage rating that must not be exceeded in the reverse bias region

When vin is negative.

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.inNon Ideal Waveform

Half-wave Rectifier

• The total effect of diode on the output signal is given in below

Average voltage VAV

• The average d.c. value of this half-wave-rectified sine wave is

0

0sin2

1dVV MAV

MM VV 0coscos

2

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.inFull-wave Rectifiers Bridge

Working :

• For the positive half of the AC cycle:

• Diode D1 and D2 gets forward biased and conducts.

Working :

• For the negative half of the AC cycle

• Diode D3 and D4 gets forward biased and conducts during this half cycle.

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.inDetails of working of FWR

• We initially consider the diodes to be ideal, such that VC =0 and Rf =0

• The four-diode bridge can be bought as a package During positive half cycles vi is

positive.

• Current is conducted through diodes D1, resistor R and diode D2

• Meanwhile diodes D3 and D4 are reverse biased

• During negative half cycles vi is negative.

• Current is conducted through diodes D3, resistor R and diode D4

• Meanwhile diodes D1 and D2 are reverse biased.

• Current always flows the same way through the load R.

• the average d.c. value of this full-wave-rectified sine wave is VAV = 2VM/ (i.e. twice

the half-wave value)

• Two diodes are in the conduction path.

• Thus in the case of non-ideal diodes vo will be lower than vi by 2VC.

• As for the half-wave rectifier a reservoir capacitor can be used. In the full wave case

the discharge time is T/2 and

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.inCentre - tap FWR

• Two diodes and a center-tapped transformer are required.

• VDC = 0.636(Vm)

• Note that Vm here is the transformer secondary voltage to the tap.

Operation

For the positive half of the AC cycle:

2RC

TVΔV M

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.inFor the negative half of the AC cycle:

Summary

Note: Vm = peak of the AC voltage.

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.inApplication of diode as Clippers

• Clippers have ability to “clip/remove” off a portion of the input signal without

distorting the remaining part of the alternating waveform.

• HWR is simplest form of clippers. The orientation of diode is going to decide the part

of sinusoidal waveform to be clipped off.

Clipper configuration

Depending on the way in which the diodes are connected with the input, the clipper are

classified in to two major categories, viz.,

• Series configuration

• Parallel configuration

1. Series clipper example 1

2. Series Clipper example 2

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.in3. Series clipper ex – 3 & 4

4. Series clipper Ex - 5 & 6

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.inVarious clipepr examples along with transfer characteristics

Biased parallel clippers

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.inDiode testing :

1. Diode testing using multi-meter

One problem with using an ohmmeter to check a diode is that the readings obtained

only have qualitative value, not quantitative. In other words, an ohmmeter only tells you

which way the diode conducts; the low-value resistance indication obtained while

conducting is useless. If an ohmmeter shows a value of “1.73 ohms” while forward-biasing a

diode, that figure of 1.73 Ω doesn't represent any real-world quantity useful to us as

technicians or circuit designers.

It neither represents the forward voltage drop nor any “bulk” resistance in the

semiconductor material of the diode itself, but rather is a figure dependent upon both

quantities and will vary substantially with the particular ohmmeter used to take the reading.

For this reason, some digital multimeter manufacturers equip their meters with a special

“diode check” function which displays the actual forward voltage drop of the diode in volts,

rather than a “resistance” figure in ohms. These meters work by forcing a small current

through the diode and measuring the voltage dropped between the two test leads. (Figure

below)

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.inMeter with a “Diode check” function displays the forward voltage drop of 0.548 volts instead of a low resistance.

The forward voltage reading obtained with such a meter will typically be less than the

“normal” drop of 0.7 volts for silicon and 0.3 volts for germanium, because the current

provided by the meter is of trivial proportions. If a multimeter with diode-check function

isn't available, or you would like to measure a diode's forward voltage drop at some non-

trivial current, the circuit of Figure below may be constructed using a battery, resistor, and

voltmeter

Measuring forward voltage of a diode without“diode check” meter function:(a) Schematic diagram. (b) Pictorial diagram

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.in2. Curve tracers

A curve tracer can display the characteristics of a host device.

Device could be diode or transistor or other semiconductor device.

Curve tracer by tektronix and other companies available

Easy to use and testing with less effort and time.

Diode specifications

• Data sheets provide data on specific semiconductor device.

• Manufacturers provide these information

• Usually given in easy readable formats like graphs, artwork, tables and so on.,

• These specifications are required for proper utilization of devices for specific

applications

Important data to be considered are

The forward voltage VF (at specific T) Maximum forward current IF

Maximum reverse saturation current IR

The reverse voltage rating (PIV) Maximum power dissipation Capacitance levels Reverse recovery time trr

Operating temperature rangeDepending on type of diode being used, additional data such as

Frequency Noise level Switching time Thermal resistance

Peak repetitive values are also provided

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.inFor IN4001 and 4007

Maximum ratings are those values beyond which device damage can occur.

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.inZener diodes

• By proper doping of the silicon, the “Zener Breakdown” can be made to have a very“sharp breakdown”.

• The breakdown voltage is commonly labeled as VZ.

Characteristics of Zener diode

• Equivalent circuit consist of a constant voltage supply of VZ in series with a zener

resistor rZ.

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.in• The approximate model is obtained just by neglecting the effect of rZ in the equivalent

model. Only a constant voltage source is used in this model.

• The temperature coefficients reflects the percentage change in VZ with temperature

and it is defined by the relation

• Tc={∆VZ/ VZ( T1-T0) } x 100%

• ∆VZ change in zener potential due to temperature variation

• (T1-T0) change in temperature

Examples

1. Det. Nominal voltage for 1N961 fairchild zener diode at temp of 1000c.Solution:∆VZ=Tc VZ(T1-T0)/100

={0.072x10V/100}(1000-250)= 0.54V

Therefore change in Zener voltage is 10.54V when temperature is raised from 250c to 1000c.

2. Find Is and vL using zener characteristics for given data.

3. Compute the Thevenin equivalent of the previous circuit with the zener diode as theloadThevenin voltageThevenin resistanceWe can then write VT +RTiD+vD = 0 and find out vD,, iD using the zener diodecharacteristics

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.invL = vD and IS = vL /RL + iD

Solution

Answers

• vL = 10V• IS = vL /RL + iD = 10/6 +10 mA = 11.67mA• vL = 9.5 V• IS = vL /RL + iD = 9.5/1.2 +5 mA = 12.92mA

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.in4. Find currents through diode D1 and D2.

General Approach:

• Assume the state of each of the diodes: i.e., “on” or “off”.

• Analyze the circuit and check to see if your assumptions were correct.

• If not correct try another set of assumptions.• Assume D1 is “off”: Replace with open• Assume D2 is “on”: Replace with short

vD1 = 10V – 3V = 7V

But this is not possible since the D1 would be forward biased or “on” with vD1 = 0V.

We must try another set of assumptions

• Assume D1 is “on” and D2 is “off”

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.inExample 2

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Chapter 2. - DC Biasing - BJTs

Objectives

To Understand :• Concept of Operating point and stability• Analyzing Various biasing circuits and their comparison with respect to stability

BJT – A Review

• Invented in 1948 by Bardeen, Brattain and Shockley• Contains three adjoining, alternately doped semiconductor regions: Emitter (E),

Base (B), and Collector (C)• The middle region, base, is very thin• Emitter is heavily doped compared to collector. So, emitter and collector are not

interchangeable.

Three operating regions

• Linear – region operation:– Base – emitter junction forward biased– Base – collector junction reverse biased

• Cutoff – region operation:– Base – emitter junction reverse biased– Base – collector junction reverse biased

• Saturation – region operation:– Base – emitter junction forward biased– Base – collector junction forward biased

Three operating regions of BJT

• Cut off: VCE = VCC, IC 0

• Active or linear : VCE VCC/2 , IC IC max/2

• Saturation: VCE 0 , IC IC max

Q-Point (Static Operation Point)

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• The values of the parameters IB, IC and VCE together are termed as ‘operatingpoint’ or Q ( Quiescent) point of the transistor.

Q-Point

• The intersection of the dc bias value of IB with the dc load line determines the Q-point.

• It is desirable to have the Q-point centered on the load line. Why?• When a circuit is designed to have a centered Q-point, the amplifier is said to be

midpoint biased.• Midpoint biasing allows optimum ac operation of the amplifier.

Introduction - Biasing

The analysis or design of a transistor amplifier requires knowledge of both the dc andac response of the system.In fact, the amplifier increases the strength of a weak signalby transferring the energy from the applied DC source to the weak input ac signal• The analysis or design of any electronic amplifier therefore has two components:

• The dc portion and• The ac portion

During the design stage, the choice of parameters for the required dc levels willaffect the ac response.

What is biasing circuit?

• Once the desired dc current and voltage levels have been identified, a networkmust be constructed that will establish the desired values of IB, IC and VCE, Such anetwork is known as biasing circuit. A biasing network has to preferably makeuse of one power supply to bias both the junctions of the transistor.

Purpose of the DC biasing circuit

• To turn the device “ON”• To place it in operation in the region of its characteristic where the device

operates most linearly, i.e. to set up the initial dc values of IB, IC, and VCE

Important basic relationship

• VBE = 0.7V• IE = ( + 1) IB IC

• IC = IB

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Biasing circuits:

• Fixed – bias circuit• Emitter bias• Voltage divider bias• DC bias with voltage feedback• Miscellaneous bias

Fixed bias

• The simplest transistor dc bias configuration.• For dc analysis, open all the capacitance.

DC Analysis

• Applying KVL to the input loop:VCC = IBRB + VBE

• From the above equation, deriving for IB, we get,IB = [VCC – VBE] / RB

• The selection of RB sets the level of base current for the operating point.• Applying KVL for the output loop:

VCC = ICRC + VCE

• Thus,VCE = VCC – ICRC

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• In circuits where emitter is grounded,VCE = VE

VBE = VB

Design and Analysis

• Design: Given – IB, IC , VCE and VCC, or IC , VCE and , design the values of RB,RC using the equations obtained by applying KVL to input and output loops.

• Analysis: Given the circuit values (VCC, RB and RC), determine the values of IB,IC , VCE using the equations obtained by applying KVL to input and output loops.

Problem – Analysis

Given the fixed bias circuit with VCC = 12V, RB = 240 k, RC = 2.2 k and = 75.Determine the values of operating point.

Equation for the input loop is:IB = [VCC – VBE] / RB where VBE = 0.7V,

thus substituting the other given values in the equation, we get

IB = 47.08uAIC = IB = 3.53mA

VCE = VCC – ICRC = 4.23V• When the transistor is biased such that IB is very high so as to make IC very high

such that ICRC drop is almost VCC and VCE is almost 0, the transistor is said to bein saturation.

IC sat = VCC / RC in a fixed bias circuit.

Verification

• Whenever a fixed bias circuit is analyzed, the value of ICQ obtained could beverified with the value of ICSat ( = VCC / RC) to understand whether the transistor isin active region.

• In active region,ICQ = ( ICSat /2)

Load line analysis

A fixed bias circuit with given values of VCC, RC and RB can be analyzed ( means,determining the values of IBQ, ICQ and VCEQ) using the concept of load line also.Here the input loop KVL equation is not used for the purpose of analysis, instead, theoutput characteristics of the transistor used in the given circuit and output loop KVLequation are made use of.

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• The method of load line analysis is as below:

1. Consider the equation VCE = VCC – ICRC This relates VCE and IC for the given IB

and RC

2. Also, we know that, VCE and IC are related through output characteristicsWe know that the equation,

VCE = VCC – ICRC

represents a straight line which can be plotted on the output characteristics of thetransistor.Such line drawn as per the above equation is known as load line, the slope of which is

decided by the value of RC ( the load).

Load line

• The two extreme points on the load line can be calculated and by joining whichthe load line can be drawn.

• To find extreme points, first, Ic is made 0 in the equation: VCE = VCC – ICRC .This gives the coordinates (VCC,0) on the x axis of the output characteristics.

• The other extreme point is on the y-axis and can be calculated by making VCE = 0in the equation VCE = VCC – ICRC which gives IC( max) = VCC / RC thus giving thecoordinates of the point as (0, VCC / RC).

• The two extreme points so obtained are joined to form the load line.• The load line intersects the output characteristics at various points corresponding

to different IBs. The actual operating point is established for the given IB.

Q point variation

As IB is varied, the Q point shifts accordingly on the load line either up or downdepending on IB increased or decreased respectively.As RC is varied, the Q point shifts to left or right along the same IB line since the

slope of the line varies. As RC increases, slope reduces ( slope is -1/RC) whichresults in shift of Q point to the left meaning no variation in IC and reduction in VCE .Thus if the output characteristics is known, the analysis of the given fixed bias circuit

or designing a fixed bias circuit is possible using load line analysis as mentionedabove.

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Emitter Bias

• It can be shown that, including an emitter resistor in the fixed bias circuitimproves the stability of Q point.

• Thus emitter bias is a biasing circuit very similar to fixed bias circuit with anemitter resistor added to it.

Input loop

• Writing KVL around the input loop we get,VCC = IBRB + VBE + IERE (1)

We know that,IE = (+1)IB (2)

Substituting this in (1), we get,

VCC = IBRB + VBE + (+1)IBRE

VCC – VBE = IB(RB + (+1) RE)

Solving for IB:

IB = (VCC – VBE ) /[(RB + (+1) RE)]

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The expression for IB in a fixed bias circuit was,

IB = (VCC – VBE ) /RB

Equivalent input loop:

• REI in the above circuit is (+1)RE which means that, the emitter resistance that iscommon to both the loops appears as such a high resistance in the input loop.

• Thus Ri = (+1)RE ( more about this when we take up ac analysis)

Output loop

Collector – emitter loop

Applying KVL,VCC = ICRC + VCE + IERE

IC is almost same as IE

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Thus,

VCC = ICRC + VCE + ICRE

= IC (RC + RE) +VCE

VCE = VCC - IC (RC + RE)

Since emitter is not connected directly to ground, it is at a potential VE, given by,

VE = IERE

VC = VCE + VE OR VC = VCC – ICRC

Also, VB = VCC – IBRB OR VB = VBE + VE

Problem:

Analyze the following circuit: given = 75, VCC = 16V, RB = 430k, RC = 2k and RE = 1k

Solution:

IB = (VCC – VBE ) /[(RB + (+1) RE)]

= ( 16 – 0.7) / [ 430k + (76) 1k] = 30.24A

IC = ( 75) (30.24A) = 2.27mA

VCE = VCC - IC (RC + RE) = 9.19V

VC = VCC – ICRC = 11.46V

VE = VC – VCE = 2.27V

VB = VBE + VE = 2.97V

VBC = VB – VC = 2.97 – 11.46 = - 8.49V

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Improved bias stability

• Addition of emitter resistance makes the dc bias currents and voltages remaincloser to their set value even with variation in

– transistor beta– temperature

Stability

In a fixed bias circuit, IB does not vary with and therefore whenever there is anincrease in , IC increases proportionately, and thus VCE reduces making the Q pointto drift towards saturation.In an emitter bias circuit, As increases, IB reduces,maintaining almost same IC and VCE thus stabilizing the Q point against variations.

Saturation current

In saturation VCE is almost 0V, thus

VCC = IC ( RC + RE )Thus, saturation current

IC,sat = VCC / ( RC + RE )

Load line analysis

The two extreme points on the load line of an emitter bias circuit are,

(0, VCC / [ RC + RE ]) on the Y axis, and

( VCC, 0) on the X axis.

Voltage divider bias

RC

R1

+VCC

RE

R2

v out

v in

C2C1

C3

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This is the biasing circuit wherein, ICQ and VCEQ are almost independent of .The level of IBQ will change with so as to maintain the values of ICQ and VCEQ almost

same, thus maintaining the stability of Q point.

Two methods of analyzing a voltage divider bias circuit are:Exact method – can be applied to any voltage divider circuitApproximate method – direct method, saves time and energy, can be applied in most ofthe circuits.

Exact method

In this method, the Thevenin equivalent network for the network to the left of the baseterminal to be found.

To find Rth:

From the above circuit,

Rth = R1 R2

= R1 R2 / (R1 + R2)

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To find Eth

From the above circuit,

Eth = VR2 = R2VCC / (R1 + R2)

In the above network, applying KVL

( Eth – VBE) = IB [ Rth +( + 1) RE ]

IB = ( Eth – VBE) / [ Rth +( + 1) RE ]

Analysis of Output loop

KVL to the output loop:

VCC = ICRC + VCE + IERE

IE IC

Thus, VCE = VCC – IC (RC + RE)

Note that this is similar to emitter bias circuit.

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Problem

For the circuit given below, find IC and VCE.Given the values of R1, R2, RC, RE and = 140 and VCC = 18V.For the purpose of DC analysis, all the capacitors in the amplifier circuit are opened.

Solution

Considering exact analysis:

1. Let us find Rth = R1 R2

= R1 R2 / (R1 + R2) = 3.55K

2. Then find Eth = VR2 = R2VCC / (R1 + R2)

= 1.64V3. Then find IB

IB = ( Eth – VBE) / [ Rth +( + 1) RE ]

= 4.37A

4. Then find IC = IB = 0.612mA

5. Then find VCE = VCC – IC (RC + RE)= 12.63V

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Approximate analysis:

The input section of the voltage divider configuration can be represented by the networkshown in the next slide.

Input Network

The emitter resistance RE is seen as (+1)RE at the input loop.If this resistance is much higher compared to R2, then the current IB is much smaller thanI2 through R2.This means, Ri >> R2

OR

(+1)RE 10R2

OR

RE 10R2

This makes IB to be negligible.Thus I1 through R1 is almost same as the current I2 through R2.Thus R1 and R2 can be considered as in series.Voltage divider can be applied to find the voltage across R2 ( VB)

VB = VCCR2 / ( R1 + R2)

Once VB is determined, VE is calculated as,VE = VB – VBE

After finding VE, IE is calculated as,IE = VE / RE

IE IC

VCE = VCC – IC ( RC + RE)

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Problem

Given: VCC = 18V, R1 = 39k , R2 = 3.9k , RC = 4k , RE = 1.5k and = 140.Analyse the circuit using approximate technique.In order to check whether approximate technique can be used, we need to verify thecondition,

RE 10R2

Here,RE = 210 k and 10R2 = 39 k

Thus the conditionRE 10R2 satisfied

Solution

• Thus approximate technique can be applied.

1. Find VB = VCCR2 / ( R1 + R2) = 1.64V

2. Find VE = VB – 0.7 = 0.94V

3. Find IE = VE / RE = 0.63mA = IC

4. Find VCE = VCC – IC(RC + RE) = 12.55V

Comparison

Exact Analysis Approximate Analysis

IC = 0.612mA IC = 0.63mA

VCE = 12.63V VCE = 12.55V

Both the methods result in the same values for IC and VCE since the condition RE 10R2 is satisfied.It can be shown that the results due to exact analysis and approximate analysis havemore deviation if the above mentioned condition is not satisfied.For load line analysis of voltage divider network, Ic,max = VCC/ ( RC+RE) when VCE

= 0V and VCE max = VCC when IC = 0.

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DC bias with voltage feedback

Input loop

Applying KVL for Input Loop:

VCC = IC1RC + IBRB + VBE + IERE

Substituting for IE as ( +1)IB and solving for IB,

IB = ( VCC – VBE) / [ RB + ( RC + RE)]

Output loop

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Neglecting the base current, KVL to the output loop results in,


DC bias with voltage feedback

Input loop

Applying KVL to input loop:

VCC = ICRC + IBRB + VBE + IERE

IC IC and IC IE

Substituting for IE as ( +1)IB [ or as IB] and solving for IB,

IB = ( VCC – VBE) / [ RB + ( RC + RE)]

Output loop

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Neglecting the base current, and applying KVL to the output loop results in,


In this circuit, improved stability is obtained by introducing a feedback path fromcollector to base.Sensitivity of Q point to changes in beta or temperature variations is normally less thanthat encountered for the fixed bias or emitter biased configurations.

Problem:

Given:VCC = 10V, RC = 4.7k, RB = 250 and RE = 1.2k. = 90.Analyze the circuit.

IB = ( VCC – VBE) / [ RB + ( RC + RE)]

= 11.91A

IC = ( IB ) = 1.07mA

VCE = VCC – IC ( RC + RE) = 3.69V

In the above circuit, Analyze the circuit if = 135 ( 50% increase).

With the same procedure as followed in the previous problem, we get

IB = 8.89A

IC = 1.2mA

VCE = 2.92V

50% increase in resulted in 12.1% increase in IC and 20.9% decrease in VCEQ

Problem 2:

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Determine the DC level of IB and VC for the network shown:

Solution:

Open all the capacitors for DC analysis.

RB = 91 k + 110 k = 201k

IB = ( VCC – VBE) / [ RB + ( RC + RE)]

= (18 – 0.7) / [ 201k + 75( 3.3+0.51)]

= 35.5A

IC = IB = 2.66mA

VCE = VCC – (ICRC)

= 18 – ( 2.66mA)(3.3k)

= 9.22V

Load line analysis

The two extreme points of the load line IC,max and VCE, max are found in the same as avoltage divider circuit.

IC,max = VCC / (RC + RE) – Saturation current

VCE, max – Cut off voltage

Miscellaneous bias configurations

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There are a number of BJT bias configurations that do not match the basic types ofbiasing that are discussed till now.

Miscellaneous bias (1)

Analyze the circuit in the next slide. Given = 120

Solution

This circuit is same as DC bias with voltage feedback but with no emitter resistor.Thus the expression for IB is same except for RE term.

IB = (VCC – VBE) / ( RB + RC)

= ( 20 – 0.7) / [680k + (120)(4.7k)]

= 15.51A

IC = IB = 1.86mA

VCE = VCC – ICRC = 11.26V = VCE

VB = VBE = 0.7V

VBC = VB – VC = 0.7V – 11.26V = - 10.56V


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Equivalent circuit

Input loop

Output loop

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Solution

The above circuit is fixed bias circuit.

Applying KVL to input loop:

VEE = VBE + IBRB

IB = ( VEE – VBE) / RB = 83A

IC = IB = 3.735mA

VC = -ICRC = - 4.48V

VB = - IBRB = - 8.3V


Determine VCE,Q and IE for the network.Given = 90( Note that the circuit given is common collector mode which can be identified byNo resistance connected to the collector output taken at the emitter)

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Input loop

Writing KVL to input loop:

VEE = IBRB + VBE + (+1)IBRE

IB = (VEE – VBE ) / [RB + (+1) RE]

= ( 20 – 0.7) / [ 240K + (91)(2K)]

= 45.73A

IC = IB = 4.12mA

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Output loop

Applying KVL to the output loop:

VEE = VCE + IERE

IE = (+1) IB = 4.16mA, VEE = 20V

VCE = VEE – IERE = 11.68V


Find VCB and IB for the Common base configuration given:

Given: = 60

Input loop

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Applying KVL to input loop

IE = ( VEE – VBE ) / RE

= 2.75mA

IE = IC = 2.75mA

IB = IC / = 45.8A

Output loop

Applying KVL to output loop:

VCC = ICRC + VCB

VCB = VCC – ICRC = 3.4V


Determine VC and VB for the network given below.Given = 120Note that this is voltage divider circuit with split supply.( +VCC at the collector and – VEE at the emitter)

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Thevinin equivalent at the input

Rth= (8.2k)(2.2k) / [ 8.2k+2.2k] = 1.73k

I = (VCC + VEE) / [R1 + R2]

= ( 20 + 20) / ( 8.2K + 2.2K)

= 3.85mA

Eth = IR2 – VEE

= - 11.53V

Equivalent circuit

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Applying KVL:

VEE – Eth – VBE – ( +1)IBRE – IBRth = 0

IB = ( VEE – Eth – VBE ) / [( +1) RE + Rth ]

= 35.39A

IC = IB = 4.25mA

VC = VCC – ICRC = 8.53V

VB = - Eth – IBRth = - 11.59V

Design Operations:

Designing a circuit requires

Understanding of the characteristics of the device

The basic equations for the network

Understanding of Ohms law, KCL, KVL

If the transistor and supplies are specified, the design process will simply

determine the required resistors for a particular design.

Once the theoretical values of the resistors are determined, the nearest

standard commercial values are normally chosen.

Operating point needs to be recalculated with the standard values of resistors

chosen and generally the deviation expected would be less than or equal to 5%.

Problem:

• Given ICQ = 2mA and VCEQ = 10V. Determine R1 and RC for the network shown:

Solution

To find R1:

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1. Find VB. And to find VB, find VE because, VB = VE + VBE

2. Thus, VE = IERE and IE IC = 2mA= (2mA)(1.2k) = 2.4V

3. VB =2.4 + 0.7 = 3.1V4. Also, VB = VCCR2 /(R1 + R2)

3.1 = (18)(18k) / R1+18kThus, R1 = 86.52k

To find RC :Voltage across RC = VCC – ( VCE + IERE)

= 18 – [ 10 + (2mA)1.2k]= 5.6V

RC = 5.6/2mA= 2.8K

Nearest standard values are,R1 = 82k + 4.7 k = 86.7 k where as calculated value is 86.52 k .RC = 2.7k in series with 1k = 2.8k

both would result in a very close value to the design level.

Problem 2

The emitter bias circuit has the following specifications: ICQ = 1/2Isat, Isat = 8mA, VC =18V, VCC = 18V and = 110. Determine RC , RE and RB.

Solution:ICQ = 4mA

VRC = (VCC – VC) = 10V

RC = VRC / ICQ,

= 10/4mA = 2.5k

To find RE: ICsat = VCC / (RC + RE)

To find RB: Find IB where, IB = IC / = 36.36A

Also, for an emitter bias circuit,

IB = (VCC – VBE) / RB+( +1) RE

Thus, RB = 639.8 k

Standard values: RC = 2.4 k, RE = 1 k, RB = 620 k

8mA = 28 / ( 2.5k + RE)

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Thus, RE = 1k

Transistor switching networks:

Through proper design transistors can be used as switches for computer and controlapplications.When the input voltage VB is high ( logic 1), the transistor is in saturation ( ON). Andthe output at its collector = VCE is almost 0V( Logic 0)

Transistor as a switch

When the base voltage VB is low( logic 0), i.e, 0V, the transistor is cutoff( Off) and IC

is 0, drop across RC is 0 and therefore voltage at the collector is VCC.( logic 1)Thus transistor switch operates as an inverter.This circuit does not require any DC bias at the base of the transistor.

Design

When Vi ( VB) is 5V, transistor is in saturation and ICsat

Just before saturation, IB,max = IC,sat / DC

Thus the base current must be greater than IB,max to make the transistor to work insaturation.

Analysis

When Vi = 5V, the resulting level of IB is

IB = (Vi – 0.7) / RB

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= ( 5 – 0.7) / 68k

= 63A

ICsat = VCC / RC = 5/0.82k

= 6.1mA

Verification

( IC,sat / ) = 48.8A

Thus IB > ( IC,sat / ) which is required for a transistor to be in saturation.

A transistor can be replaced by a low resistance Rsat when in saturation ( switch on)Rsat = VCE sat/ ICsat (VCE sat is very small and ICsat is IC,max is maximum current)A transistor can be replaced by a high resistance Rcutoff when in cutoff ( switch on)

ProblemDetermine RB and RC for the inverter of figure:

IC sat = VCC / RC

10mA = 10V/ RC

RC = 1k

IB just at saturation = IC sat /

= 10mA / 250

= 40A

Choose IB> IC sat / , 60 A

IB = (Vi – 0.7) / RB

60 A = ( 10 – 0.7) / RB

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RB = 155k

Choose RB = 150k, standard value,

re calculate IB, we get IB = 62 A which is also > IC sat /

Thus, RC = 1k and RB = 155k

Switching Transistors

Transistor ‘ON’ time = delay time + Rise timeDelay time is the time between the changing state of the input and the beginning of aresponse at the output.Rise time is the time from 10% to 90% of the final value.Transistor ‘OFF’ time = Storage time + Fall timeFor an ‘ON’ transistor, VBE should be around 0.7VFor the transistor to be in active region, VCE is usually about 25% to 75% of VCC.If VCE = almost VCC, probable faults:

– the device is damaged– connection in the collector – emitter or base – emitter circuit loop is open.

One of the most common mistake in the lab is usage of wrong resistor value.Check various voltages with respect to ground.Calculate the current values using voltage readings rather than measuring current bybreaking the circuit.

Problem – 1

Check the fault in the circuit given.

Problem - 2

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PNP transistors

The analysis of PNP transistors follows the same pattern established for NPN transistors.The only difference between the resulting equations for a network in which an npn

transistor has been replaced by a pnp transistor is the sign associated with particularquantities.

PNP transistor in an emitter bias

Applying KVL to Input loop:

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VCC = IBRB +VBE+IERE

Thus, IB = (VCC – VBE) / [RB + (+1) RE]

Applying KVL Output loop:

VCE = - ( VCC – ICRC)

Bias stabilization

The stability of a system is a measure of the sensitivity of a network to variations inits parameters.In any amplifier employing a transistor the collector current IC is sensitive to each ofthe following parameters. increases with increase in temperature.Magnitude of VBE decreases about 2.5mV per degree Celsius increase in temperature.ICO doubles in value for every 10 degree Celsius increase in temperature.

T (degreeCelsius)

Ico (nA) VBE (V)

- 65 0.2 x 10-3 20 0.85

25 0.1 50 0.65

100 20 80 0.48

175 3.3 x 103 120 0.3

Stability factors

S (ICO) = IC / IC0

S (VBE) = IC / VBE

S () = IC / Networks that are quite stable and relatively insensitive to temperature variationshave low stability factors.

The higher the stability factor, the more sensitive is the network to variations in thatparameter.

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S( ICO)

• Analyze S( ICO) for– emitter bias configuration– fixed bias configuration– Voltage divider configuration

For the emitter bias configuration,

S( ICO) = ( + 1) [ 1 + RB / RE] / [( + 1) + RB / RE]

If RB / RE >> ( + 1) , then

S( ICO) = ( + 1)

For RB / RE <<1, S( ICO) 1

Thus, emitter bias configuration is quite stable when the ratio RB / RE is as small aspossible.Emitter bias configuration is least stable when RB / RE approaches ( + 1) .

Fixed bias configuration

S( ICO) = ( + 1) [ 1 + RB / RE] / [( + 1) + RB / RE]

= ( + 1) [RE + RB] / [( + 1) RE + RB]

By plugging RE = 0, we get

S( ICO) = + 1

This indicates poor stability.

Voltage divider configuration

S( ICO) = ( + 1) [ 1 + RB / RE] / [( + 1) + RB / RE]

Here, replace RB with Rth

S( ICO) = ( + 1) [ 1 + Rth / RE] / [( + 1) + Rth / RE]

Thus, voltage divider bias configuration is quite stable when the ratio Rth / RE is as small

as possible.

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Physical impact

In a fixed bias circuit, IC increases due to increase in IC0. [IC = IB + (+1) IC0]IB is fixed by VCC and RB. Thus level of IC would continue to rise with temperature –a very unstable situation.

In emitter bias circuit, as IC increases, IE increases, VE increases. Increase in VE

reduces IB. IB = [VCC – VBE – VE] / RB. A drop in IB reduces IC.Thus, thisconfiguration is such that there is a reaction to an increase in IC that will tend tooppose the change in bias conditions.

In the DC bias with voltage feedback, as IC increases, voltage across RC increases,thus reducing IB and causing IC to reduce.

The most stable configuration is the voltage – divider network. If the condition RE

>>10R2, the voltage VB will remain fairly constant for changing levels of IC. VBE =VB – VE, as IC increases, VE increases, since VB is constant, VBE drops making IB tofall, which will try to offset the increases level of IC.

S(VBE)

S(VBE) = IC / VBE

For an emitter bias circuit, S(VBE) = - / [ RB + ( + 1)RE]

If RE =0 in the above equation, we get S(VBE) for a fixed bias circuit as,S(VBE) = - / RB.

For an emitter bias,

S(VBE) = - / [ RB + ( + 1)RE] can be rewritten as,

S(VBE) = - (/RE )/ [RB/RE + ( + 1)]

If ( + 1)>> RB/RE, thenS(VBE) = - (/RE )/ ( + 1)

= - 1/ RE

The larger the RE, lower the S(VBE) and more stable is the system.

Total effect of all the three parameters on IC can be written as,

IC = S(ICO) ICO + S(VBE) VBE + S()General conclusion:

The ratio RB / RE or Rth / RE should be as small as possible considering all aspects ofdesign.

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General Amplifiers

Cascade connection - FET & BJT

Numerical

Cascode connection

Darlington connection

Packaged Darlington connection

Dc bias of Darlington connection

AC equivalent

ac output impedance of Darlington connection

AC voltage gain

Feedback concept

Feedback connection type

Practical feedback circuits


Numerical

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.inCascade connection – FET

• Cascade connection is a series connection with the output of one stage thenapplied as input to the second stage.

• Cascade connection provides a multiplication of the gain of each stage for alarger overall gain.

• Gain of overall cascade amplifier is the product of stage gains AV1 and AV2

Av = Av1AV2 = (-gmRD1) (-gmRD2)

• The input impedance of the cascade amplifier is that of stage 1,

Zi = RG1

• Output impedance is that of stage 2,

Z0=RD2

• The main function of cascading the stages is the larger overall gain achieved.

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.inNumerical

Calculate dc bias, voltage gain, input impedance, output impedance,Also

calculate the load voltage if a 10K Ω load is connected across the output

Data for numerical

• C1=C2=C3=0.05uF

• RG1=RG2=3.3 MΩ

• RS1=RS2=680 Ω

• RD1=RD2=2.4 KΩ

• IDSS=10mA; VP=-4V for both stages

Solution

Step 1: from the dc bias details we can find out VGSQ= -1.9V, IDQ=2.8mA

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.inStep 2: both transistors have

gmo=2 IDSS/ Vp =2(10mA)/4 =5mS

At dc bias point, gm=gmo(1-VGS/VP)

gm =5m(1-(-1.9)/(-4) = 2.6mS

Step 3: the voltage gain of each stage

AV1=AV2=-gm RD=-2.6m x 2.4K = -6.2

• Step 4: Overall gain of cascaded stage is

Av=Av1Av2=-6.2 x -6.2 = 38.4

(output is in phase with input)

• Step 5: output voltage is Vo=Av Vi =384 mV

• Cascade amplifier input impedance is

Zi=RG= 3.3 MΩ

• Output impedance (with rd=very high)

Zo=RD= 2.4 KΩ

• Load voltage if load resistance is 10 KΩ

VL= [RL/(RL+Zo)] Vo

=[10K/(10K+2.4)] 384mV=310mV

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.inCascade amplifier – BJT

• RC coupled cascade amplifier is taken here for example

• Advantage of cascading is increase in the overall voltage gain.

• Dc bias is obtained by procedure followed for single stage amplifier.

• Gain of each stage: AV= -(RC װ RL )/re

• Amplifier input impedance is that of

stage 1: Zi= R1 װ R2 װ βre

• Output impedance is that of stage 2 :

Zo=Rc װ ro

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.inNumerical

Calculate voltage gain, output impedance, input impedance for cascaded BJT

amplifier of fig above. Calculate output voltage resulting if 10K ohms load is

connected to load.

Given,

R1=15KΩ; R2=4.7KΩ;Rc=2.2KΩ;RE=1KΩ

• C1=C2=C3=10uF

• β=200 for both transistors

• Input voltage vi= 25uV

Solution:

• Dc analysis yields

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.in• VB=4.7V;VE=4.0V;VC=11V; IE=4.0mA

• At bias point, re=VT/IE=26m/4.0m=6.5 Ω

• Voltage gain of stage 1 is then,

• AV1= -{RC װ (R1 װ R2 װ βre)}/re

= -665.2/6.5=-102.3

• AV2= -Rc/re = -2.2K/6.5 =-338.46

• Overall gain of AV=AV1AV2

=-102.3 x -338.46

=34,624

• Output voltage is : Vo=AV Vi=34624 x 25u

=0.866V

• Amplifier input impedance is

• Zi= R1 װ R2 װ βre =4.7K װ 15 K װ 200x6.5

=953.6 ohms.

• VL= {RL/Zo+RL} Vo

={10K/2.2K+10K}0.866 = 0.71 V

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.inCascode connection

• A cascode connection has one transistor on top in series with another.

• Figure below shows CE stage feeding a CB stage.

• This arrangement is designed to provide a high input impedance with low

voltage gain to ensure that the input Miller capacitance is at a minimum with

the CB stage providing good high frequency operation.

Cascade connection configuration fig:1

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Cascade connection configuration fig:2

Numerical

Calculate the voltage gain for the cascode amplifier of fig above..

Solution:

Dc analysis: VB1=4.9V ; VB2=10.8V;

IC1=Ic2=3.8mA

Dynamic resistance of each transistor is then re=26/3.8=6.8 ohms

• Voltage gain of stage 1 is

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.inAv1= -Rc/re= -re/re = -1

• Voltage gain of stage 2 is

Av2=Rc/re =1.8K/6.8 = 265

• Resulting in an overall cascode amplifier gain of Av=Av1 x Av2 =-1 x 265=-265

• CE stage with a gain of -1 provides the higher input impedance of CE stage.

• With gain of -1, miller capacitance is kept very small.

• A large gain is then provided by the CB stage, resulting in large overall gainof -265.

Darlington connection

Popular connection operates as “super beta” transistor is Darlington connection.

• Main feature of the Darlington connection is that the composite acts as asingle unit with a current gains of individual transistors.

• Darlington connection provides a current gain of βo= β1+ β2

• If β1= β2= β then βo= β2

• This configuration provides a transistor having a very large current gain,typically a few thousands.

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.inPackaged Darlington transistor

• Specification information of 2N999 Darlington transistor package

DC bias of Darlington circuits

BEEB

EEE

BDBDE

EDB

BEccB

VVV

RIV

Voltages

III

RR

VVI

)1(

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.inNumerical

Calculate dc bias voltages and currents for the Darlington connection. GivenRB=3.3MΩ;RE=390 Ω;βd=8000;VCC=18V;VBE=1.6V

VV

VVVV

VmRIV

Voltages

mAuIII

uAMRR

VVI

C

BEEB

EEE

BDBDE

EDB

BEccB

18

6.96.18

8)390(48.20

48.20)56.2(8000)1(

56.2)390(80003.3

6.118

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.inAC equivalent circuit

Equivalent model

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.inInput impedance

• The ac base current through ri is

Ib=Vi-Vo/ri

• Since Vo=(Ib+βDIb)RE

• Substituting Ib in Vo expression,

Ibri=Vi-Vo=Vi-Ib(1+ βD)RE

solving for Vi,

Vi=Ib[ri+(1+ βD)RE]=Ib(ri+ βDRE)

• Ac input impedance looking into the transistor base is then

Vi/Ib= ri+ βDRE

Zi=RB װ (ri+ βDRE)

ac output impedance of Darlington connection

This can be determined for ac circuit shown in fig below

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.inOutput impedance

• The output impedance can be determined by applying a voltage Vo andmeasuring the current Io with Vs setting to zero.

• Solution for Io yields..

Zo= RE װ ri װ ri/βD

oi

D

iEo

i

oD

i

o

E

oBD

i

o

E

oo

VrrR

I

r

V

r

V

R

VI

r

V

R

VI

11

iDiEo

oo rrRI

VZ

//1/1

1

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.inac voltage gain

Gain expression

On simplification

Numerical

For the Darlington pair, given RE=390 ohms and β=8000. Calculate gain ifri=5KΩ

EbD

EDEbEbDbo

RIIbIbriVi

RRIRIIV

)(

)()(

1)(

)()(

)(

DREREri

DRERE

Vi

VoAv

RRRRr

VV

RRrIV

EDEEDEi

io

EDEibi

998.0]3908000390[5

3908000390

xK

xAv

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.inFeedback concepts

• Depending on the relative polarity of fed back signal in to the circuit, thereare two types of feedback

> Negative feedback

> Positive feedback

Negative feedback results in Reduced gain

Positive feedback are used in oscillators.

Feedback amplifier

Negative feedback circuits

• Reduces the gain

• Increases input impedance

• Better stabilized frequency response

• Lower output impedance

• Reduced noise

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.in• More linear operation

Feedback connection types

• Voltage series feedback

• Voltage shunt feedback

• Current series feedback

• Current shunt feedback

Here voltage refers to small part of voltage as input to the feedback network

Current refers to tapping some part of output current through feedbacknetwork.

Series refers to connecting feedback signal in series with the input signalvoltage.

Shunt refers to connecting feedback signal in shunt with the input signalvoltage

Series feedback connections increases the input resistance

Shunt feedback connections decreases the input resistance.

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.inVoltage series feedback Af=Vo/Vs

Voltage shunt feedback Af=Vo/Is

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.inCurrent series feedback Af=Io/Vs

Current shunt feedback Af=Io/Is

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.inGain with feedback

• Gain without feedback is A

• Feedback factor β

• Gain with feedback is (1+A β)

ParameterVoltageseries

Voltageshunt

Currentseries

Currentshunt

Gain withfeedback

A Vo/Vi Vo/Ii Io/Vi Io/Ii

Feedback factor β Vf/vo If/Vo Vf/Io If/Io

Gain withfeedback

Af Vo/Vs Vo/Is Io/Vs Io/Is

Voltage series feedback

• With zero feedback then Vf=0 the voltage gain of amplifier stage is

A=Vo/Vs=Vo/Vi

• If feedback of Vf is connected then,

Vi=Vs-Vf

Vo=AVi=A(Vs-Vf)=AVs-AVf=A(Vs-A(βVo)

Then, (1+ βA)Vo=AVs

Overall gain with feedback is

Af=Vo/Vi=A/(1+A β)

This shows that gain of feedback has reduced by factor (1+A β)

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.inVoltage shunt feedback

• Af=Vo/Is=A Ii / (Ii+If)=AIi/(Ii+ βAIi)

• Af=A/(1+ βA)

Input impedance with FB

• Ref to fig(1)

Ii=Vi/Zi=(Vs-Vf) / Zi = (Vs- βVo) / Zi

Ii Zi= Vs- βAVi

Vs=Ii Zi+ β A Vi = Ii Zi+ β A Ii Zi

Zif = Vs/Ii=Zi+(βA)Zi=Zi(1+ βA)

Improved circuit features of feedback

• Reduction in frequency distortion

When Aβ» 1, then Af=A/(1+A β)≈1/ β

• Here feedback is completely resistive and thus frequency distortion arisingbecause of varying gain with frequency is considerably reduced.

• Bandwidth variation

• When Aβ» 1, then Af=A/(1+A β)≈1/ β

• Therefore, here we can see that, practical circuits, open loop gain drops athigh frequencies.

• Therefore Aβ no longer » 1, hence Af=1/ β

No longer holds good.

• Here reduction in gain has provided improvement in the Bandwidth.

Product of gain and Bandwidth remains same it’s a tradeoff between gain and BW

• Gain stability for Aβ»1,

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.in• This shows that magnitude of relative change in dAf/A is reduced by the

factor Aβ compared to that without feedback dA/A

Numerical

If a amplifier with gain of -1000 and feedback of β=-0.1 has a gain change of 20%due to temperature, calculate the change in gain of the feedback amplifier.

Solution:


• Voltage series feedback

A

dA

A

1

dA

dA

A1Af

f

%2.0........

%20)1000(1.0

11

A

dA

AAf

dAf

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.in• Here part of output voltage (Vo) is obtained using a feedback network of

resistors R1 and R2.

• The feedback voltage Vf is connected in series with the source signal Vs.their difference being the input signal Vi.

• Gain without feedback A=Vo/Vi=-gmRL

Where RL=parallel combination of RD,Ro,(R1+R2)

• The feedback network provides a feedback factor or β=Vf/Vo = -R2/R1+R2

• Using values of A and β in above equation, Af is

Numerical:

Calculate the gain without and with feedback for the FET amplifier shown in fig.circuit values are given to be R1=80KΩ,R2=20KΩ,RD=10KΩ and gm=4000uS

Solution :

RL=5K Ω

A=-20

β=-0.2 and Af=-4

2

21

212

1

,1..

)/(11

R

RRAf

thenAif

gRRRR

Rg

A

AAf

mL

Lm

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.inSeries feedback connection

• Here gain of op-amp is reduced by factor β=R2/R1+R2

Numerical

If open loop gain of op-amp is 100,000 and feedback resistors are R1=1.8K Ω andR2=200 Ω then calculate the gain with feedback .

Solution

• β=0.1

• Af=9.9999

• Here Aβ>>1, Af=1/ β=1/0.1=10

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.inEmitter follower circuit

• The output voltage Vo is also the feedback voltage in series with the inputvoltage.

• Operation of the circuit without the feedback Vf=0 then,

• The operation with feedback then provides that,

1

)/(

o

f

s

Efe

s

ieEfe

s

Ebfe

i

o

V

V

V

Rh

V

hVsRh

V

RIh

V

VA

)/)(1(1

/

1 ieEfe

ieEfe

s

o

hRh

hRh

A

A

V

VAf

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.inCurrent series feedback

• Feedback technique is to sample the output current (Io) and return aproportional voltage in series with the input.

• It stabilizes the amplifier gain, the current series feedback connectionincreases the input resistance.

• In this circuit, emitter of this stage has an un bypassed emitter, it effectivelyhas current-series feedback.

• The current through RE results in feedback voltage that opposes the sourcesignal applied so that the output voltage Vo is reduced.

• To remove the current-series feedback, the emitter resistor must be eitherremoved or bypassed by a capacitor (as is done in most of the amplifiers)

1

,1

Af

hfeRE

Rhh

Rh

Efeie

Efe

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.inThe fig below shows the equivalent circuit for current series feedback

Gain, input and output impedance for this condition is,

Numerical

Calculate the voltage gain of the circuit..

Efeie

CfeCfc

s

o

s

co

s

ovf

ie

Efecoof

ie

Efeieiif

Eie

feE

iefe

s

of

Rhh

RhRAR

V

I

V

RI

V

VA

Afeedbackwith

h

RhRAZZ

h

RhhAZZ

Rh

hR

hh

A

A

V

IA

;..

1)1(

1)1(

)(1

/

1

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.inWith RB=470Ω,RC=2.2KΩ,RE=510 Ω, hfe=120,hie=900Ω.

Solution:

• The factor (1+Aβ) is then,

1+(-0.085)(-510) =44.35

• The gain with feedback is

Af=Vo/vi=A/(1+A β)

=-.085/44.35 = -1.92x10e-3

• Voltage gain with feedback is

Avf=Vo/Vs=AfRC=(-1.92x10e-3)(2.2x10e3)=4.2

• Without feedback (RE=0) the voltage gain is

510

085.0510900

120

REIo

VfREhie

hfe

Vi

IoA

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.inAv=-RC/re=-2.2x10e3/7.5= -293.3

Voltage shunt feedback

• Constant gain op-amp circuit provides voltage shunt feedback.

• Ref to fig below. The input impedance of a ideal op-amp is taken to beinfinite. Hence Ii=0,vi=0 and voltage gain is infinity.

• Ie., A=Vo/Ii=infinity

• And β=If/Vo= -1/Ro

• This is transfer resistance gain.

Voltage shunt negative feedback amplifier

1.Constant gain circuit

2.Equivalent circuit

• Voltage gain with feedback ,

1

0

1

1)(

1 R

R

RRo

V

Is

Is

VoAvf

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.inVoltage shunt feedback using FET

Equivalent circuit

• With no feedback A=Vo/Ii=-gmRDRS

• The feedback factor is β=If/Vo= -1/RF

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.in• With feedback, gain of the circuit is,

Numerical

Calculate voltage gain with and without feedback for the circuit of FET f/b. Withthe values, gm=5mS, RD=5.1KΩ, Rs=1KΩ, RF=20KΩ

Solution :

Use above formulae

• Av=-gmRD=-25.5

• Feedback gain Avf=-11.2

SDmF

FDm

SDmF

FDm

SSDmF

FSDm

s

s

s

ovf

SDmF

SDm

s

of

RRgR

RRg

RRgR

RRg

RRRgR

RRRg

V

I

I

VA

isckwithfeedbagainvoltage

RRgR

RRg

A

A

I

VA

)(

1

,..

))(/1(11

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1

CHAPTER.4: Transistor at low frequencies

• Introduction• Amplification in the AC domain• BJT transistor modeling• The re Transistor Model• The Hybrid equivalent Model

Introduction

• There are three models commonly used in the small – signal ac analysis oftransistor networks:

• The re model• The hybrid model• The hybrid equivalent model

Amplification in the AC domain

The transistor can be employed as an amplifying device, that is, the output ac poweris greater than the input ac power. The factor that permits an ac power output greaterthan the input ac power is the applied DC power. The amplifier is initially biased forthe required DC voltages and currents. Then the ac to be amplified is given as input tothe amplifier. If the applied ac exceeds the limit set by dc level, clipping of the peakregion will result in the output. Thus, proper (faithful) amplification design requiresthat the dc and ac components be sensitive to each other’s requirements andlimitations. The superposition theorem is applicable for the analysis and design of thedc and ac components of a BJT network, permitting the separation of the analysis ofthe dc and ac responses of the system.

BJT Transistor modeling

• The key to transistor small-signal analysis is the use of the equivalent circuits(models). A MODEL IS A COMBINATION OF CIRCUIT ELEMENTSLIKE VOLTAGE OR CURRENT SOURCES, RESISTORS, CAPACITORSetc, that best approximates the behavior of a device under specific operatingconditions. Once the model (ac equivalent circuit) is determined, the schematicsymbol for the device can be replaced by the equivalent circuit and the basicmethods of circuit analysis applied to determine the desired quantities of thenetwork.

• Hybrid equivalent network – employed initially. Drawback – It is defined for a setof operating conditions that might not match the actual operating conditions.

• re model: desirable, but does not include feedback term

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2

• Hybrid model: model of choice.

AC equivalent of a network

• AC equivalent of a network is obtained by:• Setting all dc sources to zero and replacing them by a short – circuit equivalent• Replacing all capacitors by short – circuit equivalent• Removing all elements bypassed by the short – circuit equivalents• Redrawing the network in a more convenient and logical form.

re model

• In re model, the transistor action has been replaced by a single diode betweenemitter and base terminals and a controlled current source between base andcollector terminals.

• This is rather a simple equivalent circuit for a device

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3

The Hybrid equivalent model

For the hybrid equivalent model, the parameters are defined at an operating point. The quantities hie, hre,hfe, and hoe are called hybrid parameters and are the

components of a small – signal equivalent circuit.• The description of the hybrid equivalent model will begin with the general two

port system.

• The set of equations in which the four variables can be related are:• Vi = h11Ii + h12Vo

• Io = h21Ii + h22Vo

• The four variables h11, h12, h21 and h22 are called hybrid parameters ( the mixtureof variables in each equation results in a “ hybrid” set of units of measurement forthe h – parameters.

• Set Vo = 0, solving for h11, h11 = Vi / Ii Ohms• This is the ratio of input voltage to the input current with the output terminals

shorted. It is called Short circuit input impedance parameter.• If Ii is set equal to zero by opening the input leads, we get expression for h12:

h12 = Vi / Vo , This is called open circuit reverse voltage ratio.• Again by setting Vo to zero by shorting the output terminals, we get

h21 = Io / Ii known as short circuit forward transfer current ratio.• Again by setting I1 = 0 by opening the input leads, h22 = Io / Vo . This is known as

open – circuit output admittance. This is represented as resistor ( 1/h22)• h11 = hi = input resistance• h12 = hr = reverse transfer voltage ratio• h21 = hf = forward transfer current ratio• h22 = ho = Output conductance

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4

Hybrid Input equivalent circuit

•

Hybrid output equivalent circuit

Complete hybrid equivalent circuit

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5

Common Emitter Configuration - hybrid equivalent circuit

• Essentially, the transistor model is a three terminal two – port system.• The h – parameters, however, will change with each configuration.• To distinguish which parameter has been used or which is available, a second

subscript has been added to the h – parameter notation.• For the common – base configuration, the lowercase letter b is added, and for

common emitter and common collector configurations, the letters e and c are usedrespectively.

Common Base configuration - hybrid equivalent circuit

Configuration Ii Io Vi Vo

Common emitter Ib Ic Vbe Vce

Common base Ie Ic Veb Vcb

Common Collector Ib Ie Vbe Vec

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6

• Normally hr is a relatively small quantity, its removal is approximated by hr 0and hrVo = 0, resulting in a short – circuit equivalent.

• The resistance determined by 1/ho is often large enough to be ignored incomparison to a parallel load, permitting its replacement by an open – circuitequivalent.

h-Parameter Model v/s. re Model

hie = re

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7

hfe = ac

Common Base: re v/s. h-Parameter Model

Common-Base configurations - h-Parameters

hib= re

hfb= - = -1Problem

• Given IE = 3.2mA, hfe = 150, hoe = 25S and hob = 0.5 S . Determine– The common – emitter hybrid equivalent– The common – base re model

Solution:• We know that, hie = re and re = 26mV/IE = 26mV/3.2mA = 8.125• re = (150)(8.125) = 1218.75k• ro = 1 /hoe = 1/25S = 40k

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8

• re = 8.125• ro = 1/ hob = 1/0.5S = 2M • 1

• Small signal ac analysis includes determining the expressions for the followingparameters in terms of Zi, Zo and AV in terms of

– – re

– ro and– RB, RC

• Also, finding the phase relation between input and output• The values of , ro are found in datasheet• The value of re must be determined in dc condition as re = 26mV / IE

Common Emitter - Fixed bias configuration

•Removing DC effects of VCC and Capacitors

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9

re model

Small signal analysis – fixed bias

• From the above re model,Zi = [RB re] ohms

If RB > 10 re, then,[RB re] re

Then, Zi re

Zo is the output impedance when Vi =0. When Vi =0, ib =0, resulting in open circuitequivalence for the current source.

• Zo = [RC ro ] ohms• AV

– Vo = - Ib( RC ro)

• From the re model, Ib = Vi / re

• thus,– Vo = - (Vi / re) ( RC ro)– AV = Vo / Vi = - ( RC ro) / re

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10

• If ro >10RC,– AV = - ( RC / re)

• The negative sign in the gain expression indicates that there exists 180o phaseshift between the input and output.

Common Emitter - Voltage-Divider Configuration

• The re model is very similar to the fixed bias circuit except for RB is R1 R2 in thecase of voltage divider bias.

• Expression for AV remains the same.Zi = R1 R2 re

Zo = RC

• From the re model, Ib = Vi / re

• thus,Vo = - (Vi / re) ( RC ro)

• AV = Vo / Vi = - ( RC ro) / re

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11

o If ro >10RC,

AV = - ( RC / re)

Common Emitter - Unbypassed Emitter-Bias Configuration

•

• Applying KVL to the input side:

Vi = Ib re + IeRE

Vi = Ib re +( +1) IbRE

Input impedance looking into the network to the right of RB is

Zb = Vi / Ib = re+ ( +1)RE

Since >>1, ( +1) =

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12

Thus,Zb = Vi / Ib = (re+RE)

• Since RE is often much greater than re,Zb = RE,

•Zi = RB||Zb

• Zo is determined by setting Vi to zero, Ib = 0 and Ib can be replaced by opencircuit equivalent. The result is,

• Zo = RC

• AV : We know that, Vo = - IoRC

= - IbRC

= - (Vi/Zb)RC

AV = Vo / Vi = - (RC/Zb)

Substituting, Zb = (re + RE)AV = Vo / Vi = - [RC /(re + RE)]

RE >>re, AV = Vo / Vi = - [RC /RE]• Phase relation: The negative sign in the gain equation reveals a 180o phase shift

between input and output.

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13

Emitter – follower

re model

• Zi = RB || Zb

• Zb = re+ ( +1)RE

• Zb = (re+ RE)

• Since RE is often much greater than re, Zb = RE

• To find Zo, it is required to find output equivalent circuit of the emitter followerat its input terminal.

• This can be done by writing the equation for the current Ib.Ib = Vi / Zb

Ie = ( +1)Ib

= ( +1) (Vi / Zb)

• We know that, Zb = re+ ( +1)RE substituting this in the equation for Ie we get,

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14

Ie = ( +1) (Vi / Zb)

= ( +1) (Vi / re+ ( +1)RE )

Ie = Vi / [re/ ( +1)] + RE

• Since ( +1) = ,

Ie = Vi / [re+ RE]

• Using the equation Ie = Vi / [re+ RE] , we can write the output equivalent circuit as,

•

• As per the equivalent circuit,

Zo = RE||re

• Since RE is typically much greater than re, Zo re

• AV – Voltage gain:

• Using voltage divider rule for the equivalent circuit,

Vo = Vi RE / (RE+ re)

AV = Vo / Vi = [RE / (RE+ re)]

• Since (RE+ re) RE,

AV [RE / (RE] 1

•

• Phase relationship

As seen in the gain equation, output and input are in phase.

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15

Common base configuration

re model

Small signal analysis

• Input Impedance: Zi = RE||re

• Output Impedance: Zo = RC

• To find, Output voltage,

Vo = - IoRC

Vo = - (-IC)RC = IeRC

o Ie = Vi / re, substituting this in the above equation,

Vo = (Vi / re) RC

Vo = (Vi / re) RC

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16

Voltage Gain: AV:

AV = Vo / Vi = (RC/ re)

1; AV = (RC/ re)

Current gain

Ai = Io / Ii

Io = - Ie = - Ii

Io / Ii = - -1

Phase relation: Output and input are in phase.

h-Parameter Model vs. re Model

CB re vs. h-Parameter Model

Common-Base h-Parameters

1h

rh

fb

eib

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17

• Small signal ac analysis includes determining the expressions for the followingparameters in terms of Zi, Zo and AV in terms of

– – re

– ro and– RB, RC

• Also, finding the phase relation between input and output• The values of , ro are found in datasheet• The value of re must be determined in dc condition as re = 26mV / IE

Common Emitter Fixed bias configuration

•

Removing DC effects of VCC and Capacitors

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18

re model

Small signal analysis – fixed bias

Input impedance Zi:

From the above re model, is,

Zi = [RB re] ohms

If RB > 10 re, then,

[RB re] re

Then, Zi re

Ouput impedance Zoi:

Zo is the output impedance when Vi = 0. When Vi = 0, ib = 0, resulting in open circuitequivalence for the current source.

Zo = [RC ro ] ohms

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19

Voltage Gain Av:

Vo = - Ib( RC ro)

From the re model, Ib = Vi / re

thus, Vo = - (Vi / re) ( RC ro)

AV = Vo / Vi = - ( RC ro) / re

If ro >10RC, AV = - ( RC / re)

Phase Shift:

The negative sign in the gain expression indicates that there exists 180o phase shiftbetween the input and output.

Problem:

Common Emitter - Voltage-Divider Configuration

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20

Equivalent Circuit:

The re model is very similar to the fixed bias circuit except for RB is R1 R 2 in the caseof voltage divider bias.

Expression for AV remains the same.

Zi = R1 R2 re

Zo = RC

:

Voltage Gain, AV:

From the re model,

Ib = Vi / re

Vo = - Io ( RC ro),

Io = Ib

thus, Vo = - (Vi / re) ( RC ro)

AV = Vo / Vi = - ( RC ro) / re

If ro >10RC, AV = - ( RC / re)

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Problem:

Given: = 210, ro = 50k.Determine: re, Zi, Zo, AV. For the network given:

To perform DC analysis, we need to find out whether to choose exact analysis orapproximate analysis.

This is done by checking whether RE > 10R2, if so, approximate analysis can be chosen.Here, RE = (210)(0.68k) = 142.8k.

10R2 = (10)(10k) = 100k.

Thus, RE > 10R2.

Therefore using approximate analysis,

VB = VccR2 / (R1+R2)

= (16)(10k) / (90k+10k) = 1.6V

VE = VB – 0.7 = 1.6 – 0.7 = 0.9V

IE = VE / RE = 1.324mA

re = 26mV / 1.324mA = 19.64

Effect of ro can be neglected if ro 10( RC). In the given circuit, 10RC is 22k, ro is 50K.

Thus effect of ro can be neglected.

Zi = ( R1||R2||RE)

= [90k||10k||(210)(0.68k)] = 8.47k

Zo = RC = 2.2 k

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AV = - RC / RE = - 3.24

If the same circuit is with emitter resistor bypassed,

Then value of re remains same.

Zi = ( R1||R2||re) = 2.83 k

Zo = RC = 2.2 k

AV = - RC / re = - 112.02

Common Emitter Un bypassed Emitter - Fixed Bias Configuration

Equivalent Circuit:

Applying KVL to the input side:

Vi = Ibre + IeRE

Vi = Ibre +( +1) IbRE

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Input impedance looking into the network to the right of RB is

Zb = Vi / Ib = re+ ( +1)RE

Since >>1, ( +1) =

Thus, Zb = Vi / Ib = (re+RE)

Since RE is often much greater than re,

Zb = RE,

Zi = RB||Zb

Zo is determined by setting Vi to zero, Ib = 0 and Ib can be replaced by open circuit

equivalent.

The result is, Zo = RC

We know that, Vo = - IoRC

= - IbRC

= - (Vi/Zb)RC

AV = Vo / Vi = - (RC/Zb)

Substituting Zb = (re + RE)

AV = Vo / Vi = - [RC /(re + RE)]

RE >>re, AV = Vo / Vi = - [RC /RE]

Phase relation: The negative sign in the gain equation reveals a 180o phase shift betweeninput and output.

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Problem:

Given: = 120, ro = 40k.Determine: re, Zi, Zo, AV.To find re, it is required to perform DC analysis and find IE as re = 26mV / IE

To find IE, it is required to find IB.

We know that,IB = (VCC – VBE) / [RB + (+1)RE]

IB = (20 – 0.7) / [470k + (120+1)0.56k] = 35.89A

IE = (+1)IB = 4.34mA

re = 26mV / IE = 5.99

Effect of ro can be neglected, if ro 10( RC + RE)

10( RC + RE) = 10( 2.2 k + 0.56k)

= 27.6 k

and given that ro is 40 k, thus effect of ro can be ignored.

Z i = RB|| [ ( re + RE)]

= 470k || [120 ( 5.99 + 560 )] = 59.34

Zo = RC = 2.2 k

AV = - RC / [ ( re + RE)]

= - 3.89

Analyzing the above circuit with Emitter resistor bypassed i.e., Common Emitter

IB = (VCC – VBE) / [RB + (+1)RE]

IB = (20 – 0.7) / [470k + (120+1)0.56k]

= 35.89A

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IE = (+1)IB = 4.34mA

re = 26mV / IE = 5.99

Zi = RB|| [re] = 717.70

Zo = RC = 2.2 k

AV = - RC / re = - 367.28 ( a significant increase)

Emitter – follower

re model

Zi = RB || Zb

Zb = re+ ( +1)RE

Zb = (re+ RE)

Since RE is often much greater than re, Zb = RE

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To find Zo, it is required to find output equivalent circuit of the emitter follower at its

input terminal.

This can be done by writing the equation for the current Ib.

Ib = Vi / Zb

Ie = ( +1)Ib

= ( +1) (Vi / Zb)

We know that,

Zb = re+ ( +1)RE

substituting this in the equation for Ie we get,

Ie = ( +1) (Vi / Zb)

= ( +1) (Vi / re+ ( +1)RE )

dividing by ( +1), we get,

Ie = Vi / [re/ ( +1)] + RE

Since ( +1) = ,

Ie = Vi / [re+ RE]

Using the equation Ie = Vi / [re+ RE], we can write the output equivalent circuit as,

As per the equivalent circuit,

Zo = RE||re

Since RE is typically much greater than re,

Zo re

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AV – Voltage gain:

Using voltage divider rule for the equivalent circuit,

Vo = Vi RE / (RE+ re)

AV = Vo / Vi = [RE / (RE+ re)]

Since (RE+ re) RE,

AV [RE / (RE] 1

Phase relationship

As seen in the gain equation, output and input are in phase.

Common base configuration

Vo

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re model

Small signal analysis

Zi = RE||re

Zo = RC

To find

Vo = - IoRC

Vo = - (-IC)RC = IeRC

Substituting this in the above equation, Ie = Vi / re,

Vo = (Vi / re) RC

Vo = (Vi / re) RC

AV = Vo / Vi = (RC/ re)

1; AV = (RC/ re)

Current gain Ai :

Ai = Io / Ii

Io = - Ie = - Ii

Io / Ii = - -1

Phase relation: Output and input are in phase.

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Common Emitter - Collector Feedback Configuration

re Model

Input Impedance: Zi

Zi = Vi / Ii,

Ii = Ib – I,

thus it is required to find expression for I in terms of known resistors.

I = (Vo – Vi)/ RF (1)

Vo = - IoRC

Io = Ib + I

Normally, I << Ib

thus, Io = Ib ,

Vo = - IoRC

Vo = - Ib RC,

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Replacing Ib by Vi / re

Thus,

Vo = - (Vi RC) / re

= - (Vi RC) / re (2)

Substituting (2) in (1):

I = (Vo – Vi)/ RF

= (Vo / RF) - (Vi/ RF)

= - [(Vi RC) / RF re] - (Vi/ RF)

I = - Vi/RF[ (RC / re )+1]

We know that, Vi = Ibre,

Ib = Ii + I

and, I = - Vi/RF[ (RC / re ) +1]

Thus, Vi = ( Ii + I ) re = Ii re + I re

= Ii re - (Vi re)( 1/RF)[ (RC / re )+1]

Taking Vi terms on left side:

Vi + (Vire)( 1/RF)[ (RC / re )+1] = Ii re

Vi[1 + (re)( 1/RF)[ (RC / re ) +1] = Ii re

Vi / Ii = re / [1 + (re)( 1/RF)[ (RC / re ) +1]

But, [ (RC / re )+1] RC / re

(because RC >> re)

Thus, Zi = Vi / Ii

= re / [1 + (re)( 1/RF)[ (RC / re )]

= re / [1 + ()(RC/RF)]

Thus, Zi = re / [(1/) + (RC/RF)]

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To find Output Impedance Zo:

Zo = RC || RF ( Note that ib = 0, thus no effect of re on Zo)

Voltage Gain AV:

Vo = - IoRC

= - IbRC ( neglecting the value of I )

= - (Vi/ re)RC

AV = Vo / Vi = - (RC/re)

Phase relation: - sign in AV indicates phase shift of 180 between input and output.

Collector DC feedback configuration

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re model

Zi = RF1 ||re

Zo = RC||RF2||ro,

for ro10RC, Zo = RC||RF2

To find Voltage Gain AV :

Vo = - Ib(RF2||RC||ro), Ib = Vi / re

Vo = - (Vi / re)(RF2||RC||ro)

Vo / Vi = - (RF2||RC||ro) / re,

for ro10RC,

AV = Vo / Vi = - (RF2||RC) / re

Determining the current gain

For each transistor configuration, the current gain can be determined directly from thevoltage gain, the defined load, and the input impedance.

We know that, current gain (Ai) = Io / Ii

Io = (Vo / RL) and Ii = Vi / Zi

Thus, Ai = - (Vo /RL) / (Vi / Zi)

= - (Vo Zi / Vi RL)

Ai = - AV Zi / RL

Example:

For a voltage divider network, we have found that, Zi = re

AV = - RC / re and RL = RC

Thus, Ai = - AV Zi / RL

= - (- RC / re )(re) / RC

Ai =

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For a Common Base amplifier, Zi = re, AV = RC / re, RL = RC

Ai = - AV Zi / RL

= - (RC / re )(re) / RC

= - 1

Effect of RL and RS:

Voltage gain of an amplifier without considering load resistance (RL) and sourceresistance (RS) is AVNL.Voltage gain considering load resistance ( RL) is AV < AVNL

Voltage gain considering RL and RS is AVS, where AVS<AVNL< AV

For a particular design, the larger the level of RL, the greater is the level of ac gain.Also, for a particular amplifier, the smaller the internal resistance of the signal source, thegreater is the overall gain.

Fixed bias with RS and RL:

AV = - (RC||RL) / re

Z i = RB|| re

Zo = RC||ro

To find the gain AVS, ( Zi and RS are in series and applying voltage divider rule)

Vi = VSZi / ( Zi+RS)

Vi / VS = Zi / ( Zi+RS)

AVS = Vo / VS = (Vo/Vi) (Vi/VS)

AVS = AV [Zi / ( Zi+RS)]

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Voltage divider with RS and RL

Voltage gain: AV = - [RC||RL] / re

Input Impedance: Zi = R1||R2|| re

Output Impedance: Zo = RC||RL||ro

Emitter follower with RS and RL

re model:

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Voltage Gain: AV = (RE||RL) / [RE||RL+re]

Input Impedance: Zi = RB || Zb

Input Impedance seen at Base: Zb = (RE||RL)

Output Impedance Zo = re

Two – port systems approach

This is an alternative approach to the analysis of an amplifier.This is important where the designer works with packaged with packaged productsrather than individual elements.An amplifier may be housed in a package along with the values of gain, input andoutput impedances.But those values are no load values and by using these values, it is required to findout the gain and various impedances under loaded conditions.This analysis assumes the output port of the amplifier to be seen as a voltage source.The value of this output voltage is obtained by Thevinising the output port of theamplifier.

Eth = AVNLVi

Model of two port system

Applying the load to the two port system

Applying voltage divider in the above system:

Vo = AVNLViRL / [ RL+Ro]

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Including the effects of source resistance RS

Applying voltage divider at the input side, we get:

Vi = VSRi /[RS+Ri]

Vo = AVNLVi

Vi = VSRi /[RS+Ri]

Vo = AVNL VSRi /[RS+Ri]

Vo/ VS = AVS = AVNLRi /[RS+Ri]

Two port system with RS and RL

We know that, at the input side

Vi = VSRi /[RS+Ri]

Vi / VS = Ri /[RS+Ri]

At the output side,

Vo = AVNLViRL / [ RL+Ro]

Vo / Vi = AVNLRL / [ RL+Ro]

Thus, considering both RS and RL:

AV = Vo / Vs

= [Vo / Vi] [Vi / Vs]

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AV = (AVNLRL / [ RL+Ro]) (Ri / [RS+Ri])

Example:

Given an amplifier with the following details:

RS = 0.2 k, AVNL = - 480, Zi = 4 k, Zo = 2 k

Determine:

AV with RL =1.2k

AV and Ai with RL= 5.6 k, AVS with RL = 1.2

Solution:

AV = AVNLRL / (RL + Ro)

= (- 480)1.2k / (1.2k+2k)

= - 180

With RL = 5.6k, AV = - 353.76

This shows that, larger the value of load resistor, the better is the gain.

AVS = [Ri /(Ri+RS)] [ RL / (RL+Ro)] AVNL

= - 171.36

Ai = - AVZi/RL, here AV is the voltage gain when RL = 5.6k.

Ai = - AVZi/RL

= - (-353.76)(4k/5.6k) = 252.6

Hybrid model

This is more accurate model for high frequency effects. The capacitors that appear arestray parasitic capacitors between the various junctions of the device. These capacitancescome into picture only at high frequencies.

• Cbc or Cu is usually few pico farads to few tens of pico farads.

• rbb includes the base contact, base bulk and base spreading resistances.

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• rbe ( r), rbc, rce are the resistances between the indicated terminals.

• rbe ( r) is simply re introduced for the CE re model.

• rbc is a large resistance that provides feedback between the output and the input.

• r = re

• gm = 1/re

• ro = 1/hoe

• hre = r / (r + rbc)

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FET small signal Analysis

• FET introduction and working principles

• FET small signal analysis

• FET self bias technique.

• Examples

• JFET self bias configuration

• Numerical

• JFET Voltage divider configuration

• JFET common drain configuration

• Source follower.

• Numerical

• JFET common gate

• Depletion mode

• Enhancement mode

• E MOSFET drain feedback configuration.

• E MOSFET voltage divider Configuration.

• numerical

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.inFET Introduction

• The Field-Effect Transistor (FET) is a type of transistor thatworks by modulating a microscopic electric field inside asemiconductor material.

• There are two general type of FET's, the MOSFET and JFET.

Symbol and representation

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.inBasic operation of JFET

• The JFET operation is compared with the water spigot.

The source of water pressure

• accumulated electrons at the negative pole of the applied voltagefrom Drain to Source

The drain of water

• electron deficiency (or holes) at the positive pole of the appliedvoltage from Drain to Source.

The control of flow of water

• Gate voltage that controls the width of the n-channel, which inturn controls the flow of electrons in the n-channel from source todrain.

JFET Operating Characteristics

There are three basic operating conditions for a JFET:

A. VGS = 0, VDS increasing to some positive value

B. VGS < 0, VDS at some positive value

C. Voltage-Controlled Resistor

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.inA. VGS = 0, VDS increasing to some positive value

Three things happen when VGS = 0 and VDS is increased from 0to a more positive voltage:

• The depletion region between p-gate and n-channel increases aselectrons from n-channel combine with holes from p-gate.

• Increasing the depletion region, decreases the size of the n-channelwhich increases the resistance of the n-channel.

• But even though the n-channel resistance is increasing, the current(ID) from Source to Drain

Through the n-channel is increasing. This is because VDS isincreasing.

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.inPinch off

Saturation

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.inAt the pinch-off point:

• any further increase in VGS does not produce any increase in ID.VGS at

pinch-off is denoted as Vp.

• ID is at saturation or maximum. It is referred to as IDSS.

• The ohmic value of the channel is at maximum.

B. VGS < 0, VDS at some positive value

As VGS becomes more negative the depletion region increases.

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.inNow Id < Idss

As VGS becomes more negative:

• the JFET will pinch-off at a lower voltage (Vp).

• ID decreases (ID < IDSS) even though VDS is increased.

• Eventually ID will reach 0A. VGS at this point is called Vp orVGS(off).

Also note that at high levels of VDS the JFET reaches a breakdownsituation. ID will increases uncontrollably if VDS > VDSmax

C. Voltage-Controlled Resistor

The region to the left of the pinch-off point is called the ohmicregion.

The JFET can be used as a variable resistor, where VGS controlsthe drain-source resistance (rd).

As VGS becomes more negative, the resistance (rd) increases.

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.inTransfer Characteristics

• The transfer characteristic of input-to-output is not as straightforward in a JFET

as it was in a BJT.

• In a BJT, β indicated the relationship between IB (input) and IC(output).

• In a JFET, the relationship of VGS (input) and ID (output) is alittle more complicated:

Current relation

Comparison between BJT & FET

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.inBJT FET

1.BJT controls large output(Ic) bymeans of a relatively small basecurrent. It is a current controlleddevice.

1.FET controls drain currentby means of small gatevoltage. It is a voltagecontrolled device

2.Has amplification factor β 2.Has trans-conductance gm.

3.Has high voltage gain 3.Does not have as high asBJT

4.Less input impedance 4.Very high input impedance

FET Small-Signal Analysis

• FET Small-Signal Model

• Trans-conductance

The relationship of VGS (input) to ID(output)is called trans-conductance.

• The trans-conductance is denoted gm.

Definition of gm using transfer characteristics

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.inExample:

Determine the magnitude of gm for a JFET with IDSS = 8mA and VP = -4V at the following dc bias points.

a. At VGS = -0.5V

b. At VGS = -1.5V

c. At VGS = -2.5V

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.inMathematical Definition of gm

FET Impedance

• Input Impedance Zi : ∞ ohms

• Output Impedance Zo: rd= 1/yos

Yos=admittance equivalent circuit parameter listed on FET specification sheets.

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.inTwo port model

FET AC Equivalent Circuit

Phase Relationship

• The phase relationship between input and output depends on theamplifier configuration circuit.

• Common – Source ~ 180 degrees

• Common - Gate ~ 0 degrees

• Common – Drain ~ 0 degrees

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.inJFET Common-Source (CS) Fixed-Bias Configuration

• The input is on the gate and the output is on the drain.

• Fixed bias configuration includes the coupling capacitors c1 and c2that isolate the dc biasing arrangements from the applied signal andload.

• They act as short circuit equivalents for the ac analysis.

AC Equivalent Circuit

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.inVoltage gain

Phase difference

Negative sign in the gain expression indicates that the output voltage is1800 phase shifted to that of input.

Example

For fixed bias circuit, the following bias data are given. VGS=-2V,IDO=5.625mA and Vp=-8V. The input voltage vi. The value of yOs=40μS.

1. Determine Gm

2. Find rd

3. Determine Zi

4. Calculate ZO, AV with and without effects of rd.

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.inJFET Self bias configuration

• Main disadvantage of fixed bias configuration requires two dcvoltage sources.

• Self bias circuit requires only one DC supply to establish thedesired operating point.

Self bias configuration

If Cs is removed, it affects the gain of the circuit

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.inAC Equivalent Circuit

• The capacitor across the source resistance assumes its short circuitequivalent for dc allowing RS to define the operating point.

• Under ac conditions the capacitors assumes short circuit state andshort circuits the Rs.

• If RS is left un-shorted, then ac gain will be reduced.

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.inRedrawn equivalent circuit:

Circuit parameters:

• Since the resulting circuit is same as that of fixed biasconfiguration, all the parameter expression remains same asevaluated for fixed bias configuration.

• Input impedance Zi=RG

• Output Impedance:ZO= rd parallel RD

Leaving Rs un-bypassed helps to reduce gain variations from device todevice by providing degenerative current feedback. However, thismethod for minimizing gain variations is only effective when asubstantial amount of gain is sacrificed.

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.inSelf bias configuration with un bypassed Rs

• Here Rs is part of the equivalent circuit .

• There is no way to reduce the network with lowest complexity.

• Carefully all the parameters have to be calculated by consideringall polarities properly

Input Impedance

• Due to open-circuit condition between gate and output network,the input impedance remains as follows:

Zi=RG

Output impedance

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.in• Output impedance is defined by

ZO= Vo/Io at vi=0

Setting Vi=0 results in following circuit.

Voltage gain:

rd

RsRDgmRs

RDZo

1

)(10 RsRDrd

gmRs

RDZo

1

rd

RsRDgmRs

gmRD

Vi

VoAv

1

gmRs

gmRDAvRsRDrd

1),(10

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.inExample: A self bias circuit has operating point defined byVGSo=-2.6V, IDq=2.6mA with IDSS=8mA and Vp=-6V.Yos=20uS

Determine

a. Gm

b. Rd

c. Zi

d. Zo with and without rd effect.

e. Av with and without rd effect

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.inJFET voltage divider configuration

AC equivalent circuit

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.inVoltage gain:

Note

• Equations for ZO and Av are same as in fixed bias.

• Only Zi is now dependent on parallel combination of R1 and R2.

JFET source follower

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.inIn a CD amplifier configuration the input is on the gate, but

the output is from the source.

AC equivalent circuit

Input and output impedance:

• Input impedance : Zi=RG

• Output impedance :

setting Vi=0V will result in the gate terminal being connecteddirectly to ground as shown in figure below.

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.inEquivalent circuit

• Applying KCL at output node

gsm

sd

oo

s

o

d

o

rdgsmo

VgRrVIresult

R

V

r

V

IIVgI RS

11:

gmRr

V

VgRr

V

VgRr

V

sdo

omsd

o

gsmsd

o

11

][11

11

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.inrd, Rs and gm are all in parallel.

Voltage gain

Since denominator is larger by a factor of one, the gain can neverbe equal to or greater than one. (as in the case of emitter follower ofBJT)

msd

msd

o

o

oo

gRr

Vg

Rr

V

I

VZ

111

111 0

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.inExample:

A dc analysis of the source follower has resulted in VGS=-2.86V andIo=4.56mA.

Determine

a. gm

b. Zi

c. rd

d. Calculate Zo with and without effect of rd.

e. Calculate Av with and without effect of rd.

Compare the results.

Given IDSS=16mA, Vp=-4V, yos=25μS.

The coupling capacitors used are 0.05μF.

JFET common gate configuration

The input is on source and the output is on the drain.Same as the common base in BJT

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.inAC equivalent circuit

Impedances:

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.inVoltage gain

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.inExample: For the network shown if VGSo=-2.2V, IDoq=2.03mA,

Determine gm,rd, Zi with and without the effect of rd, Av with andwithout the effect of rd.

Also find Vo with and without rd. compare the results.

C1 and c2 are given by 10uf.

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.inMOSFETs:

MOSFETs are of two types;

Depletion type

Enhancement type

1. Depletion type MOSFETs

• Shockley’s equation is also applicable to depletion typeMOSFETs.

• This results in same equation for gm.

• The ac equivalent model for this MOS device is same as JFET.

• Only difference is VGSo is positive for n-channel device andnegative for p-channel device.

• As a result of this, gm can be greater than gmo.

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.in• Range of rd is very similar to that of JFETs.

D-MOSFET ac equivalent model

Example:A network shown below has the dc analysis results asIDSS=6mA, VP=3V,VGSo=1.5V and IDQ=7.6mA.yos=10uS

a.Determine gm and compare with gmo

b.Find rd

c.Sketch ac equivalent circuit

d.Find Zi,Zo and Av.

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.inSolution:

• gmo=4mS

• gm=6mS

• gm is 50% more than gmo

• rd= 100K Ω

• Zi=10M Ω parallel with 110M Ω =9.17MΩ

• Zo=100K Ω parallel with 1.8K Ω=1.8KΩ

• Av=-gmrd= 10.8

Ac equivalent circuits

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.inEnhancement type MOSFET

• There are two types of E-MOSFETs:

nMOS or n-channel MOSFETs

pMOS or p-channel MOSFETs

E-MOSFET ac small signal model

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.in• ID=k(VGS-VGS(Th))2

• gm is defined by

• Taking the derivative and solving for gm,

gm=2k(VGS-VGS(th))

EMOSFET drain feedback configuration

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.inAc equivalent model

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.inInput and output impedances

Voltage gain

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.inNumerical

For the above said configuration, the following results were got.K=0.24X10-3A/V2, VgsQ=6.4V, IDQ=2.75mA. Determine gm, rd, Zi withand without the effect of rd, Zo with and without the effect of rd. Avwith and without effect of rd. And compare the results. Id(sat)=6mA,VGS(th)=3V, VGS(on)=6V,yos=20uS.

• RD=2K ohms

• RF=10M ohms

• C1,c2=1uF

Solution.

• gm=2k(VGS-VGS(th))

=1.63mS.

• rd=1/yos=50KΩ

• Zi with rd:

)//(1

)//(

Ddm

Ddf

Rrg

RrRZi

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• Zi without effect of rd:

= 2.53MΩ

• Zo with rd: (RF parallel rd parallel RD)

= 1.92KΩ

• Zo without rd: Zo=RD = 2KΩ

• Gain AV with rd:

• = -3.21

• Without effect of rd:

• = -3.26

Dm

Fi

Rg

RZ

1

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.inE MOSFET voltage divider configuration

Important Parameters

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CHAPTER.6 :TRANSISTOR FREQUENCY RESPONSE

• To understand– Decibels, log scale, general frequency considerations of an amplifier.– low frequency analysis - Bode plot– low frequency response – BJT amplifier– Miller effect capacitance– high frequency response – BJT amplifier

Introduction

It is required to investigate the frequency effects introduced by the larger capacitiveelements of the network at low frequencies and the smaller capacitive elements of theactive device at high frequencies. Since the analysis will extend through a wide frequencyrange, the logarithmic scale will be used.

Logarithms

To say that logaM = x means exactly the same thing as saying ax = M .

For example: What is log28?

"To what power should 2 be raised in order to get 8?" Since 8 is 23 the answer is "3." So log28 = 3

Basic Rules

Logarithmic Rule 1:

Logarithmic Rule 2:

Logarithmic Rule 3:

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Natural Logarithm (or base e)

• There is another logarithm that is also useful (and in fact more common in naturalprocesses). Many natural phenomenon are seen to exhibit changes that are eitherexponentially decaying (radioactive decay for instance) or exponentiallyincreasing (population growth for example).

• These exponentially changing functions are written as ea, where ‘a’ represents therate of the exponential change.

• In such cases where exponential changes are involved, we usually use anotherkind of logarithm called natural logarithm. The natural log can be thought of asLogarithm Base-e.

• This logarithm is labeled with ln (for "natural log"), where, e = 2.178.

Semi – Log graph

Decibels

• The term decibel has its origin in the fact that the power and audio levels are relatedon a logarithmic basis. The term bel is derived from the surname of AlexanderGraham Bell.

• Bel is defined by the following equation relating two power levels, P1 and P2:G = [log10 P2 / P1] bel

• It was found that, the Bel was too large a unit of measurement for the practicalpurposes, so the decibel (dB) is defined such that 10 decibels = 1 bel.

• Therefore,GdB = [10 log10 P2 / P1 ] dB

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The decimal rating is a measure of the difference in magnitude between two powerlevels.

For a specified output power P2, there must be a reference power level P1. Thereference level is generally accepted to be 1mW.

GdBm = [10 log10 P2 / 1mW ] dBm

GdB = [10 log10 P2 / P1 ] dB

= [10 log10 (V22 / Ri ) / (V12 / Ri )] dB

= 10 log10 (V2 / V1)2

GdB = [20 log10 V2 / V1 ] dB

One of the advantages of the logarithmic relationship is the manner in which it can beapplied to cascaded stages wherein the overall voltage gain of a cascaded system is thesum of individual gains in dB.

AV = (Av1)(Av2)(Av3)…….

AVdB = (Av1dB)+(Av2dB)+(Av3dB)…….

Problem1:

Find the magnitude gain corresponding to a voltage gain of 100dB.

GdB = [20 log10 V2 / V1 ] dB = 100dB

= 20 log10 V2 / V1 ;

V2 / V1 = 105 = 100,000

Problem 2:

The input power to a device is 10,000W at a voltage of 1000V. The output power is500W and the output impedance is 20.

Find the power gain in decibels. Find the voltage gain in decibels.

GdB = 10 log10 (Po/Pi)= 10 log10 (500/10k)= -13.01dB

GV = 20 log10 (Vo/Vi)= 20 log10 (PR/1000)= 20 log10 [(500)(20)/1000]= - 20dB

( Note: P = V2/R; V = PR)

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Problem 3 :

An amplifier rated at 40 W output is connected to a 10 speaker.a. Calculate the input power required for full power output if the power gain is 25dB.b. Calculate the input voltage for rated output if the amplifier voltage gain is 40dB.

a. 25 = 10 log10 40/Pi

Pi = 40 / antilog(2.5) = 126.5mW

b. GV = 20log10Vo/Vi ;

40 = 20log10Vo/Vi

Vo /Vi = antilog 2 = 100

Also, Vo = PR = (40)(10) = 20V

Thus, Vi = Vo / 100 = 20/100 = 200mV

General Frequency considerations

• At low frequencies the coupling and bypass capacitors can no longer be replacedby the short – circuit approximation because of the increase in reactance of theseelements.

• The frequency – dependent parameters of the small signal equivalent circuits andthe stray capacitive elements associated with the active device and the networkwill limit the high frequency response of the system.

• An increase in the number of stages of a cascaded system will also limit both thehigh and low frequency response.

• The horizontal scale of frequency response curve is a logarithmic scale to permit aplot extending from the low to the high frequency

• For the RC coupled amplifier, the drop at low frequencies is due to the increasingreactance of CC and CE, whereas its upper frequency limit is determined by eitherthe parasitic capacitive elements of the network or the frequency dependence ofthe gain of the active device.

• In the frequency response, there is a band of frequencies in which the magnitudeof the gain is either equal or relatively close to the midband value.

• To fix the frequency boundaries of relatively high gain, 0.707AVmid is chosen tobe the gain at the cutoff levels.

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• The corresponding frequencies f1 and f2 are generally called corner, cutoff, band,break, or half – power frequencies.

• The multiplier 0.707 is chosen because at this level the output power is half themidband power output, that is, at mid frequencies,

•PO mid = | Vo2| / Ro = | AVmidVi|

2 / RO

• And at the half – power frequencies,

POHPF = | 0.707 AVmidVi|2 / Ro

= 0.5| AVmid Vi|2 / Ro

• And, POHPF = 0.5 POmid

• The bandwidth of each system is determined by f2 – f1

• A decibel plot can be obtained by applying the equation,

(AV / AVmid )dB

= 20 log10 (AV / AVmid)

Most amplifiers introduce a 180 phase shift between input and output signals. At lowfrequencies, there is a phase shift such that Vo lags Vi by an increased angle. At highfrequencies, the phase shift drops below 180.

Low – frequency analysis – Bode plot

In the low frequency region of the single – stage BJT amplifier, it is the RC combinationsformed by the network capacitors CC and CE, the network resistive parameters thatdetermine the cutoff frequencies.

Frequency analysis of an RC network

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• Analysis of the above circuit indicates that,

XC = 1/2fC 0

• Thus, Vo = Vi at high frequencies.

• At f = 0 Hz, XC = , Vo = 0V.

• Between the two extremes, the ratio, AV = Vo / Vi will vary.As frequency increases, the capacitive reactance decreases and more of the inputvoltage appears across the output terminals.

The output and input voltages are related by the voltage – divider rule:

Vo = RVi / ( R – jXC)

the magnitude of Vo = RVi / R2 + XC2

• For the special case where XC = R,

Vo =RVi / R2 = (1/2) Vi

AV = Vo / Vi = (1/2) = 0.707

• The frequency at which this occurs is determined from,

XC = 1/2f1C = R

where, f1 = 1/ 2RC

• Gain equation is written as,

AV = Vo / Vi

= R / (R – jXC) = 1/ ( 1 – j(1/CR)

= 1 / [ 1 – j(f1 / f)]

• In the magnitude and phase form,

AV = Vo / Vi

= [1 / 1 + (f1/f)2 ] tan-1 (f1 / f)

• In the logarithmic form, the gain in dB is

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AV = Vo / Vi = [1 / 1 + (f1/f)2 ]

= 20 log 10 [1 / 1 + (f1/f)2 ]

= - 20 log 10 [ 1 + (f1/f)2]

= - 10 log10 [1 + (f1/f)2]

• For frequencies where f << f1 or (f1/ f)2 the equation can be approximated by

AV (dB) = - 10 log10 [ (f1 / f)2]

= - 20 log10 [ (f1 / f)] at f << f1

• At f = f1 ;

f1 / f = 1 and

– 20 log101 = 0 dB

• At f = ½ f1;

f1 / f = 2

– 20 log102 = - 6 dB

• At f = ¼ f1;

f1 / f = 4

– 20 log102 = - 12 dB

• At f = 1/10 f1;

f1 / f = 10

– 20 log1010 = - 20dB

• The above points can be plotted which forms the Bode – plot.

• Note that, these results in a straight line when plotted in a logarithmic scale.Although the above calculation shows at f = f1, gain is 3dB, we know that f1 isthat frequency at which the gain falls by 3dB. Taking this point, the plot differsfrom the straight line and gradually approaches to 0dB by f = 10f1.

Observations from the above calculations:

• When there is an octave change in frequency from f1 / 2 to f1, there existscorresponding change in gain by 6dB.

• When there is an decade change in frequency from f1 / 10 to f1, there existscorresponding change in gain by 20 dB.

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Low frequency response – BJT amplifier

• A voltage divider BJT bias configuration with load is considered for this analysis.• For such a network of voltage divider bias, the capacitors CS, CC and CE will

determine the low frequency response.

Let us consider the effect of each capacitor independently.

CS:

• At mid or high frequencies, the reactance of the capacitor will be sufficientlysmall to permit a short – circuit approximations for the element.

• The voltage Vi will then be related to Vs by

Vi |mid = VsRi / (Ri+Rs)

• At f = FLS, Vi = 70.7% of its mid band value.

sLs

Ri)C(Rs2

1f

βre||R2||R1Ri

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• The voltage Vi applied to the input of the active device can be calculated using thevoltage divider rule:

Vi = RiVs / ( Ri+ Rs – jXCs)Effect of CC:

• Since the coupling capacitor is normally connected between the output of theactive device and applied load, the RC configuration that determines the lowcutoff frequency due to CC appears as in the figure given below.

•

• Ro = Rc|| ro

Effect of CE:

)CcRRo(π2

1f

LLC

EeLE

CRπ2

1f )r

βsR

(||RR eEe

R2||R1||RssR

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• The effect of CE on the gain is best described in a quantitative manner by recallingthat the gain for the amplifier without bypassing the emitter resistor is given by:

AV = - RC / ( re + RE)• Maximum gain is obviously available where RE is 0.• At low frequencies, with the bypass capacitor CE in its “open circuit” equivalent

state, all of RE appears in the gain equation above, resulting in minimum gain.• As the frequency increases, the reactance of the capacitor CE will decrease,

reducing the parallel impedance of RE and CE until the resistor RE is effectivelyshorted out by CE.

• The result is a maximum or midband gain determined by AV = - RC / re.• The input and output coupling capacitors, emitter bypass capacitor will affect only

the low frequency response.• At the mid band frequency level, the short circuit equivalents for these capacitors

can be inserted.• Although each will affect the gain in a similar frequency range, the highest low

frequency cutoff determined by each of the three capacitors will have the greatestimpact.

Problem:

Determine the lower cutoff freq. for the network shown using the followingparameters:

Cs = 10μF, CE = 20μF, Cc = 1μF

Rs = 1kΩ, R1= 40kΩ, R2 = 10kΩ,

RE = 2kΩ, RC = 4kΩ, RL = 2.2kΩ,

β = 100, ro = ∞Ω, Vcc = 20V

• Solution:

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a. To determine re for the dc conditions, let us check whether RE > 10R2

Here, RE = 200k, 10R2 = 100k. The condition is satisfied. Thus approximate

analysis can be carried out to find IE and thus re.

VB = R2VCC / ( R1+R2) = 4V

VE = VB – 0.7 = 3.3V

IE = 3.3V / 2k = 1.65mA

re = 26mV / 1.65mA = 15.76

Mid band gain:

AV = Vo / Vi = -RC||RL / re = - 90

• Input impedance

Zi = R1 || R2|| re = 1.32K

• Cut off frequency due to input coupling capacitor ( fLs)

fLs = 1/ [2(Rs +Ri)CC1 = 6.86Hz.

fLc = 1 / [2(RC + RL) CC

= 1 / [ 6.28 (4k + 2.2k)1uF]

= 25.68 Hz

Effect of CE:

RS = RS||R1||R2 = 0.889

Re = RE || (RS/ + re) = 24.35

fLe = 1/2 ReCE = 327 Hz

fLe = 327 Hz

fLC = 25.68Hz

fLs = 6.86Hz

In this case, fLe is the lower cutoff frequency.

• In the high frequency region, the capacitive elements of importance are the inter-electrode ( between terminals) capacitances internal to the active device and thewiring capacitance between leads of the network.

• The large capacitors of the network that controlled the low frequency response areall replaced by their short circuit equivalent due to their very low reactance level.

• For inverting amplifiers, the input and output capacitance is increased by acapacitance level sensitive to the inter-electrode capacitance between the inputand output terminals of the device and the gain of the amplifier.

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Miller Effect Capacitance

• Any P-N junction can develop capacitance. This was mentioned in the chapter ondiodes.

• In a BJT amplifier this capacitance becomes noticeable between: the Base-Collector junction at high frequencies in CE BJT amplifier configurations.

• It is called the Miller Capacitance.• It effects the input and output circuits.

•• Ii = I1 + I2 Eqn (1)

• Using Ohm’s law yields

I1 = Vi / Zi,

I1 = Vi / R1

and I2 = (Vi – Vo) / Xcf

= ( Vi – AvVi) / Xcf

I2 = Vi(1 – Av) / Xcf

Substituting for Ii, I1 and I2 in eqn(1),

Vi / Zi = Vi / Ri + [(1 – Av)Vi] /Xcf

1/ Zi = 1/Ri + [(1 – Av)] /Xcf

1/ Zi = 1/Ri + 1/ [Xcf / (1 – Av)]

1/ Zi = 1/Ri + 1/ XCM

Where, XCM = [Xcf / (1 – Av)]

= 1/[ (1 – Av) Cf]

CMi = (1 – Av) Cf

CMi is the Miller effect capacitance.

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• For any inverting amplifier, the input capacitance will be increased by a Millereffect capacitance sensitive to the gain of the amplifier and the inter-electrode( parasitic) capacitance between the input and output terminals of the activedevice.

Miller Output Capacitance (CMo)

Applying KCL at the output node results in:

Io = I1+I2

I1 = Vo/Ro

and I2 = (Vo – Vi) / XCf

The resistance Ro is usually sufficiently large to permit ignoring the first term of theequation, thus

Io (Vo – Vi) / XCf

Substituting Vi = Vo / AV,

Io = (Vo – Vo/Av) / XCf

= Vo ( 1 – 1/AV) / XCf

Io / Vo = (1 – 1/AV) / XCf

Vo / Io = XCf / (1 – 1/AV)

= 1 / Cf (1 – 1/AV)

= 1/ CMo

CMo = ( 1 – 1/AV)Cf

fMo CC

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CMo Cf [ |AV| >>1]

If the gain (Av) is considerably greater than 1:

High frequency response – BJT Amplifier

• At the high – frequency end, there are two factors that define the – 3dB cutoff point:– The network capacitance ( parasitic and introduced) and– the frequency dependence of hfe()

Network parameters

• In the high frequency region, the RC network of the amplifier has the configurationshown below.

• At increasing frequencies, the reactance XC will decrease in magnitude, resultingin a short effect across the output and a decreased gain.

Vo = Vi(-jXC) / R -jXC

Vo / Vi = 1/[ 1+j(R/XC)] ; XC = 1/2fC

AV = 1/[ 1+j(2fRC)];

AV = 1/[ 1+jf/f2]

o This results in a magnitude plot that drops off at 6dB / octave with increasingfrequency.

fMo CC

ViVo

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Network with the capacitors that affect the high frequency response

• Capacitances that will affect the high-frequency response:

Cbe, Cbc, Cce – internal capacitances

Cwi, Cwo – wiring capacitances

CS, CC – coupling capacitors

CE – bypass capacitor

The capacitors CS, CC, and CE are absent in the high frequency equivalent of the BJTamplifier.The capacitance Ci includes the input wiring capacitance, the transitioncapacitance Cbe, and the Miller capacitance CMi.The capacitance Co includes theoutput wiring capacitance Cwo, the parasitic capacitance Cce, and the output Millercapacitance CMo.In general, the capacitance Cbe is the largest of the parasiticcapacitances, with Cce the smallest.As per the equivalent circuit,

fH = 1 / 2RthiCi

Rthi = Rs|| R1||R2||Ri

Ci = Cwi+Cbe+CMi = CWi + Cbe+(1- AV) Cbe

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At very high frequencies, the effect of Ci is to reduce the total impedance of theparallel combination of R1, R2, Ri, and Ci.The result is a reduced level of voltageacross Ci, a reduction in Ib and the gain of the system.For the output network,

fHo = 1/(2RThoCo)

RTho = RC||RL||ro

Co = Cwo+Cce+CMo

At very high frequencies, the capacitive reactance of Co will decrease andconsequently reduce the total impedance of the output parallel branches.The net result is that Vo will also decline toward zero as the reactance Xc becomessmaller.The frequencies fHi and fHo will each define a -6dB/octave asymtote.If the parasitic capacitors were the only elements to determine the high – cutofffrequency, the lowest frequency would be the determining factor.However, thedecrease in hfe(or ) with frequency must also be considered as to whether its breakfrequency is lower than fHi or fHo.

hfe (or ) variation

• The variation of hfe( or ) with frequency will approach the following relationship

hfe = hfe mid / [1+(f/f)]

• f is that frequency at which hfe of the transistor falls by 3dB with respect to itsmid band value.

• The quantity f is determined by a set of parameters employed in the hybrid model.

• In the hybrid model, rb includes the• base contact resistance

• base bulk resistance

• base spreading resistance

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Hybrid model

• The resistance ru(rbc) is a result of the fact that the base current is somewhatsensitive to the collector – to – base voltage.

• Since the base – to – emitter voltage is linearly related to the base current throughOhm’s law and the output voltage is equal to the difference between the base thebase – to – emitter voltage and collector – to – base voltage, we can say that thebase current is sensitive to the changes in output voltage.

• Thus,

f = 1/[2r(C+Cu)]

r = re = hfe mid re

• Therefore,

f = 1/[2 hfemid re(C+Cu)]

OR

f = 1/[2 mid re(C+Cu)]

• The above equation shows that, f is a function of the bias configuration.

• As the frequency of operation increases, hfe will drop off from its mid band valuewith a 6dB / octave slope.

• Common base configuration displays improved high frequency characteristicsover the common – emitter configuration.

• Miller effect capacitance is absent in the Common base configuration due to noninverting characteristics.

• A quantity called the gain – bandwidth product is defined for the transistor by thecondition,

| hfemid / [1+j(f/f)| = 1

• So that,

|hfe|dB = 20 log10 | hfemid / [1+j(f/f)|

= 20 log101 = 0 dB

• The frequency at which |hfe|dB = 0 dB is indicated by fT.

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| hfemid / [1+j(f/f)| = 1

hfemid / 1+ (fT/f)2 hfemid / (fT/f) =1

( by considering fT>>f)

• Thus, fT = hfemid f OR fT = mid f

• But, f = 1/[2 mid re(C+Cu)]

fT = (mid) 1/[2 mid re(C+Cu)]

fT = 1/[2 re(C+Cu)]

Problem:

For the amplifier with voltage divider bias, the following parameters are given:

RS = 1k , R1 = 40k, R2 = 10k, Rc = 4k, RL = 10k

Cs = 10F, Cc = 1 F, CE= 20 F

= 100, ro = , VCC = 10

C = 36pF, Cu = 4pF, Cce=1pF, Cwi=6pF, Cwo=8pF

a. Determine fHi and fHo

b. Find f and fT

Solution:

To find re, DC analysis has to be performed to find IE.

VB = R2VCC / R1+R2 = 2V

VE = 2 – 0.7 = 1.3V

IE = 1.3/1.2K = 1.083mA

re = 26mV / 1.083mA

re = 24.01,

re = 2.4k

Ri = RS||R1||R2||re

Ri = 1.85k

AV = Vo/Vi = - (Rc ||RL) / re

AV = - 119

RThi = Rs||R1||R2||Ri

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RThi = 0.6k

To determine fHi and fHo:

fHi = 1/[2RThiCi] ;

Ci = Cwi+Cbe+(1 – AV)Cbc

= 6pF + 36pF + (1 – (-119)) 4pF

Ci = 522pF

fHi = 1/2RThiCi

fHi = 508.16kHz

RTho = Rc||RL

RTho = 2.86k

Co = Cwo+Cce+C Mo

= 8pF+1pF+(1 – (1/-119))4pF

Co = 13.03pF

fHo = 1/2RThoCo

fHo = 8.542MHz

f = 1/[2 mid re(C+Cu)]

f = 1.66MHz

fT = f

fT = 165.72MHz

Summary – Frequency response of BJT Amplifiers

• Logarithm of a number gives the power to which the base must be brought toobtain the same number

• Since the decibel rating of any equipment is a comparison between levels, areference level must be selected for each area of application.

• For Audio system, reference level is 1mW• The dB gain of a cascaded systems is the sum of dB gains of each stage.• It is the capacitive elements of a network that determine the bandwidth of a

system.• The larger capacitive elements of the design determine the lower cutoff

frequencies.• Smaller parasitic capacitors determine the high cutoff frequencies.• The frequencies at which the gain drops to 70.7% of the mid band value are called

– cutoff, corner, band, break or half power frequencies.• The narrower the bandwidth, the smaller is the range of frequencies that will

permit a transfer of power to the load that is atleast 50% of the midband level.

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• A change in frequency by a factor of 2, is equivalent to one octave which resultsin a 6dB change in gain.

• For a 10:1 change in frequency is equivalent to one decade results in a 20dBchange in gain.

• For any inverting amplifier, the input capacitance will be increased by a Millereffect capacitance determined by the gain of the amplifier and the inter electrode( parasitic) capacitance between the input and output terminals of the activedevice.

CMi = (1 – AV)Cf

• Also, CMo Cf (if AV >>1)

• A 3dB drop in will occur at a frequency defined by f, that is sensitive to the DCoperating conditions of the transistor.

• This variation in defines the upper cutoff frequency of the design.

Problems:

1. The total decibel gain of a 3 stage system is 120dB. Determine the dB gain ofeach stage, if the second stage has twice the decibel gain of the first and the thirdhas 2.7 times decibel gain of the first. Also, determine the voltage gain of the eachstage.

• Given: GdBT = 120dB

We have GdBT = GdB1+GdB2+GdB3

Given, GdB2 = 2GdB1

GdB3 = 2.7GdB1

Therefore, 120dB = 5.7GdB1

GdB1 = 21.05,

GdB2 = 42.10

GdB3 =56.84

We have GdB = 10 log[Vo / Vi]

Vo / Vi = antilog ( GdB/10)

G1 = 127.35

G2 = 16.21k

G3 = 483.05k

2. If the applied ac power to a system is 5W at 100mV and the output power is 48W,determine

a. The power gain in decibels

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b. The output voltagec. The voltage gain in decibels, if the output impedance is 40k.d. The input impedance

Given: Pi = 5W.Vi = 100mV, Po = 48w Ro = 40k

a. GdB =10 log [48/ 5] = 69.82

b. Po = Vo2 /Ro,

Vo = PoRo = 1385.64V

c. Voltage gain in dB = 20 log [1385.64/100m] = 82.83

d. Ri = Vi2 / Pi = 2k

General steps to solve a given problem:

Normally, the amplifier circuit with all the values of biasing resistors, value of andvalues inter electrode capacitances ( Cbe, Cbc and Cce) will be given.It is required to calculate: fLS, fLC and fLE

Also, fHi, fHo, f and fT

• Step1: Perform DC analysis and find the value of IE, and re

– Find the value of Ri ( Zi) using the value of re

– Find the value of AVmid

• Step 2: Find fLS using the formula 1/2(Ri+RS)CS

• Step 3: Find fLC using the formula 1/2(RC+RL)CC

• Step 4: Determine the value of fLE using the formula 1/2ReCE

where, Re = RE || [(RS)/ + re]

RS = RS||R1||R2

• Step 5: Determine fHi using the formula 1/2RThiCi

where RThi = R1||R2||RS||re

Ci = Cwi + Cbe + (1-AV)Cbc

• Step 6: Determine fHo using the formula 1/2RThoCo

where RTho = RC||RL||ro

Co = Cwo + Cce+ C bc

• Step 7: Determine f using the formula 1/[2 mid re(C+Cu)]

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22

• Step 8: Determine fT using the formula fT = mid f

Problem: Determine the following for the given network:

1. fLs

2. fLc

3. fLE

4. fHi

5. fHo

6. f and fT

• Given:

VCC = 20V, RB = 470k, RC = 3k, RE = 0.91k, RS = 0.6k, RL = 4.7k

CS = CC = 1F, CE = 6.8 F

Cwi = 7pF, Cwo=11pF, Cbe = 6pF, Cbe = 20pF and Cce = 10pF

Solution:

IB = (VCC – VBE) / [RB + ( +1)RE]

IB = 3.434mA

IE = IB

IE = 3.434mA

re = 26mV / IE

re = 7.56

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.in

23

AV = - (RC||RL) / re

AV = -242.2

Zi = RB|| re

Zi = 754.78

fLS = 1/2(Ri+RS)CS

fLS = 117.47Hz

fLC = 1/2(RC+RL)CC

fLC = 20.66 Hz

fLE = 1/2ReCE ;

where, Re = [(RS /)+ re] || RE

RS = RB || RS

fLE = 1.752kHz

Ci = Cwi + Cbe + (1 – AV) Cbc

Ci = 1.48nF

RThi = RS || RB|| re

RThi = 334.27

fHi = 1 / 2(1.48nF)(334.37)

fHi = 321.70 KHz

Co = CWo + Cce + (1 – 1/AV) Cbc

Co = 27.02pF

RTho = RC || RL

RTho = 1.83K

fHo = 1 / 2(27.02p)(1.83k)

fHo = 3.21MHz

f = 1 / 2 (100) (7.56)( 20p + 6p)

f = 8.09MHz

fT = f

fT = 803MHz

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.in

24

Equations - Logarithms

1. a = bx, x = logba

2. GdB = 10 log P2 / P1

3. GdB = 20 log V2 / V1

Equations – Low frequency response

1. AV = 1 / [1 – j(f1/f)],

where, f1 = 1/2RC

Equations – BJT low frequency response

1. fLs = 1 / [2(RS+Ri)CS] ,

where, Ri = R1||R2||re

2. fLC = 1 /[2(Ro+RL)CC],

where, Ro = RC||ro

3. fLE = 1 / 2ReCE,

where, Re = RE || ( RS/ +re) and RS = RS||R1||R2

Miller effect Capacitance

CMi = (1 – AV)Cf,

CMO = ( 1 – 1/AV)Cf

BJT High frequency response:

1. AV = 1/ [1 + j(f/f2)]

2. fHi = 1 / 2RThiCi,

where, RThi = RS||R1||R2||Ri, Ci = CWi+Cbe+ CMi

3. fHO = 1/ 2RThoCo,

where, RTho = RC||RL||ro

Co = CWo+Cce+ CMo

4. f = 1/[2 mid re(C+Cu)]

5. fT = f

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lution


Power Amplifiers

• Introduction

• Definitions and amplifier types

• Series fed class A amplifiers

• Transformer coupled class A amplifier

• Transformer coupled amplifier continuation

• Numerical

• Class B amplifier operation

• Class B amplifier circuits

• Numerical

• Amplifier distortion

• Numerical

• Second harmonic distortion

• Power transistor heat sinking

• Thermal analogy of power transistor

• Class C and class D amplifiers

• Numerical

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.inIntroduction

Amplifier receives a signal from some pickup transducer or other input

source and provides larger version of the signal.

In small signal amplifiers the main factors are usually amplification,

linearity and magnitude of gain.

Classes of PAs

Amplifier classes represent the amount the output signal varies over one

cycle of operation for a full cycle of input signal

So the following classes of PA are defined

Class A

Class B

Class AB

Class C

Class D

Class A amplifier• Class A amplifying devices operate over the whole of the input cycle such

that the output signal is an exact scaled-up replica of the input with no

clipping. Class A amplifiers are the usual means of implementing small-

signal amplifiers. They are not very efficient. a theoretical maximum of 50%

is obtainable with inductive output coupling and only 25% with capacitive

coupling.

• In a Class A circuit, the amplifying element is biased so the device is always

conducting to some extent, and is operated over the most linear portion of its

characteristic curve Because the device is always conducting, even if there is

no input at all, power is drawn from the power supply. This is the chief

reason for its inefficiency.

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.inClass B

• Class B amplifiers only amplify half of the input wave cycle. As such they

create a large amount of distortion, but their efficiency is greatly improved

and is much better than Class A. Class B has a maximum theoretical

efficiency of 78.5% (i.e., π/4). This is because the amplifying element is

switched off altogether half of the time, and so cannot dissipate power.

• A single Class B element is rarely found in practice, though it can be used in

RF power amplifier where the distortion levels are less important. However

Class C is more commonly used for this.

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.inClass AB

• A practical circuit using Class B elements is the complementary pair or

"push–pull" arrangement. Here, complementary or quasi-complementary

devices are used to each amplify the opposite halves of the input signal,

which is then recombined at the output. This arrangement gives excellent

efficiency, but can suffer from the drawback that there is a small mismatch

at the "joins" between the two halves of the signal..

• Class AB sacrifices some efficiency over class B in favor of linearity, so will

always be less efficient (below 78.5%). It is typically much more efficient

than class A.

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.inClass C

• Class C amplifiers conduct less than 50% of the input signal and the

distortion at the output is high, but high efficiencies (up to 90%) are

possible. Some applications (for example, megaphones) can tolerate the

distortion. A much more common application for Class C amplifiers is in RF

transmitters, where the distortion can be vastly reduced by using tuned loads

on the amplifier stage.

• The input signal is used to roughly switch the amplifying device on and off,

which causes pulses of current to flow through a tuned circuit.

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.inClass D

• Class D amplifiers are much more efficient than Class AB power amplifiers.

As such, Class D amplifiers do not need large transformers and heavy

heatsinks, which means that they are smaller and lighter in weight than an

equivalent Class AB amplifier. All power devices in a Class D amplifier are

operated in on/off mode.

• These amplifiers use pulse width modulation,

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.inComparison of Amplifier classes

Series fed class A amplifiers

It is a fixed bias circuit.

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.inDC bias operation

The DC bias set by Vcc and Rb

Collector current IC=βIB

Collector –emitter voltage

VCE=VCC-ICRC

Load line

Power considerations

The power into an amplifier is provided by the power supply

With no input supply, current drawn is collector bias current ICq.

pi(dc)=VCCICq

Output power

The output voltage and current varying around the bias point provide ac

power to the load.

BB

R

VVccI

7.0

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.inUsing rms signals

P0(ac)=VCE(rms)IC(rms)

=I2C(rms) Rc

=V2C(rms)/Rc

Using peak signals

The ac power delivered to the load is

p0={VCE(p) IC(p)} / 2

or = {I2c(p)/2} Rc

={V2CE(p)}/2Rc

Using peak-peak signals

P0(ac)={VCE(p-p) IC(p-p)}/8

= {I2c(p-p)/8} Rc

={V2CE(p)}/8Rc

Efficiency

Efficiency of an amplifier represents the amount of ac power delivered from

dc source. It can be calculated using

Maximum Efficiency

Maximum voltage swing VCE(p-p)=VCC

Maximum current swing IC(p-p)=VCC/RC

Maximum power

The maximum power input evaluated using dc bias current set to half of the

maximum value….

100)()(

% xdcPiacPo

8

)/()(

RcVccVccacPo

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.in Maximum Pi(dc)=VCC(maximum IC)

Maximum efficiency = {maximum Po(ac)/

maximum Pi(dc)} x100

= 25%

Maximum efficiency

The maximum efficiency of a class A series fed amplifier is thus seen to be

25%.

The maximum efficiency occurs only for ideal conditions of both voltage

and current swing .thus practical circuits will have less than this percentage.

Numerical

Calculate input power, output power and efficiency of the amplifier circuit for the

circuit shown below for an input voltage that increases the base current by 10mA

peak.

Data given

VCC=20V

Rc=20 ohms

RB=1k ohms

β=25

2

/ RcVccVcc

1002/

8/2

2

xRcccV

RcccV

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.inSolution

Hint: use the above derived formulae

Po(ac)=0.625W

Pi(dc)=9.6W

Efficiency=6.5%

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.inTransformer coupled class A amplifier

The transformer can step up or step down a voltage applied to primary coil .

Transformer coupled class A PA• A form of class A amplifier having maximum efficiency of 50% uses

transformer to couple the output signal to the load.

Impedance transformation

If α=N1/N2 Then Above equation reduces to

1

2

1

2

N

N

V

V

2

1

1

2

N

N

I

I

2

1 1

2

1

2

1

2

2

1

2

2

1/1

2/2

1

2

N

N

N

N

N

N

I

I

I

V

IV

IV

R

R

RL

RL

221

2

1

2

1

N

N

R

R

RL

RL

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.inLoad resistance reflected to the primary side as,

Transformer coupled amplifier

• Drawing DC and AC load line

• Signal swing and output AC power

Power across the load can be expressed as

• IL=I2=N1/N2 IC

• with the output ac power then calculated using

PL=IL2(rms) RL

RLRL

OR

RR

21

2 21

8

))(( minmaxminmax)(

minmax)(

minmax)(

CCCECEaco

CCppC

CECEppCE

IIVVP

III

VVV

11

22 V

N

NVVL

L

rmsLL R

VP )(

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.inNumericalCalculate the ac power delivered to 8 ohm speaker for the circuit shown below.

The circuit component values result in a dc base current of 6mA, and the input

signal Vi results in a peak base current swing of 4mA.

Solution:

Step 1: dc load line is drawn vertically from voltage point

VCEQ=VCC=10V

Step 2: for IB=6mA the operating point

VCEQ=10V & ICQ=140mA

Step 3: the effective resistance seen at the primary is RL’=(N1/N2)2 RL =72 ohms.

Step 4: the ac load line can be drawn of slope 1/72.

IC=VCE/RL’=10/72=139mA

Mark point A on graph..

ICEQ+IC=140mA+139mA

Connect point A through the point Q to obtain the ac load line.

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.inFor a given base current of 4mA peak , the maximum and minimum collector

current and collector –emitter voltage obtained from graph ..

Efficiency

The input dc power obtained from the supply is calculated from the supply dc

voltage and thus average power drawn from the supply Pi(dc)= VCC ICQ

For the transformer coupled amplifier power dissipated by the transformer is small

(due to small resistance)

The only power loss considered here is that dissipated by the power transistor and

calculated by

PQ=Pi(dc) - Po(ac)

Maximum theoretical efficiency

8

))(()( minmaxminmax CCCECE

o

IIVVacP

Wmm

acPo 477.08

)25255)(7.13.18()(

100)()(

% xdcPiacPo

%min)max(

min)max(50%

2

VCEVCE

VCEVCE

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.inLarger the value of VCEmax and smaller the value of VCEmin, the closer the

efficiency approaches the theoretical limit of 50%

Numerical

Calculate the efficiency of a transformer coupled class A amplifier for a supply of

12V and outputs of :

a. V(p)=12V

b. V(p)=6V

c. V(p)=2V

Solution :

Here VCE=VCC=12V, the maximum and minimum of the voltage swing are

VCEmax=VCEQ+V(p)=12V+12V=24V

VCEmin=VCEQ-V(p)=12V-12V=0V

This results in efficiency of ,

Case ii.



This results in efficiency of 12.5%

Case iii.



This results in efficiency of 1.39%

%50024

02450%

2

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.inClass B Amplifier operation

• Class B operation is provided when the dc bias leaves the transistor biased

just off, the transistor turning on when the ac signal is applied.

• This is essentially no bias and conducts for only one half cycle.

• To obtain output for full cycle , it is required to use two transistors and have

each conduct on opposite half-cycles, the combined operation providing a

full cycle of output on opposite half cycles of output signal.

• Since one part of the circuit pushes the signal high during one half cycle and

other part pulls the signal low during the other half cycle, the circuit is

referred to as push-pull circuit.

• Class B operation provides greater efficiency than was possible using single

transistor in class A operation.

Class B push-pull

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.inPower equations

• Input DC power

Pi(dc)=VCC Idc

Here Idc is the average current drawn

Hence Idc can be written as

Hence input power is equal to

Output ac power can be evaluated as,

Efficiency:

)(2

pIIdc

)(2

)( pIVccdcPi

L

Lo R

rmsVacP

)()(

2

100)()(

% xdcPiacPo

%5.78100)(

4

%100)]()/2[(

2/)(%

2

Vcc

pVx

xpIV

RpV

L

CC

LL

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.inPower dissipated by output transistors

• P2Q=Pi(dc)-Po(ac)

• Power handled by each transistor =P2Q/2

Numerical:

For a class B amplifier providing a 20V peak signal to a load of 16 ohms (speaker)

and power supply of VCC=30V, determine the input power, output power, and

circuit efficiency.

Solution:

Hint : use the above derived formulae

• Pi(dc)=23.9W

• Po(ac)=12.5W

• Efficiency=52.3%

For a class B amplifier using supply of VCC=30V and driving a load of 16ohms

determine the maximum input power, output power and transistor dissipation.

Solution:

Hint : use the above derived formulae

Po(ac)=28.125W

Pi(dc)=35.81W

Efficiency=78.54%

Pq=5.7W

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.inEfficiency in another form

Numerical

1. Calculate the efficiency of a class B amplifier for a supply voltage of

VCC=24V with peak output voltages of

a. VL(p)=22V

b. VL(p)=6V

%)(

54.78%

100)(2

2/)(2%

)(2)(

2

)()(

2

Vcc

pVL

x

R

pVV

RLpVL

R

pVVIVdcPi

R

pVacPo

L

LCC

L

LCCdcCC

L

L

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.inClass B amplifier circuits

• To obtain phase inverted signals .

– To use transformers using op-amps

– Using transistors

Phase splitter circuits

Using BJT

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.inUsing op-amp

Transformer coupled push-pull amplifier

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.inComplementary symmetry circuits

Working of the circuit

• Every transistor will conduct for half cycle

• Single input signal is applied to the base of both transistors

• npn transistor will be biased in conduction for positive half cycle of the

input.

• During negative half cycle pnp transistor is biased into conduction when

input goes to negative.

Disadvantages

• One disadvantage is that the need of two separate voltage supplies.

• Cross over distortion in the output signal

• This cross over distortion is referred to as the nonlinearity in the output

signal during cross over from positive to negative or vice-versa. This is due

to the fact that, none of the transistors are on near zero input and thus output

does not follow input.

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.inComplementary symmetry push-pull circuit using Darlington transistors

• This circuit provides higher output current and lower output resistance.

• Here the load resistance is matched by low output resistance of the driving

source.

Quasi complementary push-pull transformer less power amplifier

• In practical circuit it is preferred to use npn for both high-current-output

devices.

• Practical means of obtaining complementary operation while using same,

matched transistors for the output is provided by a quasi complementary

circuit.

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.inCircuit

• Here push-pull operation is achieved by using complementary transistors(Q1

and Q2) before the matched npn output transistors (Q3 and Q4)

• Q1 and Q3 forms a Darlington connection

• Q2 and Q4 forms a feedback connection, which similarly provides low-

impedance to drive the load.

• Resistor R2 can be adjusted to minimize cross over distortion by adjusting

the dc bias condition.

• This is the most popular form of power amplifier used today.

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.inNumerical

For the circuit shown calculate input power, output power and power handled by

each transistor and circuit efficiency.

• Given Vcc=+25V and VEE=-25V

• Input vi=12V

• Load resistance=4 ohms

Solution:

Hint: use the above derived formulae.

• Po(ac)=36.125W

• Pi(dc)=67.75W

• PQ=15.8W


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.inNumerical

For the circuit calculate maximum input power, maximum output power, input

voltage for maximum power operation and power dissipated by the output

transistor at this voltage.

Solution:

Hint: use the above derived formulae

• Pi(dc)=99.47W

• Po(ac)=78.125W


• To achieve maximum power operation the output voltage must be

VL(p)=VCC

• PQ=21.3W

Numerical

For the circuit shown, determine the maximum power dissipated by the output

transistors and the input voltage at which this occurs.

Solution:

• PQ=31.66W

• VL=15.9V

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.inAmplifier distortion

• Any signal varying over less than the full 3600 cycle is considered to have

distortion.

• An ideal amplifier is capable of amplifying a pure sinusoidal signal to

provide a larger version, the resulting waveform being a pure sinusoidal

frequency sinusoidal signal.

• When distortion occurs, output will not be an exact duplicate of input signal

(except for magnitude)

• Distortion can occur because the device characteristic is not linear. In this

case non linear or amplitude distortion occurs.

• Distortion can also occur because the circuit elements and devices respond

to the input signal differently at various frequencies, this being frequency

distortion.

• One technique for describing distorted but period waveforms uses Fourier

analysis, a method that describes any periodic waveform in terms of its

fundamental frequency component and frequency components at integer

multiples- these components are called harmonic components or

harmonics.

Example

A fundamental frequency of 1KHz could result in harmonics of 2KHz,3KHz,4KHz

so on.,

• 1KHz is termed as fundamental frequency

• 2KHz is termed as second harmonic

• 3KHz is termed as third harmonic and so on.,

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.inHarmonic Distortion

• A signal is considered to have harmonic distortion when there are harmonic

frequency components.

• If fundamental frequency has amplitude A1, and nth frequency component

has an amplitude of An.

• Harmonic distortion can be defined as

% nth harmonic distortion=

Numerical

Calculate the harmonic distortion components for an output signal having

fundamental amplitude of 2.5V, second harmonic amplitude of 0.1V, and fourth

harmonic amplitude of 0.05V.

Solution:

%1001

% xA

AnD

%2%1005.2

05.0%100

1

4%

%4%1005.2

1.0%100

1

3%

%10%1005.2

25.0%100

1

2%

xxA

AD

xxA

AD

xxA

AD

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.inTotal harmonic distortion

When an output signal has a number of individual harmonic distortion

components, the signal can be seen to have a total harmonic distortion based on the

individual elements as combined by relation,

Numerical

Calculate the total harmonic distortion for the amplitude components given in

previous example

Solution:

Second harmonic distortion

Ic=ICQ+Io+I1 cos wt + I2 cos wt

IcQ quiescent current

Io additional dc current due to non zero average of the distorted

signal

I1 fundamental component of current

2 second harmonic current due to twice the fundamental frequency

Solving for I1 and I2,

%100.....% 24

23

22 xDDDTHD

%95.10%

%100.....02.004.01.0% 222

THD

xTHD

%100.....% 24

23

22 xDDDTHD

2

minmax4

2minmaxI2Io

1

IcIcI

IcqIcIc

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.inDefinition of second harmonic can be

In voltage terms

Numerical

An output waveform displayed on oscilloscope provides the following

measurements,

i.VCEmin=1V; VCEmax=22V;VCEQ=12V

ii.VCEmin=4V;VCEmax=20V;VCEQ=12V

solution:

%1002

1

2minmax

minmax

xVV

VVVD

CECE

CEQCECE

%100)(

21

2 xVV

VVVD

CEMINCEMAX

CEQCEMINCEMAX

)%(0%100

422

1242021

2..

%38.2%100122

1212221

2..

distotionnoxDi

xDi

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.inPower of signal having distortion

• Power delivered to the load resistor Rc due to the fundamental component ofthe distorted signal is

• Total power due to all the harmonic components of the distorted signal is,

In terms of Total harmonic distortion

Numerical

For harmonic distortion reading of D2=0.1,D3=0.02 and D4=0.01, with I1=4A and

Rc=8 ohms, calculate THD, fundamental power component and total power.

Solution: THD=0.1

P1=64W

P=64.64W

Graphical description of harmonic components of distorted signal

• All the components are obtained by Fourier analysis

• Conclusion: any periodic signal can be represented by adding a fundamental

component and all harmonic components varying in amplitude and at

various phase angles.

21

21 cRI

P

2......)( 2

32

22

1

RcIIIP

12

21

23

22

)1(2

......)1(

PTHDP

RcIDDP

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.inPower transistor heat sinking

Heat is produced in transistors due to the current flowing through them. If you find

that a transistor is becoming too hot to touch it certainly needs a heat sink! The

heat sink helps to dissipate (remove) the heat by transferring it to the surrounding

air.

Heat sink

• Maximum power handled by a particular device and the temperature of the

transistor junction are related since the power dissipated causes an increase

in temperature at the junction of the device.

• Example : a 100 W transistor will provide more power than 10 W transistor.

• Proper heat sinking techniques will allow operation of a device at about one-

half its maximum power rating.

• There are two types of bipolar transistors

Germanium

Junction temperature : 100 – 1100C

Silicon

Junction temperature : 150 – 2000C

• Silicon transistors provide greater maximum temperature

• Average power dissipated may be approximated by

PD=VCEIC

• This power dissipation is allowed only up to a maximum temperature.

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.in• Above maximum temperature, device power dissipation must be reduced

(derated) so that at higher temperature, power handling capacity is reduced.

• The limiting factor in power handling by a particular transistor is the

temperature of the device’s collector junction.

• Power transistors are mounted in large metal cases to provide a large area

from which the heat generated by the device may radiate.

• Even then the device power rating limited.

• Instead if the device is mounted on the heat sink power handling capacity is

increased.

• The derated curve for silicon transistor given by

Mathematical definition.

factoring

)01()0()1(

derat

xTempTemptempPtempP DD

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.inNumerical:

Determine what maximum dissipation will be allowed for an 80W silicon transistor

rated at 25 degree C. if derating s required above this temp by derating factor of

0.5W/degree C at case temp of 125 degree C.

Solution:

Using the above formula

Power derated is 30W

Thermal analogy of power transistor

• θJA total thermal resistance (jn to ambient)

• θJC transistor thermal resistance (jn. To case)

• θCS insulator thermal resistance (case to heat-sink

• θSA heat-sink thermal resistance (heat sink to ambient)

• Usng electrcal analogy

• θJA= θJC+ θCS + θSA

• This analogy can be used n applying kirchoff’s law as

TJ = PD θJA +TA

• The thermal factor θ provides information about how much temp drop( or

rise) for amount of power dissipation .

• Eg: θJC =0.5 deg C/W means that power dissipation of 50W.the dffernce

between junton temp and case temp s gven by

TJ-TC = θJC PD = 0.5x50 =25 deg C.

• Value of thermal resistance from junction to free air (using HS) 40 deg

C/W

• For this thermal resistance only 1W of power dissipation results n junction

temp 40 deg C greater than the ambient.

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.in• A HS can now be seen to provide a low thermal resistance between case and

air much less than 40 deg C/W value of case alone. Using HS having

• θSA 2 deg C/W

And insulating thermal resistance (case to HS)

• θCS0. 8 deg C/W

• Finally for transistor

• θJC 0.5 deg C/W

• θJA= θJC+ θCS + θSA

= 2.0 +0.8 +0.5

= 3.3 deg C/W

With HS thermal resistance between air and the junction is only 3.3 deg C/W

compared 40 deg C/W for transistor operating directly in to free air

Numerical:

A silicon power transistor s operated with a HS θSA = 1.5 deg C/w. the transistor

rated at 150W(25 deg C) has θJC =0.5 deg C/W and the mounting insulation has

θCS =0.6 deg C /W. what s the max power dissipated f the ambient temp s 40 deg

C and TJ max s 200 deg C

• Solution : pd =(TJ-TA)/ θSA + θJC + θCS

= 61.5W

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.inClass C and Class D amplifiers

Class C• The circuit is biased to operate for less than 180 deg of input cycle. The

tuned circuit n the load provide a full cycle of output signal for fundamental

frequency of tuned LC circuit. This type of operation s thus limited to one

fixed frequency as n communication systems.

• Not suitable for power amplification

Class D amplifier

• Class D designed to operate with digital or pulse type signals

• Efficiency of 90% can be achieved.

• Desirable for power amplifiers.

• Necessary to convert any input signal in to pulse type wave before using to

drive a large power load and to convert the signal back to sinusoidal type

signal to recover the original signal .

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.in• Here class – D amplifier we can also consider D stands for Digital since that

s the name of the signal provided to the class D amplifier .

Block diagram of class D

• Most of the power applied to the amplifier is transferred to the load the

efficiency of the circuit s typically very high.

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Chapter.8: Oscillators

• Objectives:

– To understand• The basic operation of an Oscillator• the working of low frequency oscillators

– RC phase shift oscillator– Wien bridge Oscillator

• the working of tuned oscillator– Colpitt’s Oscillator, Hartley Oscillator– Crystal Oscillator

• the working of UJT Oscillator

Basic operation of an Oscillator

• An amplifier with positive feedback results in oscillations if the followingconditions are satisfied:

– The loop gain ( product of the gain of the amplifier and the gain of thefeedback network) is unity

– The total phase shift in the loop is 0• If the output signal is sinusoidal, such a circuit is referred to as sinusoidal

oscillator.

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When the switch at the amplifier input is open, there are no oscillations. Imagine that avoltage Vi is fed to the circuit and the switch is closed. This results in Vo = AV Vi andVo = Vf is fed back to the circuit. If we make Vf = Vi, then even if we remove the inputvoltage to the circuit, the output continues to exist.Vo = AV Vi

Vo = Vf

AV Vi = Vf

If Vf has to be same as Vi, then from the above equation, it is clear that, AV =1.Thus in the above block diagram, by closing the switch and removing the input, we are

able to get the oscillations at the output if AV =1, where AV is called the Loop gain.Positive feedback refers to the fact that the fed back signal is in phase with the inputsignal. This means that the signal experiences 0 phase shift while traveling in the loop.The above condition along with the unity loop gain needs to be satisfied to get the

sustained oscillations. These conditions are referred to as ‘Barkhausen criterion’.Another way of seeing how the feedback circuit provides operation as an oscillator isobtained by noting the denominator in the basic equation

Af = A / (1+A).When A = -1 or magnitude 1 at a phase angle of 180, the denominator becomes 0 andthe gain with feedback Af becomes infinite.Thus, an infinitesimal signal ( noise voltage)can provide a measurable output voltage, and the circuit acts as an oscillator even withoutan input signal.

Phase shift oscillator

• The phase shift oscillator utilizes three RC circuits to provide 180º phase shift thatwhen coupled with the 180º of the op-amp itself provides the necessary feedbackto sustain oscillations.

• The gain must be at least 29 to maintain the oscillations. The frequency ofresonance for the this type is similar to any RC circuit oscillator:

fr = 1/26RC

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FET phase shift oscillator

• The amplifier stage is self biased with a capacitor bypassed source resistor Rs anda drain bias resistor RD . The FET device parameters of interest are gm and rd.

• |A| = gmRL, where RL = (RDrd / RD + rd)• At the operating frequency, we can assume that the input impedance of the

amplifier is infinite.• This is a valid approximation provided, the oscillator operating frequency is low

enough so that FET capacitive impedances can be neglected.• The output impedance of the amplifier stage given by RL should also be small

compared to the impedance seen looking into the feedback network so that noattenuation due to loading occurs.

RC Phase shift Oscillator - BJT version

• If a transistor is used as the active element of the amplifier stage, the output of thefeedback network is loaded appreciably by the relatively low input resistance( hie) of the transistor.

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• An emitter – follower input stage followed by a common emitter amplifier stagecould be used.If a single transistor stage is desired, the use of voltage – shuntfeedback is more suitable. Here, the feedback signal is coupled through thefeedback resistor R’ in series with the amplifier stage input resistance ( Ri).

f = (1/2RC)[1/ 6 + 4(RC / R)]

hfe > 23 + 29 (R/RC) + 4 (RC / R)

Problem:

It is desired to design a phase shift oscillator using an FET having gm = 5000S, rd =40 k , and a feedback circuit value of R = 10 k. Select the value of C for oscillatoroperation at 5 kHz and RD for A > 29 to ensure oscillator action.

Solution:

• f = 1/26RC ; C = 1/26Rf = 1.3nF• |A| = gm RL

Let A = 40; RL = |A| / gm = 8 k

IC phase shift Oscillator

Wien Bridge

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• When the bridge is balanced,

(R2 / R1) = (R3 / R4) + ( C2 / C1)

f = 1/[2 R3C1R4C2]

Wien bridge Oscillator

• R and C are used for frequency adjustment and resistors R1 and R2 form part ofthe feedback path.

• If R3 = R4 =R, C1 = C2 = C, the resulting frequency is f = 1/2RCand R2 / R1 = 2

Tuned Oscillators

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• A variety of circuits can be built using the above diagram, by providing tuning inboth the input and output sections of the circuit.

• Analysis of the above diagram shows that the following types of Oscillators areobtained when the reactance elements are as designated:

Oscillator type X1 X2 X3

Colpitts Oscillator C C L

Hartley Oscillator L L C

Tuned input, Tuned Output LC LC -

Colpitts Oscillator

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• The Colpitts oscillator utilizes a tank circuit (LC) in the feedback loop. Theresonant frequency can be determined by the formula below. Since the inputimpedance affects the Q, an FET is a better choice for the active device.

fr = 1/2LCT

CT = C1C2 / C1 + C2

• An Op amp Colpitts Oscillator circuit can also be used wherein the Op ampprovides the basic amplification needed and the Oscillator frequency is set by anLC feedback network.

Hartley Oscillator

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The Hartley oscillator is similar to the Colpitts. The tank circuit has two inductors andone capacitor. The calculation of the resonant frequency is the same.

f = 1/2LTC

LT = L1 + L2 + 2M

where, M is mutual coupling

Crystal Oscillator

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• A Crystal Oscillator is basically a tuned circuit Oscillator using a piezoelectriccrystal as a resonant circuit.

• The crystal ( usually quartz) has a greater stability in holding constant atwhatever frequency the crystal is originally cut to operate.

• Crystal Oscillators are used whenever great stability is required, such ascommunication transmitters and receivers.

Characteristics of a Quartz Crystal

• A quartz crystal exhibits the property that when mechanical stress is appliedacross one set of its faces, a difference of potential develops across the oppositefaces.

• This property of a Crystal is called ‘ Piezoelectric effect’.• Similarly, a voltage applied across one set of faces of the Crystal causes

mechanical distortion in the Crystal shape.• When alternating voltage is applied to a crystal, mechanical vibrations are set up

– these vibrations having a natural resonant frequency dependent on the Crystal.• Although the Crystal has electromechanical resonance, we can represent the

Crystal action by equivalent electrical circuit as shown.

•The inductor L and the capacitor C represent electrical equivalents of Crystal massand compliance respectively, whereas resistance R is an electrical equivalent of thecrystal structures internal friction. The shunt capacitance CM represents thecapacitance due to mechanical mounting of the crystal. Because the crystal losses,represented by R, are small, the equivalent crystal Q factor is high – typically 20,000.Values of Q up to almost 106 can be achieved by using Crystals. The Crystal can

have two resonant frequencies. One resonant condition occurs when the reactances ofthe series RLC leg are equal. For this condition, the series – resonant impedance isvery low ( equal to R). The other resonant condition occurs at a higher frequencywhen the reactance of the series resonant leg equals the reactance of the capacitor CM.This is parallel resonance or antiresonance condition of the Crystal,At this frequency, the crystal offers very high impedance to the external circuit.

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To use the crystal properly, it must be connected in a circuit so that its lowimpedance in the series resonant operating mode or high impedance in theantiresonant operating mode is selected.

Series resonant circuits

• To excite a crystal for operation in the series – resonant mode, it may beconnected as a series element in a feedback path.

• At the series resonant frequency of the crystal, its impedance is smallest and theamount of feedback is largest.

•

R3 can be replaced with RF choke. Resistors R1, R2 and RE provide a voltage dividerstabililized dc bias circuit. Capacitor CE provides ac bypass of the emitter resistor,RFC coil provides for dc bias while decoupling any ac signal on the power lines fromaffecting the output signal. The voltage feedback from collector to base is a maximumwhen the crystal impedance is minimum ( in series – resonant mode). The resultingcircuit frequency of oscillation is set by the series – resonant frequency of the crystal.The circuit frequency stability is set by the crystal frequency stability which is good.

Parallel resonant circuits

Since the parallel resonant impedance of a crystal is a maximum value, it is connectedin shunt. The circuit is similar to a Colpitts circuit with Crystal connected as inductor

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element. Maximum voltage is developed across the crystal at its parallel resonantfrequency. The voltage is coupled to the emitter by a capacitor voltage dividercapacitors C1 and C2.

Crystal Oscillator using op amp

• An Op – amp can be used in a crystal oscillator. The crystal is connected in theseries resonant path and operates at the crystal series resonant frequency.

Unijunction Oscillator

Unijunction transistor( UJT) can be used in a single stage oscillator circuit to providea pulse signal suitable for digital circuit applications. The UJT can be used inrelaxation oscillator.

The operation of the circuit is as follows: C1 charges through R1 until the voltageacross it reaches the peak point. The emitter current then rises rapidly, discharging C1through the base 1 region and R3. The sudden rise of current through R3 produces thevoltage pulse. When the current falls to IV the UJT switches off and the cycle isrepeated. Oscillator operating frequency fo = 1/{RTCTln[1/(1-)]} where, isintrinsic standoff ratio, typically the value of it is between 0.4 and 0.6.Using = 0.5, fo = 1.5 / RTCT

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Capacitor is charged through resistor RT toward supply voltage VBB. As long as thecapacitor voltage VE is below a stand – off voltage (VP) set by the voltage acrossB1-B2 and the transistor stand – off ratio .• VP = VB1VB2 – VD.When the capacitor voltage exceeds this value, the UJT turns ON, discharging the

capacitor. When the capacitor discharges, a voltage rise is developed across R3.The signal at the emitter of UJT / across the capacitor is saw tooth, at the base 1 are

positive going pulses and at the base 2 are negative going pulses.

Summary:

• Phase shift Oscillator, f = 1/2RC6 , = 1/29• Wien bridge Oscillator f = 1/2RC• Colpitts Oscillator, f = 1/2 LCeq

• Ceq = C1C2/(C1+C2)• Hartley Oscillator, f = 1/2 LeqC

• Leq = L1+L2+2M• UJT Oscillator: f = 1/{RTCTln[1/(1-)]}

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Chapter 1: Diode circuits...

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