Chapter 1 Computer System Overview
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Transcript of Chapter 1 Computer System Overview
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Chapter 1Computer
System OverviewSeventh Edition
By William Stallings
Operating Systems:Internals
and Design
Principles
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How Computer works Bill Buzbee (Google)
Magic-1http://www.homebrewcpu.com/
Andrew HolmeMark 1 FORTH Computerhttp://www.holmea.demon.co.uk/Mk1/Architecture.htm
Aidil Jazmi (UTP)Magic-1 Clone http://www.aidilj.com/homemadecpu/aidil/index3.htm
Aaron Yap (UTP)Mark 1 FORTH Clonehttp://www.aidilj.com/homemadecpu/questra/index.htm
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Basic Elements
Processor
Main Memor
y
I/O Module
s
System Bus
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Processor
Controls the operation of
the computer
Performs the data
processing functions
Referred to as the Central Processing Unit (CPU)
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Main Memory
VolatileContents of the memory is lost when the computer is shut down
Referred to as real memory or primary memory
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I/O Modules
Moves data between the
computer and external
environments such as:
storage (e.g. hard drive)
communications equipment
terminals
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System Bus
Provides for communication among processors, main memory, and I/O modules
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Top-Level View
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How CPU works? http://www.youtube.com/watch?v=cNN_tTXABUA
http://www.youtube.com/watch?v=g_IaVepNDT4
http://www.youtube.com/watch?v=c06WxAvD4Nk
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Microprocessor
Invention that brought about desktop and handheld computing
Processor on a single chipFastest general purpose processorMultiprocessorsEach chip (socket) contains multiple processors (cores)
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Graphical Processing Units (GPU’s)
Provide efficient computation on arrays of data using Single-Instruction Multiple Data (SIMD) techniques
Used for general numerical processing
Physics simulations for gamesComputations on large spreadsheets
G P U
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Digital Signal Processors
(DSPs)Deal with streaming signals such as audio or video
Used to be embedded in devices like modems
Encoding/decoding speech and video (codecs)
Support for encryption and security
D S P
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System on a Chip(SoC)
To satisfy the requirements of handheld devices, the microprocessor is giving way to the SoC
Components such as DSPs, GPUs, codecs and main memory, in addition to the CPUs and caches, are on the same chip
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Instruction Execution
A program consists of a set of instructions stored in memory
Two steps:
• processor reads (fetches) instructions from memory• processor executes each instruction
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Basic Instruction Cycle
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Instruction Fetch and Execute
The processor fetches the instruction from memory
Program counter (PC) holds address of the instruction to be fetched next
PC is incremented after each fetch
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Instruction Register (IR)
Fetched instruction is loaded into Instruction Register (IR)
Processor interprets the instruction and performs required action:
Processor-memory
Processor-I/O Data processing Control
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Characteristics of a Hypothetical Machine
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Example of Program Execution
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Interrupts
Interrupt the normal sequencing of the processor
Provided to improve processor utilization
most I/O devices are slower than the processor processor must pause to wait for device wasteful use of the processor
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Common
Classes
of Interrupts
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Flow of Control
Without
Interrupts
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Interrupts: Short I/O Wait
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Transfer of Control via Interrupts
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Instruction Cycle With Interrupts
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Program
Timing:
Short I/O Wait
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Program
Timing:
Long I/O wait
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Simple
Interrupt
Processing
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Changes for an
Interrupt
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Multiple Interrupts
An interrupt occurs while another interrupt
is being processed
•e.g. receiving data from a communications line and printing results at the same time
Two approaches:•disable interrupts while an interrupt is being processed•use a priority scheme
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Transfer of Control With Multiple Interrupts:
Sequential
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Transfer of Control With
Multiple Interrupts:
Nested
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Example Time Sequence of Multiple Interrupts
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Memory Hierarchy
Major constraints in memory amount speed expense
Memory must be able to keep up with the processor
Cost of memory must be reasonable in relationship to the other components
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Memory Relationships
Faster access time = greater cost per bit
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The Memory Hierarchy
Going down the hierarchy:
decreasing cost per bit
increasing capacity increasing access time decreasing frequency
of access to the memory by the processor
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Performance of a Simple
Two-Level Memory Suppose that the processor has access to two levels of
memory. level 1 contains 1,000 bytes and has an access time of 0.1 μs; level 2 contains 100,000 bytes and has an access time of 1 μs.
Assume if a byte to be accessed is in level 1, then the processor
accesses it directly. If it is in level 2, then the byte is first transferred to level 1 and
then accessed by the processor.
For simplicity, we ignore the time required for the processor to determine whether the byte is in level 1 or level 2.
Figure 1.15 Performance of a Simple Two-Level Memory
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Computing average time to access a byte
hit ratio H , the fraction of all memory accesses that are found in the
faster memory (e.g., the cache)
example,
Suppose 95% of the memory accesses are found in the cache (H = 0.95) . Then the average time to access a byte can be expressed as
(0.95) (0.1 μs) + (0.05) (0.1 μs + 1 μs) = 0.095 + 0.055 =0.15 μs
Figure 1.15 Performance of a Simple Two-Level Memory
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Performance of a Simple
Two-Level Memory
Figure 1.15 Performance of a Simple Two-Level Memory
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Secondary Memory
Also referred to as auxiliary memory• External• Nonvolatile• Used to
store program and data files
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Cache Memory
Invisible to the OS
Interacts with other memory management hardware
Processor must access memory at least once per instruction cycle
Processor execution is limited by memory cycle time
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Cache Principles
Contains a copy of a portion of main memory
Processor first checks cache
If not found, a block of memory is read into cache
Because of locality of reference, it is likely that many of the future memory references will be to other bytes in the block
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Cache and Main
Memory
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Cache/Main-Memory Structure
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Tags and address Main memory consists of up to 2 n addressable words,
with each word having a unique n –bit address.
For mapping purposes, this memory is considered to consist of a number of fixed-length blocks of K words each.
That is, there are M = 2n/K blocks.
Cache consists of C slots (also referred to as lines ) of K words each, and the number of slots is considerably less than the number of main memory blocks (C<<M)
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Mapping Tags and address
Suppose 6 bits address 2 bits tag
Tag 01 01|0000, 01|0001, ……..01|1111
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Cache Read Operation
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Cache Design
Main categories are:
cache size
block size
mapping function
replacement
algorithm
write policy
number of cache
levels
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Cache and Block Size
Cache Size
Small caches have significant impact on
performance
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Mapping Function
Two constraints affect design:
When one block is read in, another may have to be replaced
The more flexible the mapping function, the more complex is the circuitry required to search the cache
∗ Determines which cache location the block will occupy
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Replacement Algorithm
chooses which block to replace when a new block is to be loaded into the cache
Least Recently Used (LRU) Algorithm effective strategy is to replace a block that has
been in the cache the longest with no references to it
hardware mechanisms are needed to identify the least recently used block
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Write Policy
Dictates when the memory write operation takes place
• can occur every time the block is updated• can occur when the block is replaced
• minimizes write operations• leaves main memory in an obsolete state
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I/O Techniques
Three techniques are possible for I/O operations:
Programmed I/O
∗ When the processor encounters an instruction relating to I/O, it executes that instruction by issuing a command to the appropriate I/O module
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Programmed I/O
The I/O module performs the requested action then sets the appropriate bits in the I/O status register
The processor periodically checks the status of the I/O module until it determines the instruction is complete
With programmed I/O the performance level of the entire system is severely degraded
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Interrupt-Driven I/O
Processor issues an I/O command to a module and then goes on to
do some other useful work
The processor executes the data transfer and then resumes its
former processing
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Interrupt-Driven I/ODrawbacks
Transfer rate is limited by the speed with which the processor can test and service a device
The processor is tied up in managing an I/O transfer
a number of instructions must be executed for each I/O transfer
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Direct Memory Access (DMA)
When the processor wishes to read or write data it
issues a command to the DMA module containing:
•whether a read or write is requested • the address of the I/O device involved• the starting location in memory to read/write• the number of words to be read/written
∗ Performed by a separate module on the system bus or incorporated into an I/O module
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Direct Memory Access
Transfers the entire block of data directly to and from memory without going through the processor
processor is involved only at the beginning and end of the transfer
processor executes more slowly during a transfer when processor access to the bus is required
More efficient than interrupt-driven or programmed I/O
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SummaryBasic Elements
processor, main memory, I/O modules, system bus
GPUs, SIMD, DSPs, SoC Instruction execution
processor-memory, processor-I/O, data processing, control
Interrupt/Interrupt Processing Memory Hierarchy Cache/cache principles and designs Multiprocessor/multicore