Chapter 1: Background - nchu.edu.t 1.pdf · Chapter 1: Background Hsung-Pin Chang Department of...

Chapter 1: Background

Hsung-Pin ChangDepartment of Computer ScienceNational Chung Hsing University

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Outlineo 1.1 Introductiono 1.2 System Software and Machine Architectureo 1.3 The Simplified Instructional Computer (SIC)

n SIC Machine Architecturen SIC/XE Machine Architecturen SIC Programming Examples

o 1.4 Traditional (CISC) Machineso 1.5 RISC Machines



1.1 Introductiono Definition: System Softwaren Consist of a variety of programs that support the

operation of a computer

n Make it possible for the user to focus on an application without needing to know the details of how the machine works internally



1.1 Introduction (Cont.)o Example:

n When you took the first programming courseo Text editor - create and modify the programo Compiler- translate programs into machine languageo Loader or linker - load machine language program into memory

and prepared for executiono Debugger - help detect errors in the program

n When you wrote programs in assembler languageo Assembler - translate assembly program into machine languageo Macro processor - translate macros instructions into its definition

n When you control all of these processes o By interacting with the OS



1.2 System Software and Machine Architectureo One characteristic in which most system software

differ from application software is machine dependencyn System programs are intended to support the operation and

use of the computer itselfn Application programs are primary concerned with the

solution of some problemo Example

n Assembler translates mnemonic instructions into machine coden Compilers must generate machine language coden OS is directly concerned with the management of nearly all of the

resources of a computing system



1.2 System Software and Machine Architecture (Cont.)o Important machine structures to the design of

system softwaren Memory structuren Registersn Data formatsn Instruction formatsn Addressing modesn Instruction set



1.2 System Software and Machine Architecture (Cont.)o This textbook discusses system software basing on a

Simplified Instructional Computer (SIC)n SIC is a hypothetical computer that includes the hardware

features most often found on real machineso Study any system software, we should identify:

n Features that are fundamentaln Features that are architecture dependentn Extended features that are relatively machine independentn Major design options for structuring the softwaren Optional features



1.3 The Simplified Instructional Computer (SIC)o SIC is a hypothetical computer that includes

the hardware features most often found on real machines

o Two versions of SICn standard modeln XE version (extra equipment)



1.3 The Simplified Instructional Computer (SIC)o SIC comes in two versionsn The standard modeln An XE version

o “extra equipments”, “extra expensive”

o These two versions has been designed to be upward compatiblen An object program for the standard SIC will also

execute properly on a SIC/XE system



1.3.1 SIC Machine Architectureo Memoryn 1 byte = 8-bitn 1 word=3 consecutive bytes

o Addressed by the location of their lowest numbered byte

n Total 32,768 (215) bytesn Memory is byte addressable



1.3.1 SIC Machine Architecture (Cont.)o Registersn Five registersn Each register is 24 bits in length

Status word9SW

Program counter8PC

Linkage register2L

Index register1X

Accumulator0A

Special useNumberMnemonic



1.3.1 SIC Machine Architecture (Cont.)o Status Word register contents

Bit position Field name Use0 MODE 0=user mode, 1=supervisor mode1 IDLE 0=running, 1=idle

2~5 ID Process identifier6~7 CC Condition code

8~11 MASK Interrupt mask12~15 Unused16~23 ICODE Interruption code



1.3.1 SIC Machine Architecture (Cont.)o Data Formats

n Integers: stored as 24-bit binary numbers;o 2’s complement representation is used for negative values

n Characters: stored as 8-bit ASCII codesn No floating-point hardware

o Instruction Formats - standard version of SIC

addressxopcode1518

The flag bit x is used to indicate indexed-addressing mode



1.3.1 SIC Machine Architecture (Cont.)o Addressing Modesn There are two addressing modes available

o Indicated by the setting of x bit in the instruction

TA=address+(X)x=1Indexed

TA=addressx=0Direct

Target address calculationIndicationMode

( ): the contents of a register or a memory location



1.3.1 SIC Machine Architecture (Cont.)o Instruction Set

n load and store instructions: LDA, LDX, STA, STX, etc.n integer arithmetic operations: ADD, SUB, MUL, DIV, etc.

o All arithmetic operations involve a register A and a word in memory, with the result being left in the register

n comparison: COMPo COMP compares the value in register A with a word in memoryo This instruction sets a condition code CC in SW (Status Word) to

indicate the result (<,=,or >)n conditional jump instructions: JLT, JEQ, JGT

o These instructions test the setting of CC and jump accordinglyn subroutine linkage: JSUB, RSUB

o JSUB jumps to the subroutine, placing the return address in register Lo RSUB returns by jumping to the address contained in register L

n Appendix A gives a complete list of all SIC instructions



1.3.1 SIC Machine Architecture (Cont.)o Input and Output

n Input and output are performed by transferring 1 byte at a time to/from the rightmost 8 bits of register A

n Three I/O instructions:o Test Device (TD)

n Tests whether the addressed device is ready to send or receive abyte of data

n Condition code is set to indicate the result ( <: ready, =: not ready)o Read Data (RD)o Write Data (WD)



1.3.2 SIC/XE Machine Architectureo Memory

n Almost the same as that previously described for SIC

n However, 1 MB (220 bytes) maximum memory available



1.3.2 SIC/XE Machine Architecture (Cont.)o Registers

n More registers are provided by SIC/XE

Floating-point accumulator (48 bits)

6FGeneral working register5TGeneral working register4S

Base register3BSpecial useNumberMnemonic



1.3.2 SIC/XE Machine Architecture (Cont.)o Data Formats

n The same data format as the standard versionn However, provide an addition 48-bit floating-point data

typeo fraction: 0~1o exponent: 0~2047o sign: 0=positive, 1=negative

fractionexponents36111

Value = (-1)S 0.f * 2(exp-1024)



1.3.2 SIC/XE Machine Architecture (Cont.)o Instruction Formatsn Larger memory means an address cannot fit into a

15-bit field n Extend addressing capacity

o Use some form of relative addressing -> instruction format 3

o Extend the address field to 20 bits -> instruction format 4

n Additional instructions do not reference memoryo Instruction format 1 & 2



1.3.2 SIC/XE Machine Architecture (Cont.)o Instruction Formats (Cont.)

op8

r2r1op448

Format 1 (1 byte)

Format 2 (2 bytes)

x1

b1

p1

n1

i1

dispeop1216

Format 3 (3 bytes)e = 0

x1

b1

p1

n1

i1

addresseop2016

Format 4 (4 bytes)e = 1



1.3.2 SIC/XE Machine Architecture (Cont.)o Addressing Modes

n Base relative addressing - format 3 onlyo n = 1, i = 1, b=1, p=0

n Program-counter relative addressing - format 3 only o n = 1, i = 1, b=0, p=1

n Direct addressing – format 3 and 4o n = 1, i = 1, b=0, p=0

n Indexed addressing – format 3 and 4o n = 1, i = 1, x = 1 or n = 0, i = 0, x = 1

n Immediate addressing – format 3 and 4o n = 0, i = 1, x = 0 // cannot combine with indexed

n Indirect addressing – format 3 and 4o n = 1, i = 0, x = 0 // cannot combine with indexed

n Simple addressing – format 3 and 4o n = 0, i = 0 or n = 1, i = 1



1.3.2 SIC/XE Machine Architecture (Cont.)

o Base Relative Addressingx

1b

0p

1n

1i

dispopcodee

n=1, i=1, b=1, p=0, TA=(B)+disp (0≤disp ≤4095)

o Program-Counter Relative Addressing

x0b

1p

1n

1i

dispopcodee

n=1, i=1, b=0, p=1, TA=(PC)+disp (-2048≤disp ≤2047)




x0b

0p

1n

1i

disp/addressopcodee

o Direct Addressingn The target address is taken directly from the disp or address

field

Format 3 (e=0): n=1, i=1, b=0, p=0, TA=disp (0≤disp ≤4095)Format 4 (e=1): n=1, i=1, b=0, p=0, TA=address




n=1, i=1, x=1Ex. Direct Indexed Addressing

Format 3, TA=(X)+dispFormat 4, TA=(X)+address

o Indexed Addressingn The term (X) is added into the target address calculation

0x b p

1n

1i

disp/addressopcodee




o Immediate Addressing – no memory access

0x b p

0n

1i

disp/addressopcodee

n=0, i=1, x=0, operand=disp //format 3n=0, i=1, x=0, operand=address //format 4

o Indirect Addressing

0x b p

1n

0i

disp/addressopcodee

n=1, i=0, x=0, TA=(disp), operand = (TA) = ((disp))n=1, i=0, x=0, TA=(address), operand = (TA) = ((address))




o Simple Addressing Modex b p

1n

1i

disp/addressopcodee

Format 3: i=1, n=1, TA=disp, operand = (disp)Format 4: i=1, n=1, TA=address, operand = (address)

x b p

0

n

0

i

dispopcode

e

i=0, n=0, TA=b/p/e/disp (SIC standard)



1.3.2 SIC/XE Machine Architecture (Cont.)o Specify how to calculate the target address value

n Base relative addressingn Program-counter relative addressingn Direct addressingn Indexed addressing

o Combined with above any addressing modeo But cannot combined with immediate or indirect addressing modes

o Specify how the target address is usedn Immediate addressingn Indirect addressingn Simple addressing



1.3.2 SIC/XE Machine Architecture (Cont.)o SIC/XE

n n=1, i=1n Except the immediate (i=1) and indirect (n=1) addressing

o SICn n=0, i=0n Ignore the b, p, e fields and consider to be part of address

fieldo Format 4

n b = 0, p = 0n Not allow base relative and PC relative addressing



LDA instructions – student exercise



1.3.2 SIC/XE Machine Architecture (Cont.)o Instruction Set – add the following new instructions

n load and store new registerso LDB, STB, etc.

n floating-point arithmetico ADDF, SUBF, MULF, DIVF

n register moveo RMO

n register-to-register arithmetico ADDR, SUBR, MULR, DIVR

n supervisor call instructiono SVCo Generates an interrupt for communicating with OS, often called

software interruptn Appendix A gives a complete list of all SIC instructions



1.3.2 SIC/XE Machine Architecture (Cont.)o Input/Outputn There are I/O channels that can be used to

perform input and output while the CPU is executing other instructionso Allow overlap of computing and I/O

n SIO, TIO, HIO: start, test, halt the operation of I/O device



1.3.3 SIC Programming Exampleso Constructions of assembly language programn Instruction: Label mnemonic operand

o Operandn Direct addressing A

o E.g. LDA ZEROn Immediate addressing #A

o E.g. LDA #0n Indexed addressing A, X

o E.g. STCH BUFFER, Xn Indirect addressing @A

o E.g J @RETADR



1.3.3 SIC Programming Examples (Cont.)o Constructions of assembly language program (Cont.)

n DataLabel BYTE valueLabel WORD valueLabel RESB valueLabel RESW value

o E.g. EOF BYTE C’EOF’o E.g. FIVE WORD 5

name of operand

integer,character



1.3.3 SIC Programming Examples (Cont.)o Data movement [fig 1.2]

n [fig 1.2 (a)] SIC assembler language programmingn No memory-to-memory move instructions

o All data movement must be done using registers

n Move 3-byte word: LDA, STA, LDL, STL, LDX, STXo By means of register A, L, or X

n Move 1-byte: LDCH, STCH n Define storage for data items

o WORD, RESW // WORD: initialized, RESW: uninitializedo BYTE, RESB // BYTE: initialized, RESB: uninitialized



1.3.3 SIC Programming Examples (Cont.)o Data movement [fig 1.2] (Cont.)n [fig 1.2 (b)] SIC/XE versions of fig. 1.2 (a)

n Make use of the immediate addressing of SIC/XEo E.g. LDA #5



1.3.3 SIC Programming Examples (Cont.)o Arithmetic [fig 1.3]n Store the value (ALPHA+INCR-1) in BETAn Store the value (GAMMA+INCR-1) in DELTA

n [fig 1.3 (a)] SIC assembler language programmingo Arithmetic operations are performed using register A,

with the result being left in register A



1.3.3 SIC Programming Examples (Cont.)o Arithmetic [fig 1.3] (Cont.)n [fig 1.3 (b)] SIC/XE assembler language

programmingo register-to-register instruction is used

n E.g. ADDR S,A

o immediate addressing is used too



1.3.3 SIC Programming Examples (Cont.)o Looping and indexing [fig 1.4]

n Copy one 11-byte character string to anothern Indexed addressing is used

o E.g. LDCH STR1, Xn [fig 1.4 (a)] SIC assembler language programming

o TIX instruction is used:n (X)=(X)+1n compare with operandn set CC to indicate the result

n [fig 1.4 (b)] SIC/XE assembler language programmingo TIXR instruction is used instead of TIX:

n (X)=(X)+1n compare with specified register instead from memoryn set CC

o immediate addressing is used too



1.3.3 SIC Programming Examples (Cont.)o Looping and indexing [fig 1.5] n ALPHA[1..100]+BETA[1..100] ->

GAMMA[1..100]n Each element is 1 word (3 bytes)n [fig 1.5 (a)] SIC assembler language

programmingo The value of index register must be incremented by 3

for each iteration of this loop



1.3.3 SIC Programming Examples (Cont.)o Looping and indexing [fig 1.5] (Cont.)n [fig 1.5 (b)] SIC/XE assembler language

programmingn Fig. 1.5 (a) is cumbersome

o Register A must be used for adding array elementsand also for incrementing the index value

n immediate addressing is used in SIC/XEn register-to-register instructions are also used

o E.g. COMPR X,To E.g. ADDR S, X



1.3.3 SIC Programming Examples (Cont.)o I/O on SIC and SIC/XE [fig 1.6] n Read 1-byte data from device F1 and copies it to

device 05n TD

o Test the status of device and set CCn < : device is readyn = : device is not ready

n RD (read data)n WD (write data)



1.3.3 SIC Programming Examples (Cont.)o Subroutine call and record input [fig 1.7]

n Read 100-byte data from input device into memory n Subroutine is used

o JSUB (jump to subroutine)o RSUB (return control to the instruction that follows the JSUB

n [fig 1.7 (a)] SIC assembler language programmingo Main program calls subroutine READ by using JSUB

n [fig 1.7 (b)] SIC/XE assembler language programmingo immediate addressing is used o TIXR instruction is used



1.4 Traditional (CISC) Machineso Complex Instruction Set Computers (CISC)n Relatively large and complicated instruction setn Several different instruction formats and lengthsn Many different addressing modesn e.g. VAX or PDP-11 from DECn e.g. Intel x86 family

o Reduced Instruction Set Computer (RISC)



1.4 Traditional (CISC) Machines (Cont.)o 1.4.1 VAX architecture from DEC

o 1.4.2 Pentium Pro architecture



1.4.2 Pentium Pro Architectureo Memory

n physical level: address are byte addresseso word (2 bytes), doubleword (or dword) (4 bytes)o Some operations are more efficient when operands are aligned

n logical level: programmers usually view the x86 memory as a collection of segments.o An address consists of segments and offsetso In some cases, a segment can also be divided into pageso The segment/offset address specified by the programmer is

translated into a physical address by the x86 MMU (Memory Management Unit)



1.4.2 Pentium Pro Architecture (Cont.)o Registers

n Eight 32-bit general-purpose registers:o EAX, EBX, ECX, EDX: data manipulationo ESI, EDI, EBP, ESP: address

n Special-purpose registers:o Two 32-bit registers:

n EIP: pointer to the next instructionn FLAGS: status word

o Six 16-bit segment registers:n CS: code segment registern SS: stack segment registern DS, ES, FS, and GS: data segments

n Floating-point unit (FPU)n All above registers are available to application programmers

o Other registers used only by system programs such as OS.



Processor model for 8086 microprocessor



Processor Model for Pentium Pro



1.4.2 Pentium Pro Architecture (Cont.)o Data Formats

n Integers: o 8-, 16-, 32-bit binary numberso Negative values: 2’s complemento FPU can also handle 64-bit signed integerso The least significant part of a numeric value is stored at the

lowest-numbered address (little-endian)o Can also be stored in binary coded decimal (BCD)

n Unpacked BCD format: o Each byte represents one decimal digit

n Packed BCD format:o Each byte represents two decimal digits, with each digit

encoded using 4 bits of the byte



1.4.2 Pentium Pro Architecture (Cont.)o Data Formats (Cont.)n Floating-point data formats:

o single-precision format: 32 bitsn 24 significant bits + 7-bit exponent + sign bit

o double-precision format: 64 bitsn 53 significant bits + 10-bit exponent + sign bit

o extended-precision format: 80 bitsn 64 significant bits + 15-bit exponent + sign bit

n Characters: o 8-bit ASCII codes



1.4.2 Pentium Pro Architecture (Cont.)o Instruction Formatsn prefix (optional) containing flags that modify the

operation of instructiono specify repetition count, segment register, etc.

n opcode (1 or 2 bytes)n operands and addressing modesn Large number of different potential instruction

formats, varying in length from 1 to 10 bytes or more



1.4.2 Pentium Pro Architecture (Cont.)o Addressing Modes

n An operand value may be specified as part of the instruction itself (immediate mode), or it may be in a register (register mode)

n TA=(base register)+(index register)*(scale factor)+displacemento base register: any general-purpose registerso index register: any general-purpose registers except ESPo scale factor: 1, 2, 4, 8o displacement: 8-, 16-, 32- bit value

n Eight different addressing modesn The address of an operand in memory may also be

specified as an absolute location (direct mode), or as a location relative to the EIP register (relative mode)



1.4.2 Pentium Pro Architecture (Cont.)o Instruction Set

n More than 400 different machine instructionso An instruction may have 0, 1, 2, 3 operandso R-to-R instructions, R-to-M instructions, M-to-M instructionso In some cases, operands may also be specified in the instruction

as immediate valueso Data movement and integer arithmetic instructions, string

manipulation instructionso Logical and bit manipulations, support control of the processor

and memory-management systemsn Special-purpose instructions for high-level programming

languageo Entering and leaving procedures,o Checking subscript values against the bounds of an array



1.4.2 Pentium Pro Architecture (Cont.)o Input and Outputn Input is performed by instructions that transfer

one byte, word, or doubleword from an I/O portinto register EAX

n Output instructions transfer one byte, word, or doubleword from EAX to an I/O port

n Repetition prefixes allow these instructions to transfer an entire string in a single operation



1.5 RISC Machineso RISC (Reduced Instruction Set Computers)n Simplify the design of processors

n Faster and less expensive processor development

n Greater reliability

n Faster instruction execution times



1.5 RISC Machines (Cont.)o Features

n Standard, fixed instruction formatn Single-cycle execution of most instructionsn Memory access is done by load and store instructions onlyn All instructions are register-to-register operations

o Except load and store n A small number of machine instructions and instruction

format, n A large number of general-purpose registersn A small number of addressing modes



1.5 RISC Machines (Cont.)o Examplesn Sun SPARC familyn IBM PowerPC seriesn ARM corp. ARM family



1.5.1 UltraSPARC Architectureo Announced by Sun Microsystems, in 1995n Member of the SPARC family

o SPARC stands for Scalable Processor ARChitecture



1.5.1 UltraSPARC Architecture -Memoryo All addresses used are byte addressesn Halfword: two consecutive bytesn Word: four bytesn Doubleword: eight bytes

o Alignmentn Halfword are stored in memory beginning at byte

address that are multiples of 2n Words begin at addresses that are multiples of 4n Doublewords at addresses that are multiples of 8



1.5.1 UltraSPARC Architecture –Memory (Cont.)o Virtual address spacen UltraSPARC programs can be written using 264

bytesn The address space is divided into pages

o Multiple page sizes are supported

n Virtual address is automatically translated into physical address by Memory Management Unit (MMU)



1.5.1 UltraSPARC Architecture –Registerso A large register file contains more than 100 general-

purpose registerso Any procedure can access only 32 registers (r0~r31)

n First 8 registers (r0~r8) are globalo Can be access by all procedures on the system (r0 is zero)

n Other 24 registers can be visualized as a window through which part of the register file can be seen

o Program counter (PC)n The address of the next instruction to be executed

o Condition code registerso Other control registers



1.5.1 UltraSPARC Architecture – Data Formatso Integers are 8-, 16-, 32-, 64-bit binary numbers

n 2’s complement is used for negative valueso Support both big-endian and little-endian byte

orderingso Three different floating-point data formats

n Single-precision, 32 bits long (23 + 8 + 1)n Double-precision, 64 bits long (52 + 11 + 1)n Quad-precision, 78 bits long (63 + 16 + 1)



1.5.1 UltraSPARC Architecture –Instruction Formatso All instructions are 32 bits longo Three Instruction Formatsn The first 2 bits identify which format is being

usedn Format 1: call instructionn Format 2: branch instructionsn Format 3: remaining instructions



1.5.1 UltraSPARC Architecture –Access Modeso Operand value may be specified inn Immediate moden Register direct mode

o Operand is in a registern Memory addressing

o PC-relative: n TA = (PC) + displacement {30 bits, signed}

o Register indirect with displacement: n TA = (register) + displacement {13 bits, signed}

o Register indirect indexed: n TA = (register – 1) + (register – 2)



1.5.1 UltraSPARC Architecture –Instruction Seto Fewer than 100 instructions

n Reflect its RISC philosophyo Only load-store instructions can access memory

n All other instructions are register-to-register operationso Pipelined execution

n While one instruction is being executed, the next one is fetched from memory and decoded

o Special-purpose instructionsn High-bandwidth block load and store operationsn Special “atomic” instructions to support multi-processor

system



1.5.1 UltraSPARC Architecture –Input and Outputo A range of memory locations is logically

replaced by device registerso Each I/O device has a unique address, or set

of addresseso Input and output can be performed with the

regular instruction setn No special I/O instructions are needed



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