Chap. 8 Sequencing and ControlChap. 8 Sequencing and Control

A Simple Computer ArchitectureA Simple Computer Architecture Single-Cycle Hardwired Control Single-Cycle Hardwired Control Multiple-Cycle Multiprogrammed ControlMultiple-Cycle Multiprogrammed Control

InstructionsInstructions InstructionInstruction

– A collection of bits that instructs the computer to A collection of bits that instructs the computer to perform a specific operationperform a specific operation

» Opcode: operation codeOpcode: operation code If the opcode consists of m bits, …If the opcode consists of m bits, …

» Instruction setInstruction set

ProgramProgram– A list of instructionsA list of instructions

Instruction formatsInstruction formats

R1 R2 – R3

R2 R7 + 3

Examples)

If R6 = 0,PC PC-20

Address offset

SequencingSequencing

Two address in a microinstructionTwo address in a microinstruction– 분기가능한 두 가지 분기가능한 두 가지 addressaddress 를 준비를 준비

CAR: Counter with parallel loadCAR: Counter with parallel load– 분기할 주소 계산분기할 주소 계산– Program Counter (PC)Program Counter (PC)

Instruction formatsInstruction formats

If R6!=0,Then, …

InstructionInstruction

InstructionOpcode

Micro-operation

Decoder

Storage ResourcesStorage Resources

Single-cycle Hardwired ControlSingle-cycle Hardwired Control

• Single-cycle computer; obtain and execute an instruction from the instruction memory all in a single clock cycle

Instruction DecoderInstruction Decoder

Cf) In micro-programmed control,Control memory

• PL=1 : jump or branch• PL=0 : PC++• PL=1, JB=1 : unconditional jump• PL=1, JB=0 : conditional branch

Condition for branch (BC) 000 : C 001 : N 010 : V 011 : Z 100 : /C 101 : /N 110 : /V 111 : /Z

Instruction DecoderInstruction DecoderBoolean eq. for decoding ?

Sample Instruction & ProgramSample Instruction & Program

16bit 로 확장

Limitations of Single-cycle ComputerLimitations of Single-cycle Computer

Require multiple clock cycles for performing complex Require multiple clock cycles for performing complex operationsoperations– Multiplication: add-and-shiftMultiplication: add-and-shift

Two read accesses of memory for executing an Two read accesses of memory for executing an instructioninstruction– Two types of memory: for instruction and dataTwo types of memory: for instruction and data– Load a data word from memory into a registerLoad a data word from memory into a register

» Two clock cycles are required.Two clock cycles are required.

Lower limit on the clock period based on a long worst Lower limit on the clock period based on a long worst case delay pathcase delay path– Pipelining controlPipelining control

Limitations of Single-cycle ComputerLimitations of Single-cycle Computer

A solution to the above limitationsA solution to the above limitations

–Multiple-cycle Micro-programmed ControlMultiple-cycle Micro-programmed Control

Multiple-Cycle Microprogrammed ControlMultiple-Cycle Microprogrammed Control

Multiple-Cycle Microprogrammed ControlMultiple-Cycle Microprogrammed Control

Multiple-Cycle Micro-programmed ControlMultiple-Cycle Micro-programmed Control

Microprogram DesignMicroprogram Design

Microprogram DesignMicroprogram Design

Microprogram DesignMicroprogram Design

Microprogram DesignMicroprogram Design

Hardwired AlternativeHardwired Alternative

Hardwired AlternativeHardwired Alternative

Pipeline ControlPipeline Control

Pipeline ControlPipeline Control