Chap. 7.4: Virtual Memory

CS61C L35 VM I (2) Garcia © UCB

Review: Caches

•Cache design choices:• size of cache: speed v. capacity• direct-mapped v. associative• for N-way set assoc: choice of N• block replacement policy• 2nd level cache?• Write through v. write back?

•Use performance model to pick between choices, depending on programs, technology, budget, ...


Another View of the Memory Hierarchy

Regs

L2 Cache

Memory

Disk

Tape

Instr. , Operands

Blocks

Pages

Files

Upper Level

Lower Level

Faster

Larger

CacheBlocks

Thus far{{Next:

VirtualMemory

Recall: illusion of memory Programmer’s view about memory

Unlimited amount of fast memory How to create the above illusion?

無限大的快速記憶體

Scene: library Book shelf

desk

books

Virtual memory 虛擬記憶體 Create an illusion of unlimited memory Motivation

A collection of programs running at once on a machine

Total memory required by all programs > the amount of main memory available

Allow a single user program to exceed the size of primary memory

Software solution: programmers divided programs into pieces, called overlays

多個程式同時執行，大於主記憶體

單一程式大於主記憶體


Simple Example: Base and Bound Reg

0

OS

User A

User B

User C

$base

$base+$bound

•Want discontinuous mapping•Process size >> mem•Addition not enough!=> What to do?

Enough space for User D,but discontinuous (“fragmentation problem”)

Virtual memory system Main memory as a cache for the

secondary storage (disk)

Memory

CPU

Memory

Size Cost ($/bit)Speed

Smallest

Biggest

Highest

Lowest

Fastest

Slowest Memory

cache

Disk

Cache for disk

How to mapto disk?

More about Virtual Memory

Called “Virtual Memory”Also allows OS to share memory, protect programs from each other

Today, more important for protection vs. just another level of memory hierarchy

Each process thinks it has all the memory to itself

Historically, it predates caches


Mapping Virtual Memory to Physical Memory

0

Physical Memory

Virtual Memory

Code

Static

Heap

Stack

64 MB

•Divide into equal sizedchunks (about 4 KB - 8 KB)

0

•Any chunk of Virtual Memory assigned to any chuck of Physical Memory (“page”)


Paging Organization (assume 1 KB pages)

AddrTransMAP

Page is unit of mapping

page 0 1K1K

1K

01024

31744

Virtual Memory

VirtualAddress

page 1

page 31

1K2048 page 2

...... ...

page 001024

7168

PhysicalAddress

PhysicalMemory

1K1K

1K

page 1

page 7...... ...

VM address translation (1)

3 2 1 011 10 9 815 14 13 1231 30 29 28 27

Page offsetVirtual page number

Virtual address

3 2 1 011 10 9 815 14 13 1229 28 27

Page offsetPhysical page number

Physical address

Translation Page size=212

Virtualaddress

Physicaladdress

Address space=232

=4GB

Address space=230

=1GB

How to translate virtual addresses ?

Ans: Direct mapped, set-associative, full-associative?

VM address translation (2)

Page offsetVirtual page number

Virtual address

Page offsetPhysical page number

Physical address

Physical page numberValid

If 0 then page is notpresent in memory

Page table register

Page table

20 12

18

31 30 29 28 27 15 14 13 12 11 10 9 8 3 2 1 0

29 28 27 15 14 13 12 11 10 9 8 3 2 1 0

Each programhas its ownpage table

220

Address translation: Full-associative


Paging/Virtual Memory Multiple Processes

User B: Virtual Memory

Code

Static

Heap

Stack

0Code

Static

Heap

Stack

A PageTable

B PageTable

User A: Virtual Memory

00

Physical Memory

64 MB

Page fault (~cache miss)

Physical memory

Disk storage

Valid

1

1

1

1

0

1

1

0

1

1

0

1

Page table

Virtual pagenumber

Physical page ordisk address

VirtualPage number

Key issues in VM Page fault penalty takes millions of cycles Pages should be large enough to amortize the

high access time 32-64KB

Reduce the page fault rate: full-associative placement

Use clever algorithm to replace pages while page faults occur LRU (least recently used) ?

Use write-back instead of write-through

Make the address translation faster

Motivation: page tables are stored in main memory

Load/storevirtual address

Page table

Physical address

In memory

Main memory

data

2 memoryaccesses !!!

Use a cacheto store page table

Translation-lookaside buffer (TLB)

Valid

1

1

1

1

0

1

1

0

1

1

0

1

Page table

Physical pageaddressValid

TLB

1

1

1

1

0

1

TagVirtual page

number

Physical pageor disk address

Physical memory

Disk storage

TLB

TLBmiss


VM, TLB, and cache

•TLBs usually small, typically 128 - 256 entries

• Like any other cache, the TLB can be direct mapped, set associative, or fully associative

Processor

VA

Cache

miss

hit

data

TLBLookup

PAhit

miss

MainMemory

Trans-lation

On TLB miss, get page table entry from main memory

VM, TLB, and caches

Valid Tag Data

Page offset

Page offset

Virtual page number

Virtual address

Physical page numberValid

1220

20

16 14

Cache index

32

Cache

DataCache hit

2

Byteoffset

Dirty Tag

TLB hit

Physical page number

Physical address tag

TLB

Physical address

31 30 29 15 14 13 12 11 10 9 8 3 2 1 0 31 30 … 12 11 … 1 0

Virtual address

TLB

cache


Comparing the 2 levels of hierarchy

Cache Version Virtual Memory vers.

Block or Line Page Miss Page Fault Block Size: 32-64B Page Size: 4K-8KB Placement: Fully Associative

Direct Mapped, N-way Set Associative

Replacement: Least Recently UsedLRU or Random (LRU)

Write Thru or Back Write Back

CS61C L36 VM II (23) Garcia © UCB

Review: 4 Qs for any Memory Hierarchy° Q1: Where can a block be placed?

• One place (direct mapped)• A few places (set associative)• Any place (fully associative)

° Q2: How is a block found?• Indexing (as in a direct-mapped cache)• Limited search (as in a set-associative cache)• Full search (as in a fully associative cache)• Separate lookup table (as in a page table)

° Q3: Which block is replaced on a miss? • Least recently used (LRU)• Random

° Q4: How are writes handled?• Write through (Level never inconsistent w/lower)• Write back (Could be “dirty”, must have dirty bit)


°Block 12 placed in 8 block cache:• Fully associative• Direct mapped• 2-way set associative

- Set Associative Mapping = Block # Mod # of Sets

0 1 2 3 4 5 6 7Blockno.

Fully associative:block 12 can go anywhere

0 1 2 3 4 5 6 7Blockno.

Direct mapped:block 12 can go only into block 4 (12 mod 8)

0 1 2 3 4 5 6 7Blockno.

Set associative:block 12 can go anywhere in set 0 (12 mod 4)

Set0

Set1

Set2

Set3

Q1: Where block placed in upper level?


°Direct indexing (using index and block offset), tag compares, or combination

° Increasing associativity shrinks index, expands tag

Blockoffset

Block AddressTag Index

Q2: How is a block found in upper level?

Set Select

Data Select


°Easy for Direct Mapped°Set Associative or Fully Associative:

• Random• LRU (Least Recently Used)

Miss RatesAssociativity:2-way 4-way 8-waySize LRU Ran LRU Ran LRU Ran16 KB 5.2% 5.7% 4.7% 5.3% 4.4% 5.0%64 KB 1.9% 2.0% 1.5% 1.7% 1.4% 1.5%256 KB 1.15%1.17% 1.13% 1.13% 1.12% 1.12%

Q3: Which block replaced on a miss?


Q4: What to do on a write hit?°Write-through• update the word in cache block and corresponding word in memory

°Write-back• update word in cache block• allow memory word to be “stale”

=> add ‘dirty’ bit to each line indicating that memory be updated when block is replaced

=> OS flushes cache before I/O !!!

°Performance trade-offs?• WT: read misses cannot result in writes

• WB: no writes of repeated writes

Short conclusion of VM Virtual memory

Cache between memory and disk VM allows

A program to expand its address space Sharing of main memory among multiple

processes To reduce page fault

Large pages – use spatial locality Full associative mapping OS use clever replacement method (LRU,…)

Chap. 7.4: Virtual Memory

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Transcript of Chap. 7.4: Virtual Memory