Channel Coding - ceng.tu.edu.iq

Forth Class Electrical Dept.

Communication II Nada Nasih

1

Channel Coding

The purpose of channel coding is:-

To protect information from channel noise, distortion and

jamming which is the subject of error detection and correction

codes.

To protect information from 3rd party "enemy" which is the subject

of encryption scrambling.

Error Detecting and Correcting Codes:

The basic idea behind these codes is to add extra bits (digits) to

information such that the receiver can use it to detect and correct errors

with limited capabilities, these extra bits are called parity or check or

correction bits.

If for k digits, r parity digits are added then the transmitted digits n = k+r.

We will have r redundant digits and the code is called (n,k) code.

k = No. of information bits.

r = No. of check bits.

n = No. of transmitted bits.

With code efficiency or rate of (n

k). In general, the ability of detection or

correction depends on :

1. The technique used.

2. n,k parameters.

Simple Error Detecting Codes:

The simplest error detection schemes are the well-known even & odd

parity generators. For even parity generators, an extra bit is added for each k

information bits such that the number of ones is even.

At the receiver, an error is detected if the number of ones is odd.

Either no error occurs or even number of errors occur.

Hence, Prob. (detecting errors)=Prob. (odd number of errors).

Prob. (Un detecting errors)=Prob. (even number of errors).



2

For Odd parity generators, the same idea can be applied when

number of ones is adjusted to be odd.

The code efficiency of even and odd parity generators is 1k

k

To implement these parity generators, simple Ex-OR gates are used

at the transmitter and receiver as shown :

At transmitter

information bits even parity

1010111 1

0110101 0

1011111 0

1101000 1

At receiver

Hence, we can conclude the error detection is not ideal. It doesn't

detect errors 100%.

Note that the advantage of error detection is clear when (it is with

Automatic Repeat Query ARQ systems).

In these systems, two channels are used, the usual forward channel

with error detection and backward channel is used to inform

transmitter to retransmit the same data so that in the next

transmission, data is received correctly.

k bits

Even parity bits

K+1 bits



3

Error Correcting Codes :

In order to make the receiver have the ability to detect and correct

errors, not only a single checking (parity) bit is used but instead r bits are

used giving what is called (n,k) code.

Basic Definitions: 1. Systematic and non-systematic codes:-

If information bits a1, a2, …… ak are unchanged in their values and

positions at the transmitted codeword then this code is called

systematic code.

Input data [D]=[ a1, a2, …… ak]

Output systematic (n,k) codeword is

[C]=[ a1, a2, …… ak c1, c2, ….cr]

However, if data bits separated (spread) or changed at the output

codeword. This code is said to be non-systematic.

The output of non-systematic (7,4) code is

[C]=[ c2 a1 c3 a2 c1 a4 a3 ]

2. Hamming Distance:-

the ability of error detection and correction depends on this

parameter, the hamming distance between any two codes ci and cj is

denoted by dij which is the number of bits that differ between

theses codes for a binary (n,k) code with 2k possible codeword,

then minimum hamming distance (H.D) is the minimum dij.

Also note that n dij 0

Ex: find hamming distance for the three code words

[C1]=[1011100] , [C2]=[1011001] , [C3]=[1011000]

Sol:-

d12 = 2 d13 = 1 d23 = 1



4

3. Hamming weight:-

This is the number of ones in the non-zero codeword ci. it is

denoted by wi.

For linear block codes wmin = H.D = min (dij)

for example

[C1]=[011110] , w1 = 4

[C2]=[100001] , w2 = 2 and so on.

4. Linear and Non-linear Codes:-

When the " r " parity bits are obtained from a linear function of the

k information bits, then the code is said to be linear, other wise it

is non-linear.

For example

[C]=[ a1 a2 a3 c1 c2 ] , c1 = a1 . a2

c2 = a1 a2 a3

Linear Block Codes

The " r " parity bits are obtained using a linear function of a's data.

Mathematically, this can be described by the set of equations:-

c1 = h11.a1+ h12.a2+ h13.a3+ h14.a4+…………… h1k. ak

c2 = h21.a1+ h22.a2+ h23.a3+ h24.a4+…………… h2k. ak

: …..(1)

:

:

cr = hr1.a1+ hr2.a2+ hr3.a3+ hr4.a4+…….………… hrk.ak

Note

[+] is mod-2 (EX-OR) addition and [.] is the AND gate multiplication &

hij coefficients are binary variable for binary coding.

O/P codeword [C]= [D][G]

[D] : [ a1, a2, …… ak ]

[G] : generator matrix



5

]:[

....1000

:::::0100

....0010

....0001

][

321

2322212

1312111

kxrk

rkkkk

r

r

PI

hhhh

hhhh

hhhh

G

This matrix is called generator matrix of a Linear Block Code (LBC).

Equation (1) can also be written in matrix form as:

[H].[C]T = [0] ……….(2)

Where [C]=[ a1, a2, …… ak c1, c2, ….cr] and [H] matrix is related to [G]

by :

[H]= rxr

T

kxr IP : for binary coding the (-) signal drops out.

This rxn [H] matrix is called parity checking matrix as will be shown,

encoding can be done either using eq. (1) [[G] matrix] or eq. (2) [[H]

matrix but the decoding is done using [H] matrix only.

Hamming Bound : The number of parity bits " r " added to have certain error correction

capability is chosen by an inequality known as the humming bound. For

binary codes

t

j

n

j

rkn C0

22

Where t is the number of bits to be corrected.

For example if k=4, then to correct single error t=1 then:

rrr

j

r

j

r

CC

C

4

1

4

0

1

0

4

2

2

)!!.(

!

nmn

mCm

n



6

This gives )4(12 rr and the minimum r is r=3 (take minimum r to

have max code efficiency). This is (7,4) code note that the equality is

satisfied in this example and the code is said to be perfect.

Another example if k=5 and t=3 where three errors are corrected then:

The minimum r here is 10, and the code is (15,5). Since the equality is not

satisfied then the code is not perfect.

Hamming code: It is a single error correcting perfect code with the following parameters:

n=2r-1, HD=3, t=1. example of hamming code are (7,4),(15,11),(31,26).

The hamming codes are encoded and decoded as a linear block codes.

Encoding of Linear Block Codes:

Eq. (1) or eq. (2) can be implemented using EX-OR gates. Take for

example a (7,4) hamming code with a parity checking matrix.

[H]=

1000111

0101011

0011101

, and by using eq. (2) [H][C]T=[0] will give :

Where [C]=[ a1 a2 a3 a4 c1 c2 c3]

6

)3)(4)(5(

2

)4)(5()5(12

2

2

5

3

5

2

5

1

5

0

3

0

5

rrrrrr

CCCC

C

r

rrrrr

j

r

j

r



7

C1 = a1 + a3 + a4

C2 = a1 + a2 + a4

C3 = a1 + a2 + a3

The code table for this code can be found using the three equations of

code word.

a1 a2 a3 a4 C1 C2 C3 wi

0 0 0 0 0 0 0 ---

0 0 0 1 1 1 0 3

0 0 1 0 1 0 1 3

0 0 1 1 0 1 1 4

0 1 0 0 0 1 1 3

0 1 0 1 1 0 1 4

0 1 1 0 1 1 0 4

0 1 1 1 0 0 0 3

1 0 0 0 1 1 1 4

1 0 0 1 0 0 1 3

1 0 1 0 0 1 0 3

1 0 1 1 1 0 0 4

1 1 0 0 1 0 0 3

1 1 0 1 0 1 0 4

1 1 1 0 0 0 1 4

1 1 1 1 1 1 1 7

Wi min = 3 = HD

To find the number of errors that the (7,4) code can correct the following

eq. can be used :

2

)1int(

HDt

i.e. t=int(3-1)/2 = 1 bit. Hence, this is a single error correcting code

(Hamming code).

1a 2a 3a 4a

1C 2C C3

Output codeword

Data register

Parity register



8

Ex: find the generator matrix for the previous LBC.

Sol:

[H]=

1000111

0101011

0011101

,

-PT Ir

[G]=

0111000

1010100

1100010

1110001

][ T

kPI

Note that the equation [C]=[D][G] gives:

[C]=[ a1 a2 a3 a4 (a1 + a3 + a4) (a1 + a2 + a4) (a1 + a2 + a3)]

[C]=[ a1 a2 a3 a4 C1 C2 C3] as obtained before

Decoding of Linear Block Codes :

If [R]=[C]+[E] is the received code, where [E] is the error word.

If [E]=[0] then no error occurs.

If [E]=[0 0 ….. 0 1 0], single error occurs at second position

from the right.

If [E]=[0 0 ……1 1 0], double errors occurs at second and third

positions from the right, and so on.

The number of the errors can be corrected depend on (t) of the code.

If [R] is multiplied by [H] ( the receiver must know [H] ) then:

[H].[R]T=[H][C]T +[H][E]T

Since

[H][C]T is set to [0] at the transmitter then define [S] vector:

[S]= [H].[R]T=[H][E]T

This [S] vector is called syndrome.

If [S]=[0], the receiver decides on no errors.

If [S]≠[0], then the receiver must use [S] to find [E] and use it to

find the corrected code word.

[C]=[R]+[E] binary coding.



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Decoding for single error:

For single error hamming code, [S] is fond by multiplying [H].[R]T and

the result of the syndrome [S] is compared with each column in [H]. the

column that matches the syndrome represent the position of the error.

Thereby, for single error correction, the parity checking matrix [H] must

satisfies :

i. No all zero columns so as not to mix with no error case.

ii. No repeated columns so that the decoder can decode any received

word correctly with single error only.

Ex: for (7,4) code, with [H]=

1000111

0101011

0011101

a. Find the corrected word at the receiver, if the received word

[R]=[1001111].

b. Find the syndrome vector if double errors occur at first and last

positions

c. Draw the decoder circuit used to find [S].

Sol:

a. If [R]=[1001111]

0

1

1

1

1

1

1

0

0

1

1000111

0101011

0011101

]][[][ TRHS

[S] is similar to the forth column in [H].

Then, [E]=[0001000] and the corrected code word

]1000111[]0001000[]1001111[][][][ ERC



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b. To find [S] for double errors, then [S]= [H][E]T . where

[E]=[1000001].

0

1

1

1

0

0

0

0

0

1

1000111

0101011

0011101

]][[][ TEHS

Note that the syndrome for double error is the same as the

syndrome for double errors in this example. This assures that this

code is capable of correcting single error only.

c. To draw the decoder circuit, the syndrome equations must be found

3

2

1

7

6

5

4

3

2

1

1000111

0101011

0011101

]][[][

s

s

s

r

r

r

r

r

r

r

RHS T

s1=r1+ r3+ r4+ r5

s2=r1+ r2+ r4+ r6

s3=r1+ r2+ r3+ r7

Ex:

r1

s1 s2 s3

r1 r2 r3 r1 r4 r5 r6 r7



11

[G]=

1011100100

0110110010

0011011001

. Find the following:

a. Use Hamming bound to find error correction capability.

b. Find the parity check matrix.

c. Find the code table, hamming weight and the error correction

capability and compare it with a.

d. If the received word is [R]=[1011110011], find the corrected word

at the receiver.

Sol:

a. n=10, k=3, r=7.

The code is (10,3). Using hamming bound

Let t=1

11128

2

2

10

1

10

0

7

1

0

107

CC

Cj

j

Let t=2

)2/9*10(101128

2

2

10

2

10

1

10

0

7

2

0

107

CCC

Cj

j

Let t=3

When t=3 the hamming bound condition is disabled , there by we

take t=2 where the condition is satisfied.

)6/8*9*10()2/9*10(101128

2

2

10

3

10

2

10

1

10

0

7

3

0

107

CCCC

Cj

j



12

b. The parity check matrix is found using the generator matrix:

1000000100

0100000010

0010000111

0001000101

0000100110

0000010011

0000001001

][][ IPH T

c. The equation [H][C]T=[0] gives:

c1=a1 c2=a1+ a2 c3=a2+ a3 c4=a1+ a3

c5=a1+ a2+ a3 c6=a2 c7=a3

a1 a2 a3 c1 c2 c3 c4 c5 c6 c7 wi

0 0 0 0 0 0 0 0 0 0 ----

0 0 1 0 0 1 1 1 0 1 5

0 1 0 0 1 1 0 1 1 0 5

0 1 1 0 1 0 1 0 1 1 6

1 0 0 1 1 0 1 1 0 0 5

1 0 1 1 1 1 0 0 0 1 6

1 1 0 1 0 1 1 0 1 0 6

1 1 1 1 0 0 0 1 1 1 7

wi(min)= 5 = HD

i.e. t=int(5-1)/2 = 2 bit. Hence, this is a double error correcting

code which agrees with part a.

d. If [R]=[1011110011], then:

0

1

0

0

0

0

0

1

1

0

0

1

1

1

1

0

1

1000000100

0100000010

0010000111

0001000101

0000100110

0000010011

0000001001

]][[][ TRHS

Which is similar to the ninth column in [H] from the left, the

corrected code word [R]=[1011110001].



13

Cyclic Codes Definition A linear code is called a cyclic code if every cyclic shift of a

codeword is also a codeword. Thus, if , a=[an-1, an-2,……a0] is the

codeword of the cyclic code of length n, then the cyclic shift of this

codeword =[an-2, an-3,……a0, an-1] is the codeword of the same code.

Shifting all bits to the left one position yield another codeword as [an-3,

an-4,……a0, an-1, an-2].

Generation of Cyclic codes:

a. Non-Systematic cyclic codes: the output code word is generated

using polynomial multiplication.

Procedure:

1. For [D]=[a1, a2, …… ak] data word, write the data word in

terms of a power of a dummy variable and with a1 weighted

as MSB (Most Significant Bit) and ak as LSB (Least

Significant Bit).

i.e. D(X)=ak+ ak-1X+ ak-2X2+………..+a1X

k-1

where (+) is mod-2 addition EX-OR

for example if [D]=[11101] then

D(X)= 1+X2+X3+X4

If D(X)= 1+X2+X6 then

[D]=[1000101]

2. Multiplication: Multiply D(X) by what is called generator

polynomial g(X) of order r.

This g(X) is one of the factors of Xn+1.

For example, if n=7, then X7+1=(X+1)(X3+ X2+1)(X3+

X2+1)

For n=7, r=3, we can choose either g(X)= X3+ X2+1 or X3+

X+1.

3. The output code words will be C(X)=D(X)g(X) then C(X) is

used to find the output code word [C].



14

Ex: Write down the code table for the (7,4) non systematic cyclic code

with generator polynomial g(X)= X3+ X+1.

Sol:

K=4, r=3 then D=[ a1 a2 a3 a4 ] so the code table will be:

a1 a2 a3 a4 c1 c2 c3 c4 c5 c6 c7 wi

0 0 0 0 0 0 0 0 0 0 0 ---

0 0 0 1 0 0 0 1 0 1 1 3

0 0 1 0 0 0 1 0 1 1 0 3

0 0 1 1 0 0 1 1 1 0 1 4

0 1 0 0 0 1 0 1 1 0 0 3

0 1 0 1 0 1 0 0 1 1 1 4

0 1 1 0 0 1 1 1 0 1 0 4

0 1 1 1 0 1 1 0 0 0 1 3

1 0 0 0 1 0 1 1 0 0 0 3

1 0 0 1 1 0 1 0 0 1 1 4

1 0 1 0 1 0 0 1 1 1 0 4

1 0 1 1 1 0 0 0 1 0 1 3

1 1 0 0 1 1 1 0 1 0 0 4

1 1 0 1 1 1 1 1 1 1 1 7

1 1 1 0 1 1 0 0 0 1 0 3

1 1 1 1 1 1 0 1 0 0 1 4

[D]=[0 0 0 1] then D(X)=1

C(X)=D(X)g(X)=1.( X3+ X+1)= X3+ X+1 [C]=[0001011]

[D]=[0 0 1 0] then D(X)=X

C(X)= X.( X3+ X+1)= X4+ X2+X [C]=[0010110]

[D]=[0 0 1 1] then D(X)=X+1

C(X)=(X+1).( X3+ X+1)=

X3+ X+1+ X4+ X2+X = X4+ X3+ X2+1 [C]=[0011101]

And so on with the rest of the codes.

b. Systematic cyclic codes:



15

The polynomial representation may be used with the same

generator polynomial g(X) used in non-Systematic codes.

Procedure:

1. Find D(X) from [D]

2. Select g(X) of order r from factorization of Xn+1

3. ))(

)((Re)(.)(

Xg

XDXmXDXXC

rr where Rem is the reminder

of long division

4. Use C(X) to find [C].

Note that C(X) consists of two parts, the first is )(. XDX r which is

the same information data shifted to left by r position, the second is the

reminder )(

)(Re

Xg

XDXm

r

of order (r-1) which is the r LSBs of the output

code word or parity bits, hence [C] will have the form:

[C]=[ a1, a2, …… ak c1, c2, ….cr]

Ex: find the code table for (7,4) systematic cyclic code generated by

g(X)= X3+ X2+1

Sol:

a1 a2 a3 a4 c1 c2 c3 wi

0 0 0 0 0 0 0 ---

0 0 0 1 1 0 1 3

0 0 1 0 1 1 1 4

0 0 1 1 0 1 0 3

0 1 0 0 0 1 1 3

0 1 0 1 1 1 0 4

0 1 1 0 1 0 0 3

0 1 1 1 0 0 1 4

1 0 0 0 1 1 0 3

1 0 0 1 0 1 1 4

1 0 1 0 0 0 1 3

1 0 1 1 1 0 0 4

1 1 0 0 1 0 1 4

1 1 0 1 0 0 0 3

1 1 1 0 0 1 0 4

1 1 1 1 1 1 1 7

Here n=7, k=4, r=3



16

For [D]=[0001] , D(X)=1

Xr.D(X) =X3.1= X3 1

1

1

1

2

23

323

X

XX

XXX

C(X)=XrD(X)+Reminder

=X3+ X2+1 [C]=[0001 101]

Note that the reminder gives directly the r-parity bits if written in

binary form.

For [D]=[0010] , D(X)=X

Xr.D(X) =X3.X= X4 1

1

1

1

2

23

3

34

423

X

XX

XX

XX

XXX

XXX

C(X)= X4+ X2+X+1 [C]=[0010 111]

For [D]=[0011] , D(X)=X+1

Xr.D(X) =X3.(X+1)= X4+X3 1

1

34

3423

X

X

XXX

XXXX

C(X)= X4+ X3+X [C]=[0011 010]

And so on with the rest of the codes



17

2

1

Implementation of Cyclic Encoder:

Practically, the long division required in encoding is done using logic

circuit. That implements the division by g(X) polynomial. In general :

g(X)=g0+ g1X+ g2X2+………..+grX

r, then g0=gr=1 always for any

factorization of Xn+1. Hence only g1, g2…..,gr-1 is shown in the

implementation circuit:

This logic circuit is called Modular.

Feedback shift register implemented using D-flip flop with

synchronized clock.

Circuit Operation :-

Switch S is at position 1 giving the data bit to [C] output and at the

same time for k clock pulses, the control Z is enabled "Z=1" to

feedback the content to the registers to produce c1, c2, ….. cr bits at

the end of last clock.

Switch S is at position 2, the Z disabled to get these r parity bits to [C]

and at the same time r 0's will be fed back to the register to initialize

the register to the next data block.

NOTE

Previous encoding procedure for systematic cyclic code can be done

faster without polynomial representation if instead of g(X) is

converted into binary form called the "divisor" of the cyclic code.

Ex:

D Cr D Cr-1 D C1

g1 g2

Z control

S

[C]

]k, …… a2, a1a[



18

2

1

Using g(X)=X3+X2+1, find the output codeword for [D]=[0011] and

[D]=[0010]

Sol:

1. Convert from polynomial into binary form

g(X) =X3+X2+1 [G]=[1101]

2. Add r 0's as LSB to data=[a1, a2, …. ak] to get [a1, a2, ….

ak 0 0 0 ]

for [D]=[0011] we will have [0011000]

3. Divide it by [G]

1

010000

001101

00110001101

Then [C]=[0011010]

For [D]=[0010]

The out put should be [C]=[0010111].. how??

Ex:

Using the encoder logic circuit to find the o/p codeword for

systematic cyclic code with g(x)= X3+X2+1 and for [D]=[0101],

[0010]

Sol:

r-parity

0

D C3 D C2 D C1

g1=0 g2=1

Z control

S

[C]

]4, a3, a2, a1a[



19

First we write the transition equations for c1, c2, c3 (we write the next

state of them in terms of the present state and the input, this is done

when Z=1 then:

c3n+1=c1

n+ai

c2n+1=c3

n

c1n+1=c2

n+ c1n +ai= c2

n+ c3n+1

For [D]=[0101]

Then c1 c2 c3 =110 and [C]=[0101110]

For [D]=[0010]

Then c1 c2 c3 =111 and [C]=[0010111]

Cyclic Codes

c3 c2 c1

0 0 0

0 0 0

1 0 1

1 1 1

0 1 1

0 0 1

0 0 0

0 0 0

ai

0

1

0

1

ai

0

0

1

0

c3 c2 c1

0 0 0

0 0 0

0 0 0

1 0 1

1 1 1

0 1 1

0 0 1

0 0 0



20

Definition:A linear code is called a cyclic code if every cyclic shift of a

codeword is also a codeword. Thus, if , a=[an-1, an-2,……a0] is the

codeword of the cyclic code of length n, then the cyclic shift of this

codeword =[an-2, an-3,……a0, an-1] is the codeword of the same code.

Shifting all bits to the left one position yield another codeword as [an-3,

an-4,……a0, an-1, an-2].

Generation of Cyclic codes:

c. Non-Systematic cyclic codes: the output code word is generated

using polynomial multiplication.

Procedure:

1. For [D]=[a1, a2, …… ak] data word, write the data word in

terms of a power of a dummy variable and with a1 weighted

as MSB (Most Significant Bit) and ak as LSB (Least

Significant Bit).

i.e. D(X)=ak+ ak-1X+ ak-2X2+………..+a1X

k-1

where (+) is mod-2 addition EX-OR

for example if [D]=[11101] then

D(X)= 1+X2+X3+X4

If D(X)= 1+X2+X6 then

[D]=[1000101]

2. Multiplication: Multiply D(X) by what is called generator

polynomial g(X) of order r.

This g(X) is one of the factors of Xn+1.

For example, if n=7, then X7+1=(X+1)(X3+ X2+1)(X3+

X2+1)

For n=7, r=3, we can choose either g(X)= X3+ X2+1 or X3+

X+1.

3. The output code words will be C(X)=D(X)g(X) then C(X) is

used to find the output code word [C].



21

Ex: Write down the code table for the (7,4) non systematic cyclic code

with generator polynomial g(X)= X3+ X+1.

Sol:

K=4, r=3 then D=[ a1 a2 a3 a4 ] so the code table will be:

a1 a2 a3 a4 c1 c2 c3 c4 c5 c6 c7 wi

0 0 0 0 0 0 0 0 0 0 0 ---

0 0 0 1 0 0 0 1 0 1 1 3

0 0 1 0 0 0 1 0 1 1 0 3

0 0 1 1 0 0 1 1 1 0 1 4

0 1 0 0 0 1 0 1 1 0 0 3

0 1 0 1 0 1 0 0 1 1 1 4

0 1 1 0 0 1 1 1 0 1 0 4

0 1 1 1 0 1 1 0 0 0 1 3

1 0 0 0 1 0 1 1 0 0 0 3

1 0 0 1 1 0 1 0 0 1 1 4

1 0 1 0 1 0 0 1 1 1 0 4

1 0 1 1 1 0 0 0 1 0 1 3

1 1 0 0 1 1 1 0 1 0 0 4

1 1 0 1 1 1 1 1 1 1 1 7

1 1 1 0 1 1 0 0 0 1 0 3

1 1 1 1 1 1 0 1 0 0 1 4

[D]=[0 0 0 1] then D(X)=1

C(X)=D(X)g(X)=1.( X3+ X+1)= X3+ X+1 [C]=[0001011]

[D]=[0 0 1 0] then D(X)=X

C(X)= X.( X3+ X+1)= X4+ X2+X [C]=[0010110]

[D]=[0 0 1 1] then D(X)=X+1

C(X)=(X+1).( X3+ X+1)=

X3+ X+1+ X4+ X2+X = X4+ X3+ X2+1 [C]=[0011101]

And so on with the rest of the codes.



22

d. Systematic cyclic codes: The polynomial representation may be used with the same

generator polynomial g(X) used in non-Systematic codes.

Procedure:

5. Find D(X) from [D]

6. Select g(X) of order r from factorization of Xn+1

7. ))(

)((Re)(.)(

Xg

XDXmXDXXC

rr where Rem is the reminder

of long division

8. Use C(X) to find [C].

Note that C(X) consists of two parts, the first is )(. XDX r which is

the same information data shifted to left by r position, the second is the

reminder )(

)(Re

Xg

XDXm

r

of order (r-1) which is the r LSBs of the output

code word or parity bits, hence [C] will have the form:

[C]=[ a1, a2, …… ak c1, c2, ….cr]

Ex: find the code table for (7,4) systematic cyclic code generated by

g(X)= X3+ X2+1

Sol:

a1 a2 a3 a4 c1 c2 c3 wi

0 0 0 0 0 0 0 ---

0 0 0 1 1 0 1 3

0 0 1 0 1 1 1 4

0 0 1 1 0 1 0 3

0 1 0 0 0 1 1 3

0 1 0 1 1 1 0 4

0 1 1 0 1 0 0 3

0 1 1 1 0 0 1 4

1 0 0 0 1 1 0 3

1 0 0 1 0 1 1 4

1 0 1 0 0 0 1 3

1 0 1 1 1 0 0 4

1 1 0 0 1 0 1 4

1 1 0 1 0 0 0 3

1 1 1 0 0 1 0 4

1 1 1 1 1 1 1 7



23

Here n=7, k=4, r=3

For [D]=[0001] , D(X)=1

Xr.D(X) =X3.1= X3 1

1

1

1

2

23

323

X

XX

XXX

C(X)=XrD(X)+Reminder

=X3+ X2+1 [C]=[0001 101]

Note that the reminder gives directly the r-parity bits if written in

binary form.

For [D]=[0010] , D(X)=X

Xr.D(X) =X3.X= X4 1

1

1

1

2

23

3

34

423

X

XX

XX

XX

XXX

XXX

C(X)= X4+ X2+X+1 [C]=[0010 111]

For [D]=[0011] , D(X)=X+1

Xr.D(X) =X3.(X+1)= X4+X3 1

1

34

3423

X

X

XXX

XXXX

C(X)= X4+ X3+X [C]=[0011 010]

And so on with the rest of the codes



24

2

1

Implementation of Cyclic Encoder:

Practically, the long division required in encoding is done using logic

circuit. That implements the division by g(X) polynomial. In general :

g(X)=g0+ g1X+ g2X2+………..+grX

r, then g0=gr=1 always for any

factorization of Xn+1. Hence only g1, g2…..,gr-1 is shown in the

implementation circuit:

This logic circuit is called Modular.

Feedback shift register implemented using D-flip flop with

synchronized clock.

Circuit Operation :-

Switch S is at position 1 giving the data bit to [C] output and at the

same time for k clock pulses, the control Z is enabled "Z=1" to

feedback the content to the registers to produce c1, c2, ….. cr bits at

the end of last clock.

Switch S is at position 2, the Z disabled to get these r parity bits to [C]

and at the same time r 0's will be fed back to the register to initialize

the register to the next data block.

NOTE

Previous encoding procedure for systematic cyclic code can be done

faster without polynomial representation if instead of g(X) is

converted into binary form called the "divisor" of the cyclic code.

D Cr D Cr-1 D C1

g1 g2

Z control

S

[C]

]k, …… a2, a1a[



25

2

1

Ex:

Using g(X)=X3+X2+1, find the output codeword for [D]=[0011] and

[D]=[0010]

Sol:

4. Convert from polynomial into binary form

g(X) =X3+X2+1 [G]=[1101]

5. Add r 0's as LSB to data=[a1, a2, …. ak] to get [a1, a2, ….

ak 0 0 0 ]

for [D]=[0011] we will have [0011000]

6. Divide it by [G]

1

010000

001101

00110001101

Then [C]=[0011010]

For [D]=[0010]

The out put should be [C]=[0010111].. how??

Ex:

Using the encoder logic circuit to find the o/p codeword for

systematic cyclic code with g(x)= X3+X2+1 and for [D]=[0101],

[0010]

r-parity

0

D C3 D C2 D C1

g1=0 g2=1

Z control

S

[C]

]4, a3, a2, a1a[



26

Sol:

First we write the transition equations for c1, c2, c3 (we write the next

state of them in terms of the present state and the input, this is done

when Z=1 then:

c3n+1=c1

n+ai

c2n+1=c3

n

c1n+1=c2

n+ c1n +ai= c2

n+ c3n+1

For [D]=[0101]

Then c1 c2 c3 =110 and [C]=[0101110]

For [D]=[0010]

Then c1 c2 c3 =111 and [C]=[0010111]

c3 c2 c1

0 0 0

0 0 0

1 0 1

1 1 1

0 1 1

0 0 1

0 0 0

0 0 0

ai

0

1

0

1

ai

0

0

1

0

c3 c2 c1

0 0 0

0 0 0

0 0 0

1 0 1

1 1 1

0 1 1

0 0 1

0 0 0



27

Decoding of Systematic Cyclic Code:-

At the receiver

[R]=[C]+[E] where [E] is the error word

Or

R(X)=C(X)+E(X) , E(X) is the error polynomial

Now if we divide above equation by g(X) taking the reminder :-

)(

)(Re

)(

)(Re

)(

)(Re

Xg

XEm

Xg

XCm

Xg

XRm

And since 0)(

)(Re

Xg

XCm as shown before, then :-

)()(

)(Re

)(

)(Re XS

Xg

XEm

Xg

XRm

=syndrome polynomial of order (r-1).

1. If S(X) = 0 then no error occurs.

2. If S(X) # 0 then error occurs

To find the locations of these errors, the receiver may prepare a syndrome

table, store it in its memory, use it to find [E] from [S] starting with less

number of errors.

Ex: Prepare the syndrome table for (7,4) systematic cyclic code with

g(X)=X3+X2+1 and for single error. Check the syndrome when double

error at first and last positions occur.

Sol:-

Error Word [E] S1 S2 S3

0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 1 0 0 1

0 0 0 0 0 1 0 0 1 0

0 0 0 0 1 0 0 1 0 0

0 0 0 1 0 0 0 1 0 1

0 0 1 0 0 0 0 1 1 1

0 1 0 0 0 0 0 0 1 1

1 0 0 0 0 0 0 1 1 0

0 0 0 0 0 1 1 0 1 1

0 0 0 0 1 0 1 1 0 1



28

Each [S] is found from [E] by long division by g(X). for example if

[E]=[0100000] error at second position from the left then:-

1 1 0 1 0 1 0 0 0 0 0

1 1 0 1

0 1 0 1 0

1 1 0 1

0 1 1 1 0

1 1 0 1

0 0 1 1

[S]

Note that no repeated [S] for all possible single error. This is

expected since wi(min)=3 and the given (7,4) code is a single error

correction. Note also for double error [E]=[0000011], then

[S]=[011] which is single error at the second position (from the

left), there by these errors cannot be corrected.

Now going back to the example for double error [E]=[1000001]

1 1 0 1 1 0 0 0 0 0 1

1 1 0 1

0 1 0 1 0

1 1 0 1

0 1 1 1 0

1 1 0 1

0 0 1 1 1

[S]

[S]=[111] which is the same [S] as if single error occurs at third position

from the left.



29

Ex: using previous syndrome table, find the corrected word for the

received word [R]=[1010011].

Sol:-

First, the receiver will find [S] from the reminder of R(X)/g(X)

1 1 0 1 1 0 1 0 0 1 1

1 1 0 1

0 1 1 1 0

1 1 0 1

0 0 1 1 1 1

1 1 0 1

0 0 0 1 0

[S]

Hence, [S]=[010], using syndrome table and for this syndrome,

[E]=[0000010]

Then the corrected codeword

[C]=[R]+[E]

1010011

0000010

[C] = 1010001

Implementation of Cyclic Decoder:

The long division of [R] by [G] to obtain the reminder is implemented is

using logic circuit as shown for the generator g(X). The control Z is

enabled for "n" clock pulses and then disabled for "r" clock pulses.

Sr Sr-1 S1

g1 g2 Z control

S=[S1 S2 …… Sr]

] nr, …, 2r, 1r[ [R]=



30

Ex: use the decoder circuit to find the syndrome and the corrected word

for the received word [R]=[1011010] , if g(X)= X3+X2+1

Sol:-

First we write the transition equations for S1 S2 S3 when Z=1 :-

S3n+1=S1

n+ri

S2n+1=S3

n

S1n+1=S2

n+ S1n

Then [S]=[110], using the syndrome table then [E]=[1000000].

The corrected code word

1011010

1000000

[C] = 0011010

S3 S2 S1

0 0 0

1 0 0

0 1 0

1 0 1

0 1 1

1 0 0

1 1 0

0 1 1

ri

---

1

0

1

1

0

1

0

Sr Sr-1 S1

g1=0 g2=1 Z control

S=[S1 S2 S3]

[R]= [1011010]

Channel Coding - ceng.tu.edu.iq

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