Challenges in Hybrid DSP/FPGA Implementations of Challenges in Hybrid DSP/FPGA Implementations of Optimal BeamformingOptimal Beamforming

Bogdan Vacaliuc, Sundance DSP, Inc.Bogdan Vacaliuc, Sundance DSP, Inc.

Company Highlights and Background BF1 System Requirements Top Level Design Partitioning Case Studies Current Status Future Expansion Options

Overview

Sundance

Established 1989, Privately held Company; Assets in excess of $2M

Sundance Design, Manufacturing, Test in England and USA; Sales Offices around the World

Sundance is ISO9100-2000 compliant company and has been since 1998.

World Leading Users Michigan Tech University SPAWAR Systems Center - Charleston Lockheed Martin Cymer NASA Raytheon TRW General Dynamics Philips Medical Motorola L3-Communication Lucent Technologies MIT Rolls Royce ...

Concept of Modular Design

Module CarriersPCI cPCI VME PMC

Modules

A/D,D/A,I/ODSP,FPGA

IMAGING,MEMORY

Systems•Data Acquisition

•Medical•Industrial Control

& Monitoring

•Dual 300 MHz TI C6713

•Xilinx Virtex II XC2V2000-4

•256MB SDRAM

•920MB/s I/O bandwidth

SMT361QSMT374-300 SMT398 SMT318-SX55

Processing modules

•Quad TI C6416

•Xilinx Virtex II XC2V2000-4

•4MB internal memory

•920MB/s I/O bandwidth

•Xilinx Virtex II XC2V8000-4

•4MB ZBT SRAM

•2MB QDR SRAM

•1.6GB/s I/O bandwidth

•Dual Xilinx XC4VSX55-12

•1024 XtremeDSP

•1.6GB/s inter-FPGA I/O

•2.5GB/s I/O bandwidth

PlatformsPCI SMT310Q cPCI SMT300Q

VME SMT328Embedded SMT180

Company Highlights and Background BF1 System Requirements Top Level Design Partitioning Case Studies Current Status Future Expansion Options

BF1 System Requirements

Digital System for processing 8 element ULA or UCA (receiver only)

Target Signal: Family Radio Service (FRS)– 462.5625MHz to 467.7125MHz

– 25KHz channel separation Intermediate Frequency

– 21.4MHz Center

– 22.5MHz Bandwidth Able to separate “talkers” on the same

frequency USB 2.0 Interface to HOST

BF1 System Requirements (cont.)

Flexibility in implementing different beamforming algorithms

Flexibility in implementing different channel (de)modulation algorithms

Multi-Channel operation required– The more channels, the better

Company Highlights and Background BF1 System Requirements Top Level Design Partitioning Case Studies Current Status Future Expansion Options

Top Level Design

A tuner for each antenna An ADC for each tuner One channelizer A beamformer/demodulator for each

channel

ChannelizerTuner ADC

Beamformer Demodulator

Output to Host

ADC Selection

Fs > 75MHz– Fs > 2*(IFcenter+(IFspan/2)+Guard)

Ideal Fs is 102.4MHz Fs = Fc*M M= # FFT points Fc = 25KHz M is > 3000 for Fs > 75MHz Pick 4096 point FFT, Fs = 102.4MHz

Maximize #ADC per module Maximize ADC resolution Pick SMT364

– Quad 105MSPS ADC– 14-bit resolution

CLOCK Selection

Need to synchronize 8 ADCs (or more)

On board clock is not synchronized between all ADCs– Each pair of ADCs are clocked together

SMT364 requires two external clocks per module

For beamforming it is essential to have high stability clock sources that do not drift over time

MOST IMPORTANT component

CLOCK Selection (cont.)

Evaluate oscillator performance by considering phase noise tables

Estimate RMS jitter and compute absolute maximum SNR Make sure maximum SNR >> ADC specification

Mfg. Part Number Jitter Metric[1]

Peak SNR[2]

Greenray YH1441-B17-3.3-102.4MHz 0.041ps 91.6dB

Raltron OX6551A-LX-3-102.400 0.031ps 94dB

SBtron SBOC25BBS-3.3V-Sine-102.4MHz 0.020ps 97.8dB

Valpey-Fisher

VFTCS-B58L3S-102.4MHz 0.005ps 109dB

Vectron C4530-D107-SV033-RFS-B1-102.4MHz 0.875ps 65dB

[1] Computed from the on-line calculator at: http://www.raltron.com/cust/tools/osc.asp [2] SNR = 20log10(1/(2*PI*Fsignal*Tjitter)) as described in: http://www.analog.com/en/content/0,2886,760%255F788%255F91502,00.html

SMT399-F102.4 Module

Fixed Frequency Clock Source Frequency Stability: 50ppb Aging: 300ppb/year Option for external clock input

Fine Frequency adj. for calibration

External Clock (build option)

MMBX or SMA (build option)

MMCX (build option)

4-way Power Splitter < 3° phase variance

Amplifier with phase adjustment

On-board linear regulator and power filter

Flexible power input (TIM or EXT)

System Level – Analog Connections

EXTERNALSMT399-F102.4

TIM SITE B3SMT374-300

DSP4A,B

--- Front of Enclosure ---

TIM SITE B2SMT318-SX55

FPGA2

TIM SITE B1SMT361QDSP3A-D

TIM SITE B4SMT364

ADC2

TIM SITE A2SMT318-SX55

FPGA1

TIM SITE A3SMT364

ADC1

TIM SITE A1SMT374_300

DSP1A,B(root)

TIM SITE A4SMT361QDSP2A-D

SH

BA

1

JP1

JP2

FPGAXC2VP7

ASICCY7C68013

USB1

SH

BA

1

FPGAXC2VP7

(UNCONFIG)

ExternalBufferedComport USB2.0

TRIGGER-OUT

SP

AR

E

B-1

B-2

B-3

B-4

TR

IGG

ER

-IN

CLO

CK

-IN

A-1

A-2

A-3

A-4

J6

J8J9

J10 J7

J12

J13J11

J6

J8J9

J10 J7

J12

J13J11

J3J1

J5 J7

J10J2J1 J2J1

ADC Correction and Normalization

Parameters (offset, gain, delay) Offset

– For BF1 System each ADC is channelized independently, so offset not a problem

– For systems that interleave ADC to increase the effective sampling rate it is critical

Gain– Can be adjusted by ADC parameter– Can be adjusted numerically– Numerical adjustment is easier

Delay– ADCs can start at slightly different clock

edges (even with a trigger pulse distribution)

Design Level – ADC block detail

Common handling (in FPGA firmware) of all channels Prepares data stream for channelization

FC201 for ADC channel correction

FC202 for quadrature conversion

Company Highlights and Background BF1 System Requirements Top Level Design Channelization Case Studies Current Status Future Expansion Options

Channelization

Polyphase Filter– Each channel represents a

frequency band– M is chosen with respect to

Fs (102.4MHz) and channel spacing (25KHz)

In the BF1 System– Fs is 102.4MHz– M is 4096

Provides 4096 channels @25KSPS

Channel Partitioning and Distribution

Bandwidth problem– 8 * 4 * 102.4MHz is 3.2GB/sec– No module has that amount of I/O

capacity

Separate channels based on region of interest.– Beamforming is done on each channel

separately

Combine output from all ADCs– On different FPGAs in our system

Channel Partitioning (cont.) Use an FC108 block for

each ADC input FC108-D is a double-data

rate version of FC108– Fits onto XC4VSX55

– 220MHz with -12 part FC203A exchanges

high/low channels and ADC streams

FC203B formats the selected channels into a multiplexed “frequency domain highway”

FDMA Highway

Enables distribution of multiple channels from all ADCs to other modules

40us frame time represents the channel spacing (25KHz)– (FC202 decimated Fs by 2 with no loss of spectral

information)

AI(0)AQ(0)

BI(0)BQ(0)

HI(0)HQ(0)

AI(1)AQ(1)

BI(1)BQ(1)

HI(1)HQ(1)

AI(M-1)AQ(M-1)

BI(M-1)BQ(M-1)

HI(M-1)HQ(M-1)

15..031..16

Channels (0..C-1)

Slots (0..M=(SPAN/2)-1)

Bits in word

Channels in microframe

40µs

Putting it all together…

Software and Firmware Development

Code &Build

Debug

Analyze &Tune

-Simulink/Matlab-C Reference ModelsModeling

-Real Time Analysis-Profiling (CCS)-Timing (GPIO)

-PARS-System Generator-Diamond + CCS + ISE

-Debugger,Simulator-Data I/O, Scripting-Hardware In The Loop

Tasks & Channels

Develop System Model

Map onto hardware

Generate System Firmware

Software

Level 2

Level 1

SundanceTarget

Hardware

SMT319 with Xilinx Virtex II XC2V2000-4

MATHWORKSTM

SimulinkTM

SystemGenerator

PARS

Code ComposerStudioTM

Traditional VHDLDevelopment Tools

Photo of Initial Prototype System

Roadmap

System-System Interconnects– Expand on number of ADC channels

– Enable additional antennas

PARS Enhancements– Use HDL Coder to enable Simulink->FPGA

– Increasingly automatic code generation

Sundance will lead in modular, deployable signal processing

?

Thank YouThank You