4.10 MOSFET circuit symbols and model summary

Arrow points in the direction of positive current

D

B

S

G

(a) NMOS enhancement-mode device

D

B

S

G

(b) PMOS enhancement-mode device

D

B

S

G

(d) PMOS depletion-mode device

D

S

G

(e) Three-terminal NMOS transistor

D

S

G

(f) Three-terminal PMOS transistor

D

B

S

G

(c) NMOS depletion-mode device

Figure 4.18 - IEEE Standard MOS transistor circuit symbols

Arrow points in the direction of

Mathematical Model Summary NMOS Transistor model summary

For all regions 00'' === BGoxnn iiL

WCK µ

Cutoff region:

0=DSi for TNGS Vv ≤ Linear region:

DSDS

TNGSNDS vv

VvKi )2

( −−= for 0≥≥− DSTNGS vVv

Saturation region:

)1()(2

2DSTNGS

NDS vVv

Ki λ+−= for 0≥−≥ TNGSDS Vvv

Threshold voltage:

)22( FFSBTOTN vVV φφγ −++=

PMOS transistor mathematical model summary For all regions

00'' === BGoxnn iiL

WCK µ

Cutoff region:

0=SDi for )( TPGSTPSG VvVv ≥−≤ Linear region:

SD

SD

TPSGPSDv

vVvKi )

2( −+=

for 0≥≥+ SDTPSG vVv Saturation region:

)1()(2

2

SDTPSG

P

SDvVv

Ki λ++= for 0≥+≥ TPSGSD Vvv

Threshold voltage:

)22( FFBSTOTP vVV φφγ −+−=

D

B

S

G

iDS

vGSvSB

vDS

NMOS transistor

D

B

S

G

iSD

vSG vBS

vSD

PMOS transistor

+

-

-

-

-

-+

+

++

+

-

Figure 4.19 - NMOS and PMOS transistor circuit symbols

Table 4.1 - Categories of MOS Transistors

NMOS Device PMOS Device Enhancement-mode VTN > 0 VTP < 0 Depletion-mode VTN <= 0 VTP >=0

4.11 Biasing the MOSFET An example biasing circuit Example 4.1

Find the Q-point using the mathematical model for the NMOS transistor We replace the gate-bias network consisting of

GGV , 1R and 2R with its Thevenin equivalent circuit

VGG

R2

R1

IDS

VDD 10 V

RL 100 kΩ

30 kΩ

70 kΩ

10 V

D

G

S

V = 1 VTN

K = 25 µA/V 2n

Figure 4.20 - Constant gate voltage bias using a voltage divider

VEQ

with

GGEQ VRR

RV

21

1

+= and

21

21

RR

RRREQ +

=

We can determine the Q-point by using Kirchhoff’s

voltage law (KVL) in the loops with GSV and DSV

GSEQGEQ VRIV += (*)

DSLDSDD VRIV +=

VGS

REQ

VDD

RL

Q

+

-

IG

21 kΩ

3 V

100 kΩ

10 V

VDS

+

-I DS

D

S

G

Figure 4.21 - Simplified MOSFET bias circuit

We know for the MOSFET, however that 0=GI so that VVV EQGS 3== and we get

AVVK

I TNGSn

DS µ50)(2

2 =−=

and

VVV

VRIVV

TNGS

LDSDDDS

2

5

=−=−=

We see that DSV exceeds TNGS VV − so that the

transistor is indeed saturated. Thus, the Q-point is )5,50( VAµ , with VVGS 3= .

Example 4.2

The Q-point for the MOSFET circuit in Fig.4.20 can also be found graphically with a load-line method. The second expression in Eq.(*) represents the load line for this MOSFET circuit:

or DSDS

DSLDSDD

VI

VRIV

+=

+=51010

The load-line is constructed by finding two points:

for AIV DSDS µ100,0 == , and for VVI DSDS 10,0 == . The resulting line is drawn on the output characteristics of the MOSFET in Fig.4.22

Example 4.3 The I-v characteristic of an ideal current source is shown in Fig.4.23 which provides a constant output

121086420-2.50e-5

0.00e+0

2.50e-5

5.00e-5

7.50e-5

1.00e-4

1.25e-4

1.50e-4

Drain-Source Voltage (V)

Dra

in C

urr

ent

(A)

Q-Point

Load Line

V = 4 V

V = 3 V

V = 2 V

GS

GS

GS

Figure 4.22 - Load line for the circuit in Figs. 4.20 and 4.21

current regardless of the polarity of the voltage across the source. If the value of DDV is chosen to be larger than the value needed to pinch off the MOSFET [in this case, VVVV TNGSDD 213)( =−=−≥ ], then the output

current will be constant at 50 Aµ . For ,2VVDD ≥ the MOSFET represents an electronic current source

with a 50 Aµ output current.

86420-2-4-6-8-20

0

20

40

60

80

100

Voltage V (V)

Cu

rren

t I

(

µA)

Ideal 50 uA Current Source (Sink)

NMOSFETV = 3 V

Pinchoff Point

GS

DC

DC

Figure 4.23 - Output characteristics for an ideal current source and the

MOSFET current source

Figure 4.24 shows the NMOS transistor biased with a 3-V dc source. This simple two-terminal MOSFET circuit will behave as an electronic current source

AII DSDC µ50== over a limited range of terminal voltage, as long as

the external voltage DCV exceeds 2V.

Here, the current enters the source and it is often referred to as a current sink.

IDCVDC

IDS

+

IDC

V =3 VGS

+

VDC

-

+

-

V vDC DSAT

D

G

S

Figure 4.24 - NMOS transistor as an electronic current source

Example 4.4

The four-resistor bias circuit in Fig.4.25(a) will stabilize the MOSFET Q-point in the face of many types of circuit parameter variations. A single voltage source DDV is now used to supply both the gate-bias voltage and drain current. A Thevenin transformation is applied to this circuit, resulting in the equivalent circuit given in Fig.4.26. This is the final circuit to be analyzed.

V = 1 VTN

K = 25 µA/V 2n

R2

R1

RD

RS

VDD+

150 k Ω

100 k Ω 39 k Ω

75 k Ω

10 VD

S

G

(150 k Ω)

(100 k Ω)(18 k Ω)

(22 k Ω)

Figure 4.25(a) - Four resistor bias network for a MOSFET

Note that this circuit uses the three-terminal representation for the MOSFET in which it is assumed that the bulk terminal is tied to the source. If the bulk terminal were grounded, the analysis would become more complex because the threshold voltage would then be a function of the voltage developed at the source terminal of the device. To determine the Q-point for the circuit in Fig.4.26, we write the following two loop equations:

SDSGGSEQGEQ RIIVRIV )( +++=

SDSGDSDDSDD RIIVRIV )( +++= Because we know that 0=GI ,these equations reduce to

R2

R1

RD

RS

VDD+

VDD10 V

150 kΩ

100 kΩ

75 kΩ

39 kΩ

10 V

D

S

G

Figure 4.25(b) - Equivalent circuit with replicated sources

SDSGSEQ RIVV +=

DSSDDSDD VRRIV ++= )(

Again assuming that the transistor is operating in the saturation region with

2)(2 TNGS

nDS VV

KI −=

the input loop equation becomes

2)(2 TNGSn

GSEQ VVRK

VV −+=

and we have a quadratic equation to solve for GSV .For the values in Fig.4.25 with VVTN 1= and

2/25 VAKn µ=

So we get GSV = V66.2± For GSV = V66.2− ,the MOSFET would be cut off because TNGS Vv < . So,

GSV = V66.2+ is the answer, and AI DS µ4.34= . DSV is then found to be 6.08V. We have

)(66.1,08.6TNGSDSTNGSDS

VVVVVVVV −≥=−= The saturation region assumption is consistent with the resulting Q-point: )08.6,4.34( VAµ with

VVGS 66.2=

Example 4.5 Let us redesign the four-resistor bias network in the previous example to increase the current while

keeping DSV approximately the same: the desired Q-point will be )6,100( VAµ . We can see that the sum of

VDD

REQ

RD

V EQ I

G RS

IDS

4 V

60 kΩ

75 kΩ

10 V+

-

+

-VGS

VDS

DG

S

39 kΩ

+

-

VS

Figure 4.26 - Equivalent circuit for the four resistor bias network

DR and SR in the bias network of Fig.4.26 is determined by the Q-point values

Ω=−=+ KI

VVRR

DS

DSDDSD 40

The required value of SR

DS

S

GS

GSEQS I

V

I

VVR =

−=

But we must first find the value of GSV The gate-source voltage needed to establish

AI DS µ100= can be found by rearranging the expression for the MOSFET drain current,

VK

IVV

n

DSTNGS 83.3

2 =+=

So Rs=1.7 ΩK