ch34 microelect processing - Dokuz Eylül Universityweb.deu.edu.tr/.../MME1011processing.pdf ·...
13
Kalpakjian • Schmid Manufacturing Engineering and Technology © 2001 Prentice-Hall Page 34-1 CHAPTER 34 Fabrication of Microelectronic Devices* *By Kent M. Kalpakjian
Transcript of ch34 microelect processing - Dokuz Eylül Universityweb.deu.edu.tr/.../MME1011processing.pdf ·...
Kalpakjian • SchmidManufacturing Engineering and Technology
© 2001 Prentice-Hall Page 34-1
CHAPTER 34
Fabrication of Microelectronic Devices*
*By Kent M. Kalpakjian
Kalpakjian • SchmidManufacturing Engineering and Technology
© 2001 Prentice-Hall Page 34-2
Printed Circuit Boards
Figure 34.1 A collection of printed circuit boards. Source: Phoenix Technologies, Inc.
Kalpakjian • SchmidManufacturing Engineering and Technology
© 2001 Prentice-Hall Page 34-3
Fabrication Sequence of
and Integrated Circuit
Figure 34.2 General fabrication sequence for integrated circuits.
Kalpakjian • SchmidManufacturing Engineering and Technology
© 2001 Prentice-Hall Page 34-4
MOS Transistor Cross-Sections
Figure 34.3 Cross-sectional views of the fabrication of a MOS transistor. Source: R. C. Jaeger.
Kalpakjian • SchmidManufacturing Engineering and Technology
© 2001 Prentice-Hall Page 34-5
Chemical Vapor Deposition
Figure 34.4 Schematic diagrams of (a) continuous, atmospheric-pressure CVD reactor and (b) low-pressure CVD. Source: S. M. Sze.
Kalpakjian • SchmidManufacturing Engineering and Technology
© 2001 Prentice-Hall Page 34-6
Silicon Dioxide Growth
Figure 34.5 Growth of silicon dioxide, showing consumption of silicon. Source: S. M. Sze.
Kalpakjian • SchmidManufacturing Engineering and Technology
© 2001 Prentice-Hall Page 34-7
Pattern Transfer by Lithography
Figure 34.6 Pattern transfer by lithography. Note that the mask in step three can be a positive or negative image of the pattern. Source: After W. C. Till and J. T. Luxon.
Kalpakjian • SchmidManufacturing Engineering and Technology
© 2001 Prentice-Hall Page 34-8
Etching and Ion Implantation
Figure 34.7 Etching profiles resulting from (a) isotropic wet etching and (b) anisotropic dry etching. Source: R. C. Jaeger.
Figure 34.8 Apparatus for ion implantation
Kalpakjian • SchmidManufacturing Engineering and Technology
© 2001 Prentice-Hall Page 34-9
pn Junction Diode
Figure 34.9 (continued)
Kalpakjian • SchmidManufacturing Engineering and Technology
© 2001 Prentice-Hall Page 34-10
pn Junction Diode (cont.)
Figure 34.9
Kalpakjian • SchmidManufacturing Engineering and Technology
© 2001 Prentice-Hall Page 34-11
Two-Level Metal Interconnect
Figure 34.10 (a) Scanning electron microscope photograph of a two-level metal interconnect. Note the varying surface topography. Source: National Semiconductor Corporation. (b) Schematic drawing of a two-level metal interconnect structure. Source: R. C. Jaeger.
(a) (b)
Kalpakjian • SchmidManufacturing Engineering and Technology
© 2001 Prentice-Hall Page 34-12
Bonding and Packaging
(a) (b) (c)
Figure 34.11 (a) SEM photograph of wire bonds connecting package leads (left-hand side) to die bonding pads. (b) and (c) Detailed views of (a). Source: Courtesy of Micron Technology, Inc.
Kalpakjian • SchmidManufacturing Engineering and Technology
© 2001 Prentice-Hall Page 34-13
Integrated Circuit Packages
Figure 34.12 Schematic illustrations of different IC packages: (a) dual-in-line (DIP), and (b) ceramic flat pack, and (c) common surface mount configuration. Sources: R. C. Jaeger and A. B. Glaser; G. E. Subak-Sharpe.
