Ch3- Io Systems

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    352 ALL OPERATING SYSTEM 2SECTION # 474 & 475

    Prepared by: Fathima Sakeena

    CHAPTER 3 I/O SYSTEMS

    TEXT BOOK : Operating System Concepts with JAVA, 6th Edition,Silberschatz, Galvin, Gagne (Willey International Edition)

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    Chapter 3 I/O Systems

    I/O Hardware

    Polling

    Interrupts

    Direct Memory Access

    Application of I/O Interface

    Block and character devices,

    Network devices Clocks and timers

    Kernel I/O.

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    A typical PC bus structure

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    1. PCI (Peripheral component Interconnect)bus connects processor

    and memory subsystem with fast devices.

    2. Expansion bus connects slow devices such as keyboard, serial and

    parallel ports.

    3. SCSI ( small computer system Interface)bus connects the disks and

    SCSI controller.

    How can the processor give commands and data to controller to perform

    I/O transfer?

    Controller has one or more registers for data and control signals.

    Processor communicates with controller by reading writing bit

    patterns from these registers

    IDE integrated device electronics

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    A Typical PC Bus Structure6

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    I/O port registers

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    I/O port consists four registers status, control, data in, data

    out.

    1. Status register contains bits that can be read by host. This

    bits indicate whether the current command completed, byte is

    available in data in register or device error.

    2. Control register can be written by host to start new

    command or to change the mode of the device.

    3. Data in register read by host to get input.

    4. Data out register written by host to sent output.

    Data registers are typically 1 to 4 bytes, here host refers to any

    one of the I/O device.

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    Polling

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    Communication between host and controller

    Controller indicates its status through the busy bit in status register.

    Controller sets busy bit when its is working, and clears the busy bit, when it is

    ready to accept the next command.

    The host sets the command ready bit , when a command in available incommand register.

    If the controller is busy , the host is reading the status register over and over

    until the busy bit becomes clear. This called as busy waiting or polling.

    Polling becomes inefficient , when it is attempted repeatedly, the host is ready

    for service but controller is busy. The hard ware mechanism enables the host to notify the CPU, that the device

    becomes ready for service.This is called an interrupt.

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    Interrupts

    The CPU hardware has a wire called the interrupt request line

    that CPU senses after executing every instruction.

    When CPU detects a interrupt, CPU transfers the control to

    interrupt handler routine. Interrupt handler routine performs

    the necessary processing, then return to CPU.

    Device controller raises an interrupt interrupt signal send via

    interrupt request line CPU catches the interrupt

    dispatches to interrupt handler handler clears the interrupt

    by servicing the device. Two types of interrupts maskable and non maskable.

    Non maskable interrupts for unrecoverable memory errors

    Maskable for device controllers

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    Interrupt-Driven I/O Cycle

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    Direct Memory Access

    Device wants to transfer large amount of data, it seems wasteful

    to use PIO.

    PIO programmed IO- CPU watches the status bit and transfers

    one byte at a time.

    To avoid these problem, the special purpose processor called

    Direct memory access (DMA) controller.

    DMA transfer is explained in following diagram with six steps.

    Handshaking between DMA controller and device controller can

    be performed via a pair of lines called DMA- request and DMA acknowledgement.

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    Six Step Process to Perform DMA Transfer

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    Application I/O Interface

    I/O system calls encapsulate device behaviors in generic

    classes.

    Device-driver layer hides differences among I/O controllers

    from kernel.

    Devices vary in many dimensions.

    Character-streamor block

    Sequentialor random-access

    Sharable or dedicated

    Speedof operation

    read-write, read only, or write only

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    A Kernel I/O Structure

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    Characteristics of I/O Devices

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    Block and Character Devices

    Block devices include disk drives

    Understands the commands - read ( ), write ( ), seek ( )

    Applications access a device through file system interface.

    Some special applications (like DBMS) access a device as asimple linear block. This is called as raw I/O.

    Memory-mapped file access can be layered on top of the

    block devices.

    Character devices include keyboards, mice, serial ports

    Understands the commands - get(), put()

    Libraries layered on top allow line editing

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    Clocks and Timers

    Computers have hardware clocks and timers that provide three

    basic functions

    Give the current time

    Give the elapsed time Set a timer to trigger operation

    Programmable interval timer is a hardware used to measure

    elapsed time and to trigger operation.

    It can be set to wait for certain amount of time then to generate

    an interrupt.

    It can be set to do this operation once or repeat the process , to

    generate periodic interrupts.

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    Blocking and Nonblocking I/O

    System call interface has two types - blocking I/O or non blocking I/O.

    When an application issues a blocking system call,

    The execution of the application is suspended

    Application is moved from run queue to wait queue.

    Complete the I/O operation.

    Application is moved back to run queue

    This blocking system call is easy to use and understand

    When an application issues a non blocking system call,

    Does not halt the execution of application

    It returns quickly , with a return value indicates how many bytes were

    transferred. The non blocking system call is implemented via multi-threading.

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    Kernel I/O Subsystem

    Kernel provides many services related to I/O - scheduling,

    buffering, catching, spooling, device reservation and error

    handling.

    1. Scheduling

    Schedule a set of I/O requests to determine a good order to

    execute them.

    This is implemented via device queue

    2. Buffering - store data in memory while transferring between

    two devices

    To cope with device speed mismatch

    To cope with device transfer size mismatch

    To maintain copy semantics

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    Kernel I/O Subsystem

    3. Caching - fast memory holding copy of data

    Always access the copy not the original

    4. Spooling - hold output for a device

    If device can serve only one request at a time i.e., Printing

    5. Device reservation - provides exclusive access to a device

    System calls for allocation and de allocation

    Watch out for deadlock

    6. Error handling

    OS can recover from disk read, device unavailable,

    transient write failures

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