Ch03 Lecture Presentation

8/3/2019 Ch03 Lecture Presentation

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Di ital Desi n

Chapter 3:

Sequential Logic Design -- Controllers

Slides to accompany the textbookDigital Design, with RTL Design, VHDL,

and Verilog, 2nd Edition,

by Frank Vahid, John Wiley and Sons Publishers, 2010.

http://www.ddvahid.com

Digital Design 2e

Copyright 2010

Frank Vahid

1

Copyright 2010 Frank VahidInstructors of courses requiring Vahid's Digital Design textbook (published by John Wiley and Sons) have permission to modify and use these slides for customary course-related activities,

subject to keeping this copyright notice in place and unmodified. These slides may be posted a s unanimated pdf versions on publicly-accessible course websites.. PowerPoint source (or pdf

with animations) maynot be posted to publicly-accessible websites, but may be posted for students on internal p rotected sites or distributed directly to students by other electronic means.

Instructors may make printouts of the slides available to students for a reasonable photocopying charge, without incu rring royalties. Any other use requires explicit permission. Instructors

may obtain PowerPoint source or obtain special use permissions from Wiley see http://www.ddvahid.comfor information.

Introduction

Sequential circuit

Output depends not just on present inputs (as incombinational circuit), but on ast se uence of in uts

3.1

Combinational

digital circuit

1a

b

1F0

Stores bits, also known as having state

Simple example: a circuit that counts up in binary

This chapter will: Design a new building block, a flip-flop, to store one bit

Combine flip-flops to build multi-bit storage register

Describe sequential behavior with finite state machines

Convert a finite state machine to a controller

1a

b

? F0

Must know

sequence of

past inputs to

know output

Sequentialdigital circuit

Digital Design 2e

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Frank Vahid

2

sequential circuit with a register and combinational logic

Note: Slides with animation are denoted with a s mall red "a" near the animated items


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Storing One Bit Flip-Flops

Example Requiring Bit Storage

Flight attendant call button

3.2

BitStorage

Blue lightCallbutton

Cancel

button

1

Press call: light turns on

Stays onafter button released

Press cancel: light turns off

Stays off after button released

Logic gate circuit to implement this?

QCall

a

1. Call button pressed light turns on

Bit

Storage

Blue lightCall

button

Cancel

button

2. Call button released lightstays on

1

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Cancel

Doesnt work. Q=1 when Call=1, but

doesnt stay 1 when Call returns to 0

Need some form of feedback in the circuit

a BitStorage

Blue lightCall

button

Cancel

button

3. Cancel button pressed light turns off

0

First attempt at Bit Storage

Need some sort of feedback

Does circuit on the right do what we want?

QS

t

No: Once Q becomes 1 (when S=1), Q stays 1forever no value of S can bring Q back to 0

0t

0 QS 0

1S

0t

1 QS 00t

1 QS 11t

1 QS 11t

0 QS 1a

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1

0

1

0Q

t


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Bit Storage Using an SR Latch

Q

S (set) SR latch Does the circuit to the right, with cross-coupled

NOR gates, do what we want? Yes! How did someone come up with that circuit?

Maybe just trial and error, a bit of insight...

0

0

1

R=1

S=0t

Q

1S

R (reset)

1

0 0

10

1

t

Q

S=0

R=0

t

Q

S=1

R=0

0

1

1

t

Q

R=0

S=0

1

01

0

0

01

1

X0

Recall NOR

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1

0R

1

0t

1

0Q

a

Example Using SR Latch for Bit Storage

SR latch can serve as bitstorage in previous exampleof fli ht-attendant call button

BitStorage


Cancelbutton

Call=1 : sets Q to 1

Q stays 1 even after Call=0

Cancel=1 : resets Q to 0

But, theres a problem...

S

Q

Call

button

Blue light

Cancelbutton 1

0

1

a

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Problem with SR Latch

Problem

If S=1 and R=1 simultaneously, we dont know what value Q will take

R=1

S=1

0

0

0

0

t

Q

R=0

S=0

0

0

1

1

t

Q

R=0

S=0

1

1

0

0

t

Q

0

1

0

1

0

0

1

S

R

Q

t

a

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1t

0

1Q

0

Q may oscillate. Then, because one path will be

slightly longer than the other, Q will eventually

settle to 1 or 0 but we dont know which.

Known as a race condition.

a


Designer might try to avoid problem using external circuit

Circuit should prevent SR from ever being 11

But 11 can occur due to different ath dela s

1

0

1

0

Call

Cncl

Call S SR latch

Q

Call

button

External circuit

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Assume 1 ns delay per gate. The longer path from Call to

R than from Call to S causes SR=11 for short time

could be long enough to cause oscillation

1

0

1

0

S

R

SR = 11

2 ns

RCncl

Cancelbutton


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Glitch can also causeundesired set or reset

1

0Call

RCncl

Call S SR latch

Q

Callbutton

Cancelbutton

External circuit

1

0

1

0

Cncl

S

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Suppose this wire has 4 ns delay1

0R

SR = 01(undesiredglitch)

4 ns

Solution: Level-Sensitive SR Latch

Add enable input C

Only let S and R change when C=0 Ensure circuit in front of SR never sets

SR=11 exce t briefl due to ath dela s

S1S

Level-sensitive SR latch

,

Set C=1 after time for S and R to be stable

When C becomes 1, the stable S and R

value passes through the two AND gates tothe SR latchs S1 R1 inputs. R1R

Q

S

CQ

QR

Level-sensitive

S1S

Call

Level-sensitive SR latch

1

0

1

0

1

Call

Cncl

S

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SR latch symbol

a

R1Cncl

CClk

R

Q

Glitch on R (or S)doesnt affect R1 (or(S1)

0

1

0

1

S1

R1

Correctvalues when

enabled

0

1

0R

1

0C


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Level-Sensitive D Latch

SR latch requires careful design toensure SR=11 never occurs

S1D

D latchS

burden

Inserted inverter ensures R alwaysopposite of S

D Q

R1

Q

R

1

0D

C1

a

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QC

D latch symbolS1

R1

Q

0

1

0

1

0

1

0

a

Problem with Level-Sensitive D Latch

D latch still has problem (as does SR latch)

When C=1, through how many latches will a signal travel?

De ends on how lon C=1

Clk_A signal may travel through multiple latches

Clk_B signal may travel through fewer latches

D1 Q1 D2 Q2 D3 Q3 D4 Q4Y1 1? 1? 1?

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C4C3C2C1

Clk

Clk_A Clk_B


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Problem with Level-Sensitive D Latch

S2D2

D latch

S1D1

D latch

0>1 0>1

0>1

0>1

R2

2

Q2

D4

C4

Q4

R1

C1

Clk

Q1

1>01>00>1

(a)

D3

C3

Q3

Clk

D1

Clk

D1

Short clockLong clock

0>1

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(b)

Q1/D2

S2

R2

Q2 2nd latch set

(c)

Q1/D2

S2

R2

Q2

Q1 doesn't change a

a

D Flip-Flop

Flip-flop: Bit storage that stores on clock edge

One design master-servant =

Can we design bit

storage that only

stores a value on

the risin ed e of a , , .Servant disabled.

Clk = 1 Master disabled, Qm stays same. Servant

latch enabled, loads Qm, appears at Qs. Thus, value at D (and hence at Qm) when Clk

changes from 0 to 1 gets stored into servant

Clk

rising edges

D latch D latch

D flip-flopClk

D/Dm

a

clock signal?

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Note:Hundreds

of different

flip-flopdesigns

exist

master servant

DDm Ds

Cs

Qm Qs

QsQ

Q

Cm

Clk

Qm/Ds

Cm

Cs

Qs


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D Flip-Flop

Solves problem of not knowing through how many latches a signaltravels when C=1

In figure below, signal travels through exactly one flip-flop, for Clk_A orClk B_

Why? Because on rising edgeof Clk, all four flip-flops are loadedsimultaneously then all four no longer pay attention to their input, until thenext rising edge. Doesnt matter how long Clk is 1.

Two latches insideeach flip-flop

D1 Q1 D2 Q2 D3 Q3 D4 Q4Y1 1

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Clk

Clk_A Clk_B

D Flip-Flop

D Q

Q

QD

Q

Symbol for rising-edge Symbol for falling-edge

Internal design: Justinvert servant clockrather than master

The trianglemeans edge-triggered clockinput

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triggered D flip-flop triggered D flip-flop

Clk

rising edges

Clk

falling edges


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D Latch vs. D Flip-Flop

Latch is level-sensitive Stores D when C=1

Fli -flo is ed e tri ered Stores D when C changes from 0 to 1

Saying level-sensitive latch or edge-triggered flip-flop isredundant

Comparing behavior of latch and flip-flop:

Clk 1 2

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D

Q (D latch)

Q (D flip-flop) 10

87

654

9

3

Latch follows D

while Clk is 1

Flip-flop only loads D

during Clk rising edge

a

Clock Signal

Flip-flop Clk inputs typically connect to one clock signal

Coming from an oscillator component Osc.Clk

enera es per o c pu s ng s g na

Below: "Period" = 20 ns, "Frequency" = 1/20 ns = 50 MHz

"Cycle" is duration of 1 period (20 ns); below shows 3.5 cycles

0 nsTime:

Clk

10 ns 20 ns 30 ns 40 ns

000

0

1

0111

50 ns 60 ns

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Period/Freq shortcut: Remember 1 ns 1 GHz

100 GHz

10 GHz

1 GHz

100 MHz

10 MHz

0.01 ns

0.1 ns

1 ns

10 ns

100 ns

PeriodFreq.


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Flight-Attendant Call Button Using D Flip-Flop

D flip-flop will store bit

Inputs are Call, Cancel, and present valueof D flip-flop, Q

D Q

QClk

Call

button

Cancel

button

Blue

lightComb.

Circuit

Call

Cncl

D

Truth table shown below

Preserve value: ifQ=0, make D=0; ifQ=1, make D=1

Cancel -- makeD=0 D Q

Call

button BlueCall

a

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Call -- make D=1

Lets give priorityto Call -- makeD=1

Circuit derived from truth table,using Chapter 2 combinational

logic design process

QClk

Cancelbutton

Cancel

Q

Bit Storage Summary

S1D

C

D latch D flip-flop

D latch D latch

Dm Qm DsD

QsQ

S1S

C

Level-sensitive SR latchS (set)

SR latchS

R1

Q master servant

Cm

Clk

Cs Qs

R1

QR

R (reset)

Q

Feature: S=1

sets Q to 1, R=1resets Q to 0.Problem:

SR=11 yieldsundefined Q,

Feature: S and R only

have effect when C=1.An external circuit canprevent SR=11 when

C=1.Problem:avoiding

Feature: SR cant be 11.

Problem:C=1 for too longwill propagate new valuesthrough too many latches;

for too short may notresult in the bit being

Feature: Only loads D value

present at rising clock edge,so values can't propagate toother flip-flops during same

clock cycle. Tradeoff:usesmore gates internally, and

R

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We considered increasingly better bit storage until we arrived at therobust D flip-flop bit storage

other glitchesmay set/reset

inadvertently.

SR=11 can be a burden. stored. requires more external gatesthan SRbut transistors today

are more plentiful and cheaper.


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Basic Register

Typically, we store multi-bit items e.g., storing a 4-bit binary number

Re ister: multi le fli -flo s sharin clock si nal From this point, well use registers for bit storage

No need to think of latches or flip-flops

But now you know whats inside a register

DDDD

I2I3 I1 I0

4-bit register

I3 I2 I1 I0

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Q2Q3 Q1 Q0

clk Q3 Q2 Q1 Q0

reg

Example Using Registers: Temperature Display

Temperature history display

Sensor outputs temperature as 5-bit binary number

Timer pulses C every hour

,

a4x4

x3

x2

a3a2 a1 a0

Display

Present

b4 b3 b2 b1 b0

Display

1 hour ago

c4 c3 c2 c1 c0

Display

2 hours ago

18

21

24

a

Temperature

sensor

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x1

x0

Ctimer

empera ure s ory orage


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Example Using Registers: Temperature Display

Use three 5-bit registers

a4 a3 a2 a1 a0 b4 b3 b2 b1 b0 c4 c3 c2 c1 c0

15 18 20 21 21 22 24 24 24 25 25 26 26 26 27 27 27 27x4...x0

Q4

C

x4

x3

x2

x1

x0

Q3

Q2

Q1

Q0

Ra Rb

I4

I3

I2

I1

I0

Q4

Q3

Q2

Q1

Q0

I4

I3

I2

I1

I0

Rc

Q4

Q3

Q2

Q1

Q0

I4

I3

I2

I1

I0

TemperatureHistoryStorage

18

21

a

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0

0

0

18

0

0

21

18

0

24

21

18

25

24

21

26

25

24

27

26

25

C

Ra

Rb

Rc

a

Note that registers

only loaded on rising

clock edges

Finite-State Machines (FSMs) and Controllers

Want sequential circuit withparticular behavior over time

Exam le: Laser timer

3.3

Controller

x

b

clk

laser

Pushing button causes x=1 forexactly 3 clock cycles

Precisely-timed laser pulse How? Lets try three flip-flops

b=1 gets stored in first D flip-flop

Then 2nd flip-flop on next-

patient

D Q D Q D Q

clk

b

1

0

0

a

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,next

OR the three flip-flop outputs,so x should be 1 for threecycles

1

Bad job what if button

pressed a second time during

those 3 cycles?

a


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Need a Better Way to Design Sequential Circuits

Also bad because of ad hoc design process

How create other sequential circuits?

Need

A way to capturedesired sequential behavior

A way to convertsuch behavior to a sequential circuit

Step Description

Step 1:

Capturebehavior

Capture thefunction

Create a truth table or equations, whichever is

most natural for the given problem, to describe

the desired behavior of each output of the

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25

combinational logic.

2A: Create

equations

This substep is only necessary if you captured thefunction using a truth table instead of equations. Createan equation for each output by ORing all the mintermsfor that output. Simplify the equations if desired.

2B: Implement

as a gate-based circuit

For each output, create a circuit correspondingto the outputs equation. (Sharing gates among

multiple outputs is OK optionally.)

Step 2:

Convertto circuit

Like we had for

designingcombinational

circuits

Capturing Sequential Circuit Behavior as FSM

Finite-State Machine (FSM)

Describes desired behavior ofsequential circuit

Outputs: x

HiLo

x=0 x=1clk^

Akin to Boolean equations forcombinational behavior

List states, and transitions

among states Example: Toggle x every clock

cycle

Two states: Lo (x=0), and Hi(x=1)

Lo Hi Lo Hi Lo Hi Lo Hi

cycle 1 cycle 2 cycle 3 cycle 4clk

clk^

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,Lo, on rising clock edge (clk^)

Arrow points to initial state(when circuit first starts)

Lo LoHi Histate

x

Outputs:

aLo Hi

Lo Hi

or

Depicting multi-

bit or other info

in a timing

diagram


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FSM Example: Three Cycles High System

Want 0, 1, 1, 1, 0, 1, 1, 1, ...

For one clock cycle each Outputs: x

Capture as FSM

Four states: 0, first 1, second1, third 1

Transition on rising clockedge to next state

clk

On1Off On2 On3

clk^

clk^

clk^x=1x=1x=0 x=1clk^

a

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Off OffOn1On1On2 On2On3 On3Off

x

State

Outputs:

a

Three-Cycles High System with Button Input

Four states

Wait in Off while b is 0* ^

Inputs:b Outputs:x

Off

clk^x=0

b'*clk^

When b is 1 (b*clk^),

transition to On1 Sets x=1

Next two clock edges,transition to On2, then On3

clk

On2On1 On3

clk^ x=1x=1x=1 clk^b*clk^

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button pressed

Off OffOn1Off Off Off On2On3OffState

Outputs:

Inputs:

x

b


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FSM Simplification: Rising Clock Edges Implicit

Every edge ANDed with risingclock edge

Off

x=0

b

clk^

*clk^

Inputs: b; Outputs: x

withouta rising edge

We dont consider suchasynchronous FSMs lesscommon, and advanced topic

Only consider synchronousFSMs rising edge on everytransition

x=0


On2On1 On3

x=1x=1x=1 clk^^clk*clk^b

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Note: Transition with no associated conditionthus transistions to next state on next clock cycle On2On1 On3

x=1x=1x=1b

a

FSM Definition

FSM consists of Set of states

Ex: {Off, On1, On2, On3}


Off

x=0

b

Set of inputs, set of outputs

Ex: Inputs: {b}, Outputs: {x}

Initial state Ex: Off

Set of transitions

Each with condition

Describes next states

On2On1 On3

x=1x=1x=1b

We often draw FSM graphically,known as state diagram

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x: as rans ons

Set of actions

Sets outputs in each state

Ex: x=0, x=1, x=1, and x=1

Can also use table (state table), ortextual languages


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FSM Example: Secure Car Key

Many new car keys includetiny computer chip

en ey turne , car s computer(under engine hood) requestsidentifier from key

Key transmits identifier

Else, computer doesnt start car

FSM

Wait until com uter re uests ID K1 K2 K3 K4

Wait

r=0

Inputs: a; Outputs: r

aa

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(a=1)

Transmit ID (in this case, 1 1 0 1)r=1 r=1 r=0 r=1

FSM Example: Secure Car Key (cont.)

Nice feature of FSM

Can evaluate output behaviorfor different input sequence

Wait

r=0

Inputs:a;Outputs: r

aa

Timing diagrams show statesand output values for different

input waveforms

K1 K2 K3 K4

r=1 r=1 r=0 r=1

clk

Inputs

a

clk

Inputsa

Q: Determine states and r value forgiven input waveform:

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Wait Wait K1 K2 K3 K4 Wait Wait

Outputs

State

r

Wait Wait K1 K2 K3 K4 Wait

Output

State

r

K1

a


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Ex: Earlier Flight-Attendant Call Button

Previously built using SR latch,then D flip-flop

Bit

Storage


Cancel

behavior using FSM instead

Clear and precise description ofdesired behavior

Well later convert to a circuit

u on

Inputs: Call, Cncl Outputs: L

L=0 L=1Call

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LightOnLightOff

Cncl*Call'

Call'(Cncl*Call')'

How To Capture Desired Behavior as FSM

List states

,

Optionally add some transitions if they help

Create transitions For each state, define all possible transitions leaving that state.

Refine the FSM

Execute the FSM mentally and make any needed improvements.

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FSM Capture Example: Code Detector

Unlock door (u=1) onlywhen buttons pressedin sequence:

Start

Red

Green

s

rg

b

Doorlock

u

Codedetector

1

, , ,green, red

Input from each button:s, r, g, b Also, output a

indicates that somecolored buttonpressed

Ca ture as FSM

Bluea

a

Inputs:s,r,g,b,aOutputs:u

Wait

s'u=0 s

Wait for start button

Start Wait for first coloredbutton

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List states Some transitions

included ab ag arRed1

u=0

Blue

u=0

Green

u=0

Red2

u=1

aru=0

a


Capture as FSM

List states

Create transitions

Start

Red

Green

s

rg

Doorlock

u

Codedetectora

Bluea

Wait

Start

s'

a'

ar'u=0 s


a

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Red1 Red2GreenBlueab ag ar

u=0

u=0ar

u=0 u=0 u=1


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Capture as FSM

List states

Create transitions

Start

Red

Green

s

rg

b

Doorlock

u

Codedetectora

states

Refine FSM Mentally execute

Works for normalsequence

Check unusual cases

All colored buttonspressed

Bluea

Wait

s' ar' ab' ag' ar'u=0

s


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Change conditions:other buttons NOTpressed also

Start

Red1 Red2GreenBlue

a'

a'

ab ag ar

a' a'u=0

u=0 ar

u=0 u=0 u=1


Start

Red

Green

s

rg

Doorlock

u

Codedetectora

Bluea

Wait

s'b'

g')'

')'

u=0 s


'

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Start

Red1 Red2GreenBlue

a'a

a(b

r'

a'

abr'g' agr'b' arb'g'

a' a'u=0

u=0arb'g'

u=0 u=0 u=1

a(

gr

'b')

a(

rb

'g')'


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Controller Design: Laser Timer Example

Step 1: Capture the FSM

Already done

x=0

b00

Offa


2-bit state register (for 4 states)

Input b, output x

Next state signals n1, n0

Step 2B: Encode the states

Any encoding with each stateuni ue will work

x=1 x=1 x=1

b

01 10 11On2On1 On3

Combinationallogic

n1

n0

xb

FSM

inputs

FSM

outputs

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41

a

State register

s1 s0

clk

Controller Design: Laser Timer Example (cont)

Step 2C: Fill in truth tablex=0

b00

Off


a

x=1 x=1 x=1b

01 10 11On2On1 On3

Combinationallogic

s1 s0

n1

n0

xbFSM

inputs FS

M

outputs

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State registerclk


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Step 2D: Implementcombinational logic Combinational

logicn1

n0

xbFSM

inputs FS

M

outputs

a

State register

s1 s0

clk

x = s1 + s0 (note that x=1 if s1=1 or s0=1)

n1 = s1s0b + s1s0b + s1s0b + s1s0b

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43

n1 = s1s0 + s1s0

n0 = s1s0b + s1s0b + s1s0b

n0 = s1s0b + s1s0


Step 2D: Implementcombinational logic (cont)

a

Combinationallogic

n1

xbFSM

inputs FS

M

outputs

Combinational Logicx

n1

b

State register

s1 s0

n0

clk

n0

s0s1

clk State register

Digital Design 2e

Copyright 2010

Frank Vahid

44

x = s1 + s0

n1 = s1s0 + s1s0

n0 = s1s0b + s1s0


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Understanding the Controllers Behavior

x=1 x=1 x=1b

01 10 11On2On1

Off

On3

00 b

x=0

x=1 x=1 x=1

b

01 10 11On2On1

Off

On3

00

x=0

x=1 x=1 x=1

x=0

b

b

01

00

10 11On2On1

Off

On3

b

s0s1

b x

n1

n0

0 0

0

00

00

0

0

00

000

clk

1

0

10

s0s1

b x

n1

n0

clk0 0

000

s0s1

b x

n1

n0

1

0

1

1

0

00

110

clk0 1

01

a

1

0

10

0

Digital Design 2e

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Frank Vahid

45

clk

Inputs:

Outputs:

b

x

state=00 state=00 state=01

Controller Example:Button Press Synchronizer

cycle1 cycle2 cycle3 cycle4clk

Inputs:

Want simple sequential circuit that converts button press tosin le c cle duration re ardless of len th of time that

Outputs:

bo

Button presssynchronizer

controller

bi bo

Digital Design 2e

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Frank Vahid

46

button was actually pressed

We assumed such an ideal button press signal in earlier example,like the button in the laser timer controller


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Controller Example:

Button Press Synchronizer (cont)

bibi

bi

bi

FSM inputs: bi; FSM outputs: bo

Step 2A: Set up architectureCombinational

logic

n0

n1

bobi

FSM

inputs

FSM

outputs

A

B

s1

0

0

0

s0

0

0

1

bi

0

1

0

Inputs

n1

0

0

0

n0

0

1

0

bo

0

0

1

Outputs

Combinational logic

a

Step 1: Capture FSM

bo=1bo=0 bo=0bibi

bi

bi

FSM inputs: bi; FSM outputs: bo

bo

bi

n1

n0

Combinational logic

=n0 = s1s0bibo = s1s0bi + s1s0bi = s1s0

s1 s0

clkState register

Digital Design 2e

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47

C

1

1

1

1

0

0

1

1

0

1

0

1

0

1

0

0

0

0

0

0

0

0

0

0unused

Step 2C: Fill in truth table

Step 2B: Encode states

00 01 10

bo=1bo=0 bo=0

bibi

bi

Step 2D: Implementcombinational logic

clkState register

s1 s0

Controller Example: Sequence Generator Want generate sequence 0001, 0011, 1100, 1000, (repeat)

Each value for one clock cycle

Common, e.g., to create pattern in 4 lights, or control magnets of a stepper motor

Inputs: none; Outputs: w,x,y,zInputs: none; Outputs: w,x,y,zwx

00

01 10

11A

B

D

wxyz=0001 wxyz=1000

wxyz=0011 wxyz=1100

C

Step 2B: Encode states

w

x

Step 1: Create FSM

A

B

D

wxyz=0001 wxyz=1000

wxyz=0011 wxyz=1100

C

Step 2A: Set up architecture

Combinationallogic

n0s1 s0

n1

clkState register

yz

Digital Design 2e

Copyright 2010

Frank Vahid

48Step 2C: Fill in truth table

clkState register

y

z

n0s0s1

n1

Step 2D: Implement combinational logic

x = s1s0

y = s1s0z = s1

n1 = s1 xor s0n0 = s0

a


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Controller Example: Secure Car Key (from earlier example)

K1 K2 K3 K4

Wait

r=0

Inputs: a; Outputs: r

aa

ep1

a

r=1 r=1 r=0 r=1S

Combinationallogic

s2 s1 s0

n2

ra

n1n0

clk State register

Step2A

Inputs:a;Outputs: r

Digital Design 2e

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49

aa

r=0

r=1 r=1 r=0 r=1

000

001 010 011 100Step2B

Step 2C

Well omit Step 2D

Converting a Circuit to FSM (Reverse Engineering)

yx

What does thiscircuit do?

2D: Circuit to eqns

y=s1z = s1s0n1=(s1 xor s0)x

= *

a A

D

B

C

states

Step 1: FSM (get from table)

clkState register

z

n0

n1

s0s1

2C: Truth table Outputs:y, z

A

D

B

yz=01yz=00

yz=10yz=10

C

states

withoutputs

Inputs: x;Outputs:y, z

x

Digital Design 2e

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Frank Vahid

50

Work backwards

2B: (Un)encode states

Pick any state names you want

A

D

B

yz=00

yz=01

yz=10

yz=10

Cx

x

x

x

x

states with

outputs and

transitions

2A: Set up arch already done


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Reverse Engin. the D-flip-flop Flight Atten. Call Button

D Q

QClk

Callbutton

Cancelbutton

Bluelight

L

2C:

Truth

table

2D: Circuit to eqns

L = Q

D = Cncl'Q + Call (next state)

Dont let the wa the circuit is drawn

2B:

(Un)encode

states

2A: Set up

arch (nothing

Digital Design 2e

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Frank Vahid

51

confuse you; the combinational logic iseverything outside the register

Inputs: Call, Cncl Outputs: L

LightOnLightOff

L=0 L=1

Call'*Cncl

Call

Call'

Cncl'+CallStep 1: FSM

(get from table)

Common Mistakes when Capturing FSMs

Non-exclusive transitions Incomplete transitions

a

b

ab=11 next state?

a

what ifab=00?

ab

ab

a

Digital Design 2e

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52

a

ab

a

ab


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27

Verifying Correct Transition Properties

Can verify using Boolean algebra

Only one condition true: AND of each condition pair (fortransitions leaving a state) should equal 0 proves pair

a * ab= (a * a) * b= 0 * b

Answer:

can never simultaneously be true

One condition true: OR of all conditions of transitionsleaving a state) should equal 1 proves at least onecondition must be true

Examplea

a + ab= a*(1+b) + ab= a + ab + ab= a + (a+a)b= a + bFails! Might not

=

a= 0OK!

Digital Design 2e

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Frank Vahid

53

ab. ., ,

b=0)

Q: For shown transitions, prove whether:* Only one condition true (AND of each pair is always 0)* One condition true (OR of all transitions is always 1)

Verifying transition properties

Recall code detector FSM We fixed a problem with the

transition conditions

Waitsu=0 s

a

Do the transitions obey the tworequired transition properties?

Consider transitions of state

Start, and the only one trueproperty

Start

Red1 Red2GreenBlue

a

a

ab ag ar

a au=0

u=0ar

u=0 u=0 u=1

ar * a a * a(r+b+g) ar * a(r+b+g)

= (a*a)r = 0*r = (a*a)*(r+b+g) = 0*(r+b+g)= (a*a)*r*(r+b+g) = a*r*(r+b+g)

Intuitively: press red and bluebuttons at same time: conditionsar, and a(r+b+g) will both be

Digital Design 2e

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Frank Vahid

54

= = = arr +ar +arg

= 0 + arb+arg

= arb + arg

= ar(b+g)

Fails! Means that two of Startstransitions could be true

.taken?

Q: How to solve? a

A: ar should be arbg(likewise for ab, ag, ar)

Note: As evidence the pitfall is common,

we admit the mistake was not initially intentional.A reviewer of an earlier edition of the book caught it.


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Simplifying Notations

FSMs

a=0b=1c=0

a=0b=0c=1

output implicitlyassigned 0

Sequential circuits

Assume unconnectedclock inputs connectedto same external clock

clk a

a

b=1 b=0c=1

Digital Design 2e

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Frank Vahid

55

a

Mathematical Formalisms

Two formalisms to capture behavior thus far

Boolean equations for combinational circuit design

FSMs for se uential circuit desi n

Not necessary

But tremendously beneficial

Structured methodology

Correct circuits

Automated design, automated verification, many more advantages

Digital Design 2e

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Frank Vahid

56


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More on Flip-Flops and Controllers

Non-ideal flip-flop behavior

Cant change flip-flop input too close to clock edge

Setup time: time D must be stable beforeedge

clk

D

3.5

Else, stable value not present at internal latch

Hold time: time D must be held stable afteredge

Else, new value doesnt have time to loop aroundand stabilize in internal latch

Setup time violation

clk

D

setup time

SD

D latch

1

C

D

Digital Design 2e

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Leads to oscillation!

R

C

u

Q

Q

2

3 4

5 6

7

S

u

R

Q

Q

Metastability

Violating setup/hold time can lead to badsituation

Metastable state: Any flip-flop state otherthan stable 1 or 0

clk

D

setup timeviolation

Eventually settles to either, but we dont

know which

For internal circuits, we can make sure toobserve setup time

But what if input is from external(asynchronous) source, e.g., buttonpress?

Partial solution

Q

metastablestate

ai

Digital Design 2e

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58

Insert synchronizer flip-flop forasynchronous input

Special flip-flop with very small setup/holdtime

a

ai

synchronizer


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Metastability

Synchronizer flip-flop doesnt completely prevent metastability

But reduces probability of metastability in dozens/hundreds of internal flip-flops storing important values

-

First ff likely stable before next clock; second ff very unlikely to have setup timeviolated

Drawback: Change on input is delayed to internal flip-flops

By three clock cycles in below circuit

veryveryvery incredibly

Probability of flip-flop beingmetastable is:

Digital Design 2e

Copyright 2010

Frank Vahid

59

a

ai

synchronizers

Example of Reducing Metastability Probability

Recall earlier secure car key controller

Inputs: a; Outputs: r a

K1 K2 K3 K4

r=1 r=1 r=0 r=1

r=0 aa

Combinational

logic n2

ra

n1

FSM

inputs

outputs

D

flip-flopCombinational

logicn2

raOriginal

a

Adding synchronizer flip-flop reduces

metastability probability in state

register, at expense of 1 cycle delay

Digital Design 2e

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Frank Vahid

60

s2 s1 s0

n0

clkState register

s2 s1 s0

n0

clkState register

a


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Flip-Flop Set and Reset Inputs

Some flip-flops haveadditional reset/set inputs

S nchronous

D Q

QR

Q

AR

D

Q

Q

AS

ARD

Q

Synch. reset: Clears Q to 0 onnext clock edge

Synch. set: Sets Q to 1 on nextclock edge

Have priority over D input

Asynchronous

Asynch. reset: Clear Q to 0,

cycle 1 cycle 2 cycle 3 cycle 4clk

D

AR

Digital Design 2e

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61

independently of clock

Example timing diagram shown

Asynch. set: set Q to 1, indep. ofclock

Q

Initial State of a Controller

All our FSMs had initial state

But our sequential circuits did not

Can accom lish usin fli -flo s

Inputs: x; Outputs: b

Off

x=0

b

with reset/set inputs

Shown circuit initializes flip-flops to

01 Designer must ensure reset-

controller input is 1 during powerup of circuit

By electronic circuit design

On2On1 On3

x=1x=1x=1b

s1 s0

n0

n1

b xCombinational

logic

Digital Design 2e

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62

D Q Q

QR S

D

Q

clk

resetcontroller

Controller with reset to initial

state 01 (assuming state Off

was encoded as 01).


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Glitching

Glitch: Temporary values on outputs that appear soon afterinput changes, before stable new output values

Desi ner must determine whether litchin out uts mapose a problem If so, may consider adding flip-flops to outputs

Delays output by one clock cycle, but may be OK

Called registeredoutput

Combinationallogic

n1

xbD

flip-flop

xr

Digital Design 2e

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63

State register

s1 s0

n0

Laser timer controller with flip-

flop to prevent glitches on x from

unintentionally turning on laser

Glitching

Alternative registered output approach, avoid 1 cycle delay:

Add extra state register bit for each output

Connect out ut directl to its bit

No logic between state register flip-flop and output, hence no glitches

Combinationallogic

n1n0

xb

nx

x=0

b

b000

Off

Inputs:b Outputs:x

Digital Design 2e

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64

State register

x=1 x=1 x=1

011 101 111On2On1 On3

But, uses more flip-flops, plus more

logic to compute next state


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Product Profile: Pacemaker

Digital Design 2e

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65


Pacemaker

Controller

Timer

Osc

s

p

,Outputs: t, p

ResetTimer

Wait

t=1, p=0

t=0

sz

szt z

ra

rv lv

la

s

Digital Design 2e

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66

from 0.8s) t=0

Basic pacemaker


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Pacemaker right atrium Inputs: sa, za, sv, zv

Controller

ta za tv zv

sa

sv

pv

pa

rightventricle

leftventricle

left atrium, , ,

ResetTimerA

PaceA

WaitA

ta=1

pa=1

pv=1

svsa

sa*za

sa*za

PaceV

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67

TimerA TimerVResetTimerV

WaitV

tv=1

sv*zv

sv*zv

Atrioventricular

pacemaker

Chapter Summary

Sequential circuits

Have state

- -

Put several together to build register, which we used to store state

Defined FSM model to capture sequential behavior Using mathematical models Boolean equations for combinational

circuit, and FSMs for sequential circuits is important

Defined Capture/Convert process for sequential circuit

Digital Design 2e

Copyright 2010

Frank Vahid

68

Converted FSM to standard controller architecture

So now we know how to build the class of sequentialcircuits known as controllers

Ch03 Lecture Presentation

Documents

Transcript of Ch03 Lecture Presentation