CEO Based LICD Labwriteup

K. J. Somaiya College of Engineering, Mumbai-77Lab Manual: BE ETRX (Semester VIII)

Instructions to the student

Every student is expected to bring printout of write-up of his experiment tobe performed at the time of practical/tutorial session as per the time table

The student must take counter signature of the concerned faculty on thesame day during lab session for the verification of outcomes of theexperiments

The journal will content A4 size papers unless it is notified for particularsubject

The students can use separate blank A4 size papers if necessary whilewriting journal

Cover page of every experiment should be in standard format as attachedalong with lab manual

The contents of the journal will be as per the format given Students are expected to follow the instructions given by concerned faculty

from time to time

1Department of Electronics Engineering

LICD/July.-Oct13

K. J. Somaiya College of Engineering, Mumbai-77CONTENTS

Sr.No.

Name of the Experiment PageNo.

Date ofperformance

Date ofSubmission /Correction

Remarks

This to certify that Bro./Sis. _______________________________ ______________

Roll No. ______________Exam.No._______________Class____________________

Div._________ Batch No.__________ has completed the specified term work in

subject of ____________________________________in satisfactory manner inside the

college of Engineering as laid by the University of Mumbai during the academic year

Jul. / Jan.20___ to Nov./Apr.20___

Overall Grade: Grade: AA / AB / BB / BC / CC

Staff member In-charge Head of the Department Principal

Department: Electronics Engineering Branch: Electronics Engineering


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K. J. Somaiya College of Engineering, Mumbai-77July – October Year 2013

Department of Electronics Engineering

Name of lab :LICD LAB

Subject: LICD

Semester: V

List of Experiments

1. To study Inverting and Non-inverting Amplifier using op-amp.2. Design of Schmit trigger with UTP & LTP values.3. Study of Astable multivibrator using IC-741.4. Design of multiple feedback filter using IC-741.5. Design R/2R ladder 4 bit D/A converter using IC 7416. Study of Astable multivibrator and Monostable multivibrator using IC555.7. Study of IC-8038 as waveform generator.8. Software:

a)Design frequency response of Integrator/Differentiatorb)Design Precision Full Wave Rectifierc)Design Peak Detectord)Design Instrumentation Amplifier.

Additional Experiments (Not truly beyond syllabus) which students should do asan assignment

(a) Study of regulator IC-723(b) Application of IC-565(c) Flash type A/D converter(d) Application of filters

Any other experiment students may come forward, try out and show as demonstration to other batches

Subject In-charge: Names of concerned Faculty:

Prof.M.S.Marathe Prof.S.Halbe 1) Prof. .M.S.Marathe Prof.A.Y.Naiksatam 2) Prof. S.Halbe

3) Prof.A.Y.Naiksatam 4) Prof.Megha Sharma


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K. J. Somaiya College of Engineering, Mumbai-77


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Experiment / assignment / tutorial No._______

Grade: AA / AB / BB / BC / CC / CD /DD

Signature of the Staff In-charge with date


Batch: Roll No.: Experiment No.:

Title: To study Inverting and Non-inverting Amplifier using opamp 741.

______________________________________________________________________Aim and Objectives of the Experiment..--Aim:- To study Inverting and Non-inverting Amplifier using opamp 741

Objectives: To study the inverting, and non-inverting mode of operation, find the maximum inputvoltage swing, and observe effect of loading._____________________________________________________________________CEOs to be achieved:CEO1,CEO3,CEO4Theory:The op amp used is high performance monolithic one constructedusing the fair child planar epitaxial process. It is intended for widerange of analog applications. High common mode voltage &absence of latch up tendencies make 741 ideal for use as avoltage follower.Important features are:1. No frequency compensation required2. No short circuit protection3. Offset voltage nullifying capability4. No latch up problem5. Large common mode & differential gain______________________________________________________________________Stepwise-Procedure:1) Connect the circuit for Inverting configuration.2) Apply sine wave i/p of 1Vp-p,1KHz and measure o/pVoltage and draw the waveforms.3) Increase input voltage from zero to maximum such that output goesin to saturation. Measure Voh and Vol and draw transfer characteristic.

4) Apply 3V or 4V D.C. with 500_ and 1K_ in series with to the inputand measure output. comment on the input attenuation.5) Repeat steps 2 to 4 for Non Inverting Amplifier


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Circuit Diagram:

observation Table:

Sr. No. Vin Output1. D.C

2. A.C.sine wave 1 Vp-p 1KHz

3. Find out maximum peak to peak voltage (Vin) such that no clipping is observed.Increase input voltage to


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K. J. Somaiya College of Engineering, Mumbai-77observe clipping and measure VoH and VoL

4. Apply sine wave 1 vp-p with500_ and 1K_ in series with it andmeasure output.

Conclusion:

1) Comment about phase of output w.r.t. input and transfer characteristic of opamp.

2) comment on the input attenuation in both type of amplifiers


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Date: _____________ Signature of faculty in-charge


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Title: Design a Schmitt Trigger (Inverting) with UTP & LTP values.

______________________________________________________________________Aim and Objectives of the Experiment..--Aim :- To Design and study the working of Schmitt Trigger using op-amp IC 741.

Objectives: To observe the hysterisis of schmitt trigger _____________________________________________________________________CEOs to be achieved:CEO1,CEO3,CEO4Theory:The class of Comparators which use the positive (regenerative) feedback is called as Schmitt Trigger or Regenerative comparators.The Schmitt trigger circuit is as shown above .The resistance divider formed byR1 & R2, connected between the output and the non-inverting terminal ofthe op amp, introduces positive feedback. This Schmitt trigger circuit is basically an inverting comparator with positive or regenerative feedback introduced. Thus it is called as regenerative comparator. Note that the sine wave has been applied as the inputvoltage to the inverting input.Design:-1) For UTP and LTP = 4 V.

2) For UTP = 4V. and LTP = 2 V.


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K. J. Somaiya College of Engineering, Mumbai-773) For UTP = 4V. and LTP = 0 V.

Stepwise-Procedure:1. Connect the circuit as shown in the fig 1) and 2) with proper resistances used.2. Observe the waveforms at the i/p and o/p terminal.3. Verify observed and theoretical values.4. Change the Peak–Peak value of Vi from 10V. to 12V. and to 3V. and observe Vo.5. Also observe the hysterisis of the ckt keeping CRO in X-Y mode.

6. Observe Vo waveform If we reduce the value of R2 = 0.Circuit Diagram:

observation Table:


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K. J. Somaiya College of Engineering, Mumbai-771) For UTP and LTP = 4 V.

Sr.No. Vi Theoretical values Practical Values

1. 10V

2. 12V

3. 3V

2) For UTP =4V and LTP = 2 V.


1. 10V2. 12V3. 3V

3) For UTP =4V and LTP = 0V.


1. 10V2. 12V3. 3V

Draw i/p and o/p waveforms as observed on CRO for both thecircuits with scale. Use graph paper. Comment and draw if necessary for points 4, 5and6 in procedure.

Conclusion:


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Title: Design of Astable Multivibrator using IC 741

______________________________________________________________________Aim and Objectives of the Experiment..--Aim :- To Design and study the square wave generator.

Objective:- Understand the working of Astable multivibrator and study the designing of the same.____________________________________________________________________

CEOs to be achieved:CEO1,CEO3,CEO4

Theory:The circuit of an Astable Multivibrator is shown. It is called as free running or square wave generator. The output of this circuit will be at +Vsat or -Vsat depending upon whether the differential voltage is positive or negative respectively. To explain the operation, we can see that the capacitor voltage of inverting terminal is zero at start. Assume Vo = Vsat. Then Vp = _Vsat where _= R1/(R1+R2) (feedback factor).Now Vn = 0V and Vp = + _Vsat So Vo will be + Vsat. (Our assumption is true). . Withthe output voltage at +Vsat, the capacitor start charging through R from 0V to +Vsat. The voltage across the capacitor start increasing and Vo remains same till capacitor voltage is less than _Vsat, Once this voltage is crossed _Vsat the output voltage swings to –Vsat and now the capacitor charges in opposite direction towards –Vsat. Again when Vc falls below –Vsat value, the op-amp goes to positive saturation. The time period of the output waveform is given by T=2RC ln [(1+ _)/(1-_)]. If we substitute value of _ then equation becomes T=2RC ln [1+ (2R1/R2)].

Design:- Design Astable MV using opamp 741IC with following parameters: Frequency- between 200 Hz to 1 KHz. Vcc and Vee = +& - 12 V,Vop-p = 2.Vsat.

Circuit Diagram:


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____________________________________________________________________Stepwise-Procedure:

1-Connect the circuit as shown in diagram.2- Switch on the power supply.3-Observe the o/p waveforms on CRO and measure frequency.4-Connect 2 capacitors in series and then in parallel and Observe theo/p waveforms on CRO and measure frequency.5-Change the value of R and Observe the o/p waveforms on CRO andmeasure frequency .6-Now change the ratio of R1/R2 to half and observe the o/p waveformson CRO and measure frequency.7-Compare all the results with the theoretical values

observation Table:

Sr. No. Description of circuit connection

Observed value Theoretical value

1. With designed R , C2. 2 Cs in series3. 2Cs in parallel4. R varied to Rmin5. R varied to Rmax6. R1/R2 changed to

Conclusion


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Title: Design of multiple feedback filters

Aim and Objectives of the Experiment..--Aim :- To design multiple feedback filter.

Objectives: study the design multiple feedback filter and utilize the open-loop gain._____________________________________________________________________CEOs to be achieved:CEO1,CEO3,CEO4

The multiple feedback filter utilizes more than on e feedback path and exploits the full-open-loop gain.

Multiple feedback topology is an electronic filter topology which is used to implement an electronic filter by adding two poles to the transfer function.


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https://en.wikipedia.org/wiki/Transfer_function


Circuit Diagram:

Stepwise-Procedure:1.Connect the circuit as shown in the diagram.

2.Apply sine wave i/p from 100Hz to 50KHz and measure o/p voltage

3.Calculate gain in dB and plot graph of gain v/s frequency semi log paper.

Observation Table:

For Low-pass filter:

Sr. No.

frequency Measured value(v) Gain (Av)


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For high pass filter :

Sr. No.

frequency Measured value(v) Gain (Av)


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K. J. Somaiya College of Engineering, Mumbai-77Calculation:

Conclusion :



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Title: Study of R-2R ladder type DAC

______________________________________________________________________Aim and Objectives of the Experiment..--Aim :- To study R-2R ladder type DAC.

Objectives: to study application op-amp for digital to analog conversion._____________________________________________________________________CEOs to be achieved:CEO1,CEO3,CEO4

The weighted resistor type DAC not only requires wide range of resistor values but alsoit’s value of largest resistor is 128 times the R of the circuit ; and thus to avoid this problem basically R-2R LADDER type DAC is preffered. The R-2R network can be analysed by using the thevenin’s theorem by obtaining output voltage corresponding to each digital input d1,d2,d3,d4 seperately and add them to get the final voltage Vo.The expression for the output voltage is

Vo= VR [ d12-1 + d22-2 + d32-3 + ..…+ dn2-n ]

Circuit Diagram:

Stepwise-Procedure:


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1) Connect the circuit as shown in the diagram.2) Apply the digital inputs to the respective 4 bit inputs. 3)Measure the analog output voltage and compare with the theoretical values obtained by calculation.

observation Table:

Sr. No. Digitak i/p code Measured value(v) Calculated value(v)

Conclusion :


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Calculation:



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Title: Study of Astable multivibrator and monostable multivibrator using IC-555.

______________________________________________________________________Aim and Objectives of the Experiment..--Aim: - To study Astable and monostable Multivirator using IC 555.

Objectives: study application of monostable multivibrator.

___________________________________________________________________

CEOs to be achieved: CEO2,CEO3,CEO4

Theory:Astable multivibrator is also called free running oscillator, this circuit does not require any triggering signal to change its output state.Initially when the supply is switched on, the voltage across the capacitor will be zero which will be compared with the 2/3 rd Vcc in the upper comparartor and 1/3rd Vcc in the lower comparator which makes flip flop to set making output Q to go high and Q* to go low. Through inverter the finaloutput goes high. so the transistor Q1 will remain off and the capacitor starts charging through Ra, Rb towards Vcc. When the voltage across the capacitor becomes slightly more than 2/3rd Vcc, the upper comparator output goes high and lower comparator output goes low. Flip flop resets making Q =0 and Q* =1. through inverter final output goes low and transistor Q1 turns ON. The capacitor now starts discharging , when its voltage becomes slightly less than 1/3rd Vcc, the final output goes high again. The cycle repeats producing a rectangular wave at the final output.The equation for the timeperiod is:

Ton= 0.69[(Ra + Rb)* c]

Toff= 0.69 Rb* c

Total time period,

T= 0.69(Ra + 2 Rb) *c.

The frequency of oscillation,

F= 1/T.


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K. J. Somaiya College of Engineering, Mumbai-77The duty cycle is ,

D= Ton / T

Design Procedure:

For a given value of frequency and duty cycle the circuit can be designed as follows;

1. Assume the value of capacitor for a specified design.

2. The resistors value can be decided by formula below:

Rb = 1.4(D – 1) / FC

Ra = Rb (2D – 1) / (1 – D)

Where , D = given duty cycle, F = given frequency.

A Monostable Multivibrator, often called a one-shot Multivibrator, is a Pulse-generating circuit in which the duration of the pulse is determined by the RC network connected externally to the 555 timer. In a stable or standby state the output of the circuit is approximately zero or at logic-low level. When an external trigger pulse is applied, the output is forced to go High (= Vcc). The time the output remains high is determined by the External RC n/w connected to the timer.The Monostable circuit has only one stable state (output low), hence the name Monostable.Figure shows internal block diagram of 555 configured for Monostable Operation. According to figure, initially when the output is low, i.e. the Circuit is in stable state, transistor Q1 is ON and capacitor C is shorted to ground. However, upon application of a negative going trigger pulse to pin2 of amplitude greater than 1/3Vcc comparator 2’s o/p switches from high to low, sets the flip flop, which in turn drives the o/p to its high state, This turns Transistor Q1 OFF, which releases the short circuit across the External capacitor C and drives the o/p high. The capacitor C now charges towards Vcc through R. However, when the voltage across the capacitor equals 2/3 Vcc, comparator 1’s o/p switches from low to high, resets the flip flop, which in turn drives the o/p to its low state The o/p of the flip flop turns transistor Q1 ON, and hence capacitor Crapidly discharges through the transistor. The output of the Monostable remains low until a trigger pulse is again applied. Then the cycle repeats.

The graph shows the trigger i/p, output voltage and capacitor voltageWaveforms.

T = 1.1* R*C


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K. J. Somaiya College of Engineering, Mumbai-77Design procedure :

For a given value of the time period , the resistance value can be calculated from above equation of time period . The capacitance value can be assumed for a specific time period

_____________________________________________________________________Stepwise-Procedure:1.Connect the circuit as shown in the fig.

2.Adjust the pot values as per the design.

3.Observe the waveforms at the o/p terminal and across the capacitor.

4Verify observed and theoretical values.

Circuit Diagram:


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K. J. Somaiya College of Engineering, Mumbai-77Observation Table:

a) Astable multivbrator

Parameter Observed values Calculated values

b)Monostable multivibrator

Parameter Observed values Calculated values

Conclusion


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Title: Study IC 8038 function generator.

______________________________________________________________________Aim and Objectives of the Experiment..--Aim: - To study IC 8038 function generator.

Objectives: study of function generator IC-8038

__________________________________________________________________

CEOs to be achieved: CEO2,CEO3,CEO4

Theory:The operation of IC 8038 function generator is based on linear charging anddischargingof capacitor as shown in functional diagram of IC8038.

There are two current sources, out of these one, sourcing current while otheris sinking the current. These current sources alternately charge an discharge an external capacitor. When current source ‘I’ drives volt above (capacitor) +ve reference volt level,comparator1 flips the F/F. This in turn switches the current source2. Current source2 discharges the capacitor at same rate as it was charged when triangular wave falls below the –ve reference level, the other comparator flips the F/F. Current source2 is switched out & current source1 begins charging up capacitor again. The volt across external capacitor is buffered and becomes triangular wave output. The o/p of F/F is buffered and becomes square wave Both triangular and square wave outputs are buffered so that output impedance of each is 200ohms. However the sine wave output is obtained by giving triangular o/p to sine shaper but it has relatively high output impedance of 1kohm. From this sine wave is often fed to a separate non-inverting amplifier that provides buffering gain & amplitude adjustments.

_____________________________________________________________________

Stepwise-Procedure:1.Give supply voltage of 10volts

2.Check the output at pin no. 2,3,9.

3.Check by varying pot of 100KΩ & 1KΩ which parameter of which waveform gets varied.


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K. J. Somaiya College of Engineering, Mumbai-774.Draw the waveform & measure the different parameters of waves as

per the absolute value.

Circuit Diagram:

Fig.2. NMOS amplifier with Depletion load

Conclusion


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LICD/July.-Oct13

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