August 24, 2004 Sam Siewert

CEC 450 Real-Time Systems

Lecture – Design Process and Methods

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Lifecycle, Platforms, and Revision Control

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Basic Lifecycle for an RT Embedded System

Concept Analysis: Functional Requirements, RT Requirements Planning: Schedule and Resources High Level Design (Transaction Level Model) Component and Subsystem Prototyping (HW Simulation) Unit Testing, Nightly Build, Nightly Regression Analysis: Risk Identification and Mitigation Re-planning: Re-schedule and Resource Adjustment Detailed Design (Verilog or VHDL, RTL) Component and Subsystem Implementation (Synthesis and Layout) System Integration, Bring-up, and Test (Verification) System Regression Testing (Hardware/Software Integration) Tuning and Maintenance

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Spiral Model for System Development

Project Proposal

Reference Projects

Analysis Design

Develop and Unit Test Regression Test

Project HLD

Tornado/Linux Platform and Project

Build

Unit/Component Prototypes Complete

Detailed Function Description

Detailed Design

All Services Complete

Final System Demonstration Write/review Define Services And interfaces

Code, Define, Test

CMVC, Build and Test

Write/review/finalize service functionality

Finalize Design

Finalize Code Modules and Unit Tests

System Integration, Bring-up, and Tuning

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Spiral Model Schedule (15 Weeks)

Project Proposal

Reference Projects

Analysis Design

Develop and Unit Test Regression Test

Project HLD

Tornado/Linux Platform and Project

Build

Unit/Component Prototypes Evaluation

(Example Code)

Detailed Function Description

Detailed Design

All Services Complete

Final System Demonstration W1,2 W3,4

W5 W6

W7 W8

W9,10,11,12

W13,14,15

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Platform Setup Basic Microprocessor or SoC Software Platforms

– RTOS – RT Linux – Custom Executive

Firmware and Software Components

– BSP (Board Support Package) – Loader/Boot – Kernel – Drivers – Applications

For VxWorks Setup on PC x86 Hardware

– http://ece.colorado.edu/~pfefferz/vxworks/Notes_for_installing_Tornado_2.htm

General Scheme – Obtain Similar Evaluation Board, Same Architecture and Similar Peripherals as

Ultimate Hardware – Bring up RTOS, RT Linux or Executive on Evaluation Board – Bring up Same on Custom Hardware

http://ece.colorado.edu/%7Epfefferz/vxworks/Notes_for_installing_Tornado_2.htm

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Revision Control for Software Why Worry about this? – Maintain a building and working version of your code – Ability to roll back to previously working versions – Revision history

Open Source Options – CVS

http://www.nongnu.org/cvs/ http://www.tortoisecvs.org/download.shtml http://www.wincvs.org/

– Subversion http://subversion.tigris.org/ http://tortoisesvn.tigris.org/

http://www.nongnu.org/cvs/http://www.tortoisecvs.org/download.shtmlhttp://subversion.tigris.org/

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Design Methods

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System Engineering Approach System Composed of Sub-systems and Components – Mechanical (Robotics) – Analog Electrical – Digital Electrical – Firmware (Boot, Loaders, Operating System, Drivers) – Software (Applications and Real-Time Services) – Biological (E.g. Medical Systems such as a Blood Analyzer) – Chemical (E.g. Chemical Process Control) – Cryogenics (E.g. Infrared Instrumentation)

System Design View Subsystem and Component Design – Detailed Design

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High Level Design - Stereo Vision Example One Page System View – Hardware, Firmware, Software

Bt 878 Video Frame

Driver

Centroid Image

Processing

Stereo Range

Estimator

Servo Tilt / Pan

Controller

NCD 209 Servo

Controller

VxWorks X 86 CPU

Bt 878 Video

Encoder

Camera - 1

Pan Servo Tilt Servo

Mounting Plane

Camera - 2

PWM Position Signal

PWM Position Signal

Tilt / Pan Command

Bt 878 Video

Encoder

Camera - 1 Centroid

Pixel Address

X 86 Memory

Proces Frame 1 or 2

semaphore

Bt 878 Driver ISR

IRQ

Frame Ready 1 or 2

semaphore

Centroid Pixel Addresses - Camera - 1 & Camera - 2

Ethernet LAN

Video & Data

Streaming

Video Frames

Video Transport Messages

Debug Viewer

Video Stream Viewer

Ethernet Frames

Camera 1 & 2 PPM Frames , Range Data

NIC

Ethernet Frames

Video & Data

Streaming

TCP Segments

Windows ( TCP / IP )

TCP Segments

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Hardware Detailed Design - System System Block Diagrams – High level, Hardware Components, Interconnection and Protocols – Interconnection Physical/Link-Layer Protocols Shown

Mechanical Diagrams – Visio Mechanical Engineering Templates – Sub-Assemblies – Enclosures and board mounting, cooling, cabling – Actuators and Sensors – Structural

Electrical Schematics – Visio Electrical EngineeringTemplates – http://www.orcad.com/pspicead.aspx

CAD analog circuit diagrams (OrCAD) SPICE models (Simulation Program with Integrated Circuit Empahsis)

– Circuit Diagrams, Logic Design – State Machines & Logic Tables

EDA (Electronic Design Automation) Models – http://www.systemc.org/ – System Models (System-C, Verilog, VHDL) – Test Benches (C, C++)

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Stereo Vision HW Block Diagram Concentrates on HW Sub-systems and Cabling Only

NCD 209 Servo

Controller

VxWorks X 86 CPU

Bt 878 Video

Encoder

Camera - 1

Pan Servo Tilt Servo

Mounting Plane

Camera - 2

PWM Position Signal

PWM Position Signal

RS - 232 9600 Baud 8 N 1

Tilt / Pan Command

Bt 878 Video

Encoder

P C I 2 . 1 3 2 - b i t 3 3 M h Z B u s

Ethernet LAN

Windows PC Debug Viewer

10 / 100 Ethernet

Video Frame & Range Data

NTSC - 1

NTSC - 2

Etherlink III PCI NIC

RJ - 45 UTP 10 / 100

Ethernet

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Mechanical Diagrams Diagrams Show Mounting and Fastners Cut-Aways, Front, Side, Rear Views Rotation and Translation Major Physical Components Dimensions Shown as Applicable

Mounting Plane

Camera

T i l t

S e r

v o

Pan Servo

Camera

Side View Front View

Pan Servo Tilt Servo

Mounting Plane

Tilt Rotation Pan Rotation

Pan Rotation

Tilt Rotation

7 . 30 in .

6 . 00 in .

5 . 30 in .

4 . 40 in .

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Electrical Schematics Show Schematics for Each Board Show Board or Block Interconnections

NCD 209

5 V DC

8 MhZ Ceramic

Resonator

LED

Servo 1 Servo 2

220 Ohm 220 Ohm

PWM PWM

5 V DC RS - 232 From Cmd Tx

22 K Ohm

Servo Controller Board

RS 232 Commands

C - Cam 8

Bt 878 Frame Grabber NTSC Gnd

P C I 2

. 1

3 2 - b

i t 3 3

M h Z

LM 7805 VCC

100 µ F 0 . 1 µ F

6 - 12 V DC

C - Cam 8 Camera Board Connection to Frame Grabber Board

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Logic Blocks and Models Verilog, VHDL, System-C Logic Models Logic Block Diagrams, Schematics Where Applicable

32-bit ALU

64-bit Remainder

Divisor Numerator Quotient

Left shift

32-bit 32-bit 32-bit Initially Loaded In Lower 32 bits

Left shift Control Logic

REM Q

Final Output Upper 32 bits

Inputs

Outputs

J

K

Clk

JK Flip-Flop

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Software Detailed Design Real-Time Pipeline Data Flow and Timing UML Methods – Visio Add-on UML Templates

Dr. Pavel Hruby http://www.phruby.com/stencildownload.html

– Deployment, Component Diagrams – Static Class Diagrams – Sequence Diagrams or Collaboration Diagrams – Activity Diagrams or State Machines

Structured Analysis and Design Methods – Visio Flowchart & Software Category – System Data Flow – Entity Relationship Diagrams (Like a Class Diagram) – Flow Charts

Specification and Description Language – Visio Flowchart Category, SDL Diagram – Block Diagrams with Signal/Message Interfaces – Procedures and Tasks – State Machines

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Real-Time Service Pipeline Data Flow with Rates and Buffers Shows Services (Tasks) and Processing Pipelines Shows Rates and Sub-Rates in Each Pipeline Shows Intermediate Buffers if They Are Used

tBtvid (30 Hz)

Bt878 PCI NTSC decoder

(30 Hz) Serial

NCD209 PCI Ethernet

NIC

RGB Double Buffer

tFrameProc (10 Hz)

Grayscale buffer

tStream (2 Hz)

tNetTask (2 Hz)

tTracker (30 Hz) tTelemetry (1 Hz)

tPanTiltCtl (10 Hz)

Video Streaming

Telemetry Streaming

Tilt/Pan Control

SW

HW

Centroid tNetTask

(1 Hz)

TCP Buffer

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Deployment Diagram Shows Installation of Software Modules on HW

VxWorks - Target

Image - Processing

Target - Tracking

Video - Frame - Driver

Video - Streaming

Left - Frame - Grabbe

Right - Frame - Grabber

Left - Camer Right - Camera

Servo - Control - Board

Tilt - Pan - Servo - Assembly

Video - Stream - Monitor

- Monitor 1 ..*

- Source 1

- Cmd - Gen 1

- Cmd - Handler 1

- Control - Output

1 ..*

- Actuator

1 ..*

- Initiator 1 - Target

1 - Initiator

1

- Target

1

- Source 1

- Encoder 1

- Source

*

- Encoder

*

- Frame - Source 1 ..*

- Frame - Proc 1

- xy - location - gen * - xy - location - proc

*

- Frame - Source

*

- Frame - Packetizing *

Network - Transport

- Stream - Source 1 - Transporter 1 ..*

Local - Area - Network

- Stream - Termination *

- Stream - Packets *

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Class Diagrams Shows Classes, Operators, Data-Types, Methods

+ interrupt - handler ()

Frame - Event - ISR

+ frame - rdy - semgive ()

Frame - Sequencer

Frame - Grabber - Driver

+ start - frame - acquisition () + set - mux ()

Device - Initializer

- driven - by 1

- supports 1

- runs - prior - to - operation

1

- sets - up 1

- executes

1

- provides - frame - services - for 1

+ set - brightness () + set - processing - rate () + set - transport - rate () + start - driver () + shutdown - driver ()

Driver - Interface

- supplies 1

- enables - access - to 1

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Sequence Diagrams Shows Collaboration and Function-Call, Message Passing Sequences Between Objects Makes Message Passing or Calling Sequences Obvious Shows How Object Operations Are Used

Frame - Converter Edge - Enhancer Find - Centroid Frame - Buffer - Sequencer

convert - to - gs := convert - to - gs ( rgb - frame )

enhance - edges ()

find - center ()

Tracking - Control - Function

center - target ()

Frame - ISR

frame - rdy - semgive ()

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Activity Diagrams - State Machines Shows the Active States of an Object Shows Logic for State Transitions

Waiting - for - Frame - Rdy

Do - Frame - Processing Transporting

when : if ( FrameCnt % FrameProcRate == 0 )

when : if ( FrameCnt % FrameTransportRate == 0 )

Frame - Driver - Initializing

when : if ( FrameCnt > LastFrameCnt )

CEC 450�Real-Time SystemsLifecycle, Platforms, and Revision ControlBasic Lifecycle for an RT Embedded SystemSpiral Model for System DevelopmentSpiral Model Schedule (15 Weeks)Platform SetupRevision Control for SoftwareDesign MethodsSystem Engineering ApproachHigh Level Design - Stereo Vision Example Hardware Detailed Design - SystemStereo Vision HW Block DiagramMechanical DiagramsElectrical SchematicsLogic Blocks and ModelsSoftware Detailed DesignReal-Time Service PipelineDeployment DiagramClass DiagramsSequence DiagramsActivity Diagrams - State Machines