Jon MajorStephenson Institute for Renewable Energy

University of Liverpool

CdTe Solar Cells

Outline

• Why CdTe?

• CdTe cell structure

• Deposition

• Current research issues

• Industrial manufacture

Efficiency vs Eg for single band gap solar cell

AM 1.5300KSi

InP GaAsCdTe

Ge

CdS

• Max efficiency vs Eg is trade-off between current and voltage.

• Lower bandgap higher current – use more of the spectrum

• Higher bandgap higher voltage – Voc linked to Eg

• CdTe at ~1.5eV get best combined power

CdTe vs Si

• Si is intrinsically expensive due to purification costs- High purity – controlled doping- need thick wafers due to indirect gap of Si

• CdTe is a direct gap thin film compound semiconductor- 100 times more absorbing than Silicon- Can be used as a polycrystalline thin film

• Typically need >100µm of high purity crystalline Si but 1µm of CdTe will absorb >90% of above bandgap light.

• Cost of CdTe absorber layer is much lower cost than Si

Isn’t Cadmium dangerous?

+

=NaCl

Explodes in water!

Used in WWI!

SafetyCd environmental risk?

CdTe cell production contributes far less Cd to the atmosphere than fossil fuels or Si

Safety

V. Fthenakis et al, Progress in PV, 2004

• Tests up to 1100⁰C of small scale glass encapsulated modules

• ~99.5% Cd remained in module

• Loss was through ends of exposed ends of module

• In real world modules loss expected to be <0.04%

• Risk is very low

Current output

Glass superstrate

Transparent conductingoxide (~ 200nm)

CdS layer(~ 80nm - 400nm)

CdTe layer(~ 2 - 10µm)

Incident light

Back contact

Superstrate cell structure

TCOsRequirements

• Transparency > 85% over the visible range• Sheet resistance <10 Ω/□• Stable

In2O3:SnO2 (ITO)• Widely used in range of applications – PV to flexible

electronics.• Easy to achieve good electrical and optical properties.• Considered expensive due to reliance on In.

TCOsITO can be unsuitable if using high temperature CdTe deposition techniques.

In-diffusion into CdTe causes n-type doping!

• Cd2SnO4 (CTO) - gives best performance, <3 Ω/□ and transparency >90% - requires high temperatures >600⁰C.

• ZnO:A (ZAO) – Low cost, good performance – breaks down at temperatures >400⁰C.

TCOsSnO2:F (FTO)• FTO is the best compromise. • Deposited as an “on-line” coating during float glass manufacture.• Industrial choice• NSG ltd (Pilkington) “TEC” glass is commonly used.

CdS deposition routesChemical bath deposition (CBD)-Low temperature, oxygen rich small grained films.-Uses aqueous cadmium.

RF sputtering-Wide range of deposition control- Industrially scalable-Slow deposition rate

Close space sublimation (CSS)- High deposition rates- Requires higher temperature

deposition

CdS• n-type “window” layer – 2.4eV bandgap

• Typically 60-300nm thick

• Depletion region resides wholly within the CdTe – carriers generated in CdS recombine.

• Desirable to minimise CdS thickness to maximise Jsc - without compromising FF and Voc

Wavelength (nm)

400 500 600 700 800 900

Nor

mal

ised

EQE

0.0

0.2

0.4

0.6

0.8

1.0

1.2300nm CdS250nm CdS200nm CdS

J

V Increasing Rsh

Slope = 1/Rsh

b)

Too thin CdS will lead to voids and shunt related losses - Jsc may increase but FF will decrease.

CdS

CdTe

In severe cases where voids lead to TCO/CdTe interface regions VOC is also decreased

CdTe deposition routesClose space sublimation (CSS)- High deposition rates- Large grain size- Highest efficiency devices

RF sputtering- Low temperature deposition- Ultrathin CdTe- Low deposition rates

MOCVD- Allows elemental control and introduction of dopants i.e. As.- Low deposition rates

CdTe• CdTe thickness typically in 1-8μm range

• <1μm is desirable but difficult to achieve without performance loss

Paudel et al – Solar energy materials (2012)

• >8μm see losses due to Rs increase

CdCl2 “activation” step• CdCl2 activation is vital to high efficiency CdTe solar cells

• Typically converts a cell of <1% efficiency to >10%

• A thin layer (20-200nm) of CdCl2 is deposited on the CdTe free back surface

• Sample then annealed in a tube furnace under an air ambient

• Can also be done with MgCl2 as an alternative

Glass superstrate

Transparent conductingoxide (~ 200nm)

CdS layer(~ 80nm - 400nm)

CdTe layer(~ 2 - 10µm)

• It isn’t a single process and not fully understood- Grain boundary passivation- Grain growth and recrystallization- Intermixing of CdS and CdTe layers- p-type doping of CdTe layer: presumed to be via [VCd - ClTe] (A-centre)

What does the CdCl2 treatment do?

As-deposited CdCl2 treated

Low tempdeposition

High tempdeposition

Grain growth

CdTe

a

c

b

Spectrum image

Where does the chlorine go?

See little evidence of Cl at the interface with CdS Chlorine instead segregates at the

grain boundaries changing their electrical behaviour

Normalised Wd

0.0 0.2 0.4 0.6 0.8 1.0

NA

(cm-3

)

1e+13

1e+14

1e+15

1e+16

CdCl2 MgCl2 As-grown

Doping density

As-deposited ~1013cm-3

Chloride treated ~1015cm-3

As grown

Air anneal

CdCl2 treatment

Device performance

Front contact

Back contact

Glass superstrate

TCO/buffer layer

CdS window layer

CdTe layer

e-

e-

e-

Back wall EBIC

Front wall EBIC

Cross section EBIC

Gold back contact

Electron beam induced current (EBIC)

CdCl2 treatment forms the CdS/CdTe hetero-junction

Back contact

• Forming back contact to CdTe is problematic owing to the high electron affinity χS = 4.5eV

• For Ohmic contact require a work function of > 6eV – No such metal exists!

• May contact with high work function metals (e.g. Au ~5.1eV) but a barrier still exists.

Cu addition to the back contact• Solution to the contacting problem is the use of an interface layer between CdTe and metal.

• Typically done via formation of CuxTe layer at the back surface – decreases barrier width to allow tunnelling.

• Number of routes but typically- Etching CdTe in nitric/phosphoric (NP) acid etch to create Te-rich layer- Deposition of 1-10nm of Cu via thermal evaporation- Annealing at 100-250⁰C to diffuse in Cu

• Optimisation of Cu thickness and annealing is key

• See improvement in FF and Voc (if ɸb >0.5eV)

Stability of the back contact

• Alternative contacts are still being investigated.

• Sb2Te3, CdTe:As, ZnTe, MoOx, NiTe have all been demonstrated.

• Industrially Cu is still used but <2nm

• Cu is a fast diffuser in CdTe

• If it reaches the CdS layer - leads to photoconductivity and performance loss

• Leads to long term instability of performance

• High Voc and FF are more believable

• Jsc values are very sensitive to calibration or contact size errors.

• Contacts should be minimum of 0.25cm2

• If it looks to good to be true it usually is!

Etch time (s)

0 100 200 300 400 500 600

Effi

cien

cy (%

)

0

2

4

6

8

10

12

14

16

Etch time (s)

0 100 200 300 400 500 600

Fill

fact

or (%

)

10

20

30

40

50

60

Etch time (s)

0 100 200 300 400 500 600

Voc

(V)

0.45

0.50

0.55

0.60

0.65

0.70

Etch time (s)

0 100 200 300 400 500 600

J sc (m

A/c

m2 )

0

10

20

30

40

50

60

Contact errors

The CdTe VOC problem

CdTe single crystal cell Voc

1007mV

Theoretical limit ~1400mV.

CdTe polycrystalline cell today Voc - 876mV1992 - Max 855mV

A decade worth of cells from NREL (around 2500)

Why the VOC shortfall?

Carrier density in CdTe• Doping density of CdTe films limited to ~ 1015cm-3

• Due to strong self compensation of CdTe

• Limits Voc

Single crystal work with >1V

Carrier lifetime

• Voc linked to carrier lifetime in CdTe

• By improving lifetime Voc has surpassed previous assumed limit of ~855mV

• Achieved via formation of high quality MBE junctions

• Still someway short of 1.4V theoretical limit

CdTe grain boundaries

CdTe grain boundaries are highly complex as chemical composition will depend on deposition method, deposition conditions, post-growth treatment and contacting.

Boundaries may be Te-rich, Cd-rich or have Cl, O, Cu, and S segregated there. All of these are likely to change their behaviour.

Negative effects of grain boundariesGrain boundary

diffusionCurrent transportlimitation

Carrierrecombination

Some cell work shows link between grain size and performance.

CdCl2 treatment changes the behaviour of grain boundaries

Positive effects of grain boundaries

Substrate solar cells

• Up to 13.6% substrate cells produced on glass achieved

• Up to 11.5% on flexible Mo foil

• Allows lower cost and flexible substrates to be used.

• Considerable challenges to be overcome – modification of basic process and back contacting

CdTe cell efficiencies

Year

1990 1995 2000 2005 2010 2015 2020

Efficiency (%

)

15

16

17

18

19

20

21

22

23

0.9% increase in 18 years

5.4% increase in 5 years

Past few years have seen a dramatic increase in CdTe performance after years of stagnation

How has this been achieved?

CdTe PV industry

CdTe PV industry

• CdTe industry dominated by first solar

• More than 8GW of installed PV worldwide

• More than 100M modules manufactured

• Worlds single largest PV manufacturer

Record efficiency Date Produce by

15.8% May 1993 Univ. Florida

16.7% Oct 2001 NREL

17.3% Aug 2012 First Solar

18.3% Jan 2013 G.E global research

19.6% Aug 2013 G.E global research

20.4% Feb 2014 First Solar

21.0% Jan 2015 First Solar

21.5% Jun 2015 First Solar

22.1% Feb 2016 First Solar

• If cost ~1$/Wp at 16.7%• Becomes ~0.75$Wp at 22.1%• First Solar predict ~ 25% efficiency achievable with current cell

structure ~0.67$/Wp

0% 1% 2% 3%

4% 5% 10%

• Increased Eg of window layer – not typical CdS.

• Potentially CdS:O –nanostructured CdS where Eg shifts via quantum confinement.

Bandgap grading

In the next 3 years CdTe expected to match Si photovoltaics in efficiency but at much lower cost!

Summary• CdTe solar cells are poised to become lowest

cost mass production PV technology with efficiency surpassing that of multicrystalline Si

• Number of questions still remain – Doping? Bandgap grading? Grain boundaries?

• Cost of power to be further reduced through performance increases and improvements in cell structure or processing.