CDA 4253 FPGA System Design Introduction to Zynqhaozheng/teach/cda4253/slides/zynq.pdfCDA 4253 FPGA...
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CDA 4253 FPGA System DesignIntroduction to Zynq
Hao ZhengDept of Comp Sci & Eng
U of South Florida
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ZedBoard Booting and Configuration Guide ISE Design Suite 14.1
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First Things First Setting Up the ZedBoard Development Board Refer to the following figure and perform the following steps to set up the board for running the applications.
Figure 2 - ZedBoard Development Board
1. Verify a jumper is installed on JP6 to enable the processor to boot from the SD card.
2. Plug a USB cable into the PC and the JTAG micro-B USB connector (J17).
3. Plug a USB cable into the PC and the UART micro-B USB connector (J14).
4. Plug the 12V power supply into the barrel jack (J20). Do not turn the board on.
JTAGJ17
UART J14
Power SW8
Configuration Mode Pins
MIO[0] JP6
12V J20
ZedBoard Booting and Configuration Guide ISE Design Suite 14.1
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JTAG Configuration Mode You can load the FPGA and run the example software application without building the design by using the demo scripts and the pre-built hardware bitstream and software application elf files. You must have the Xilinx tools installed on your host, and have the hardware set up and connected as per the previous steps. Application Download 1. Verify the ZedBoard is powered off and that the configuration Mode jumpers are set
for JTAG mode (all pins shunted to GND) as in the figure below:
2. Slide the power switch (SW8) to the ON position. You will see the green ‘power good’ LED (LD13) illuminate.
3. Navigate to Control Panel o�Device Manager o�Ports (COM & LPT) and identify the COM port connected to the ZedBoard. Start a serial terminal session for the identified COM port and set the serial port parameters to 115200 baud rate, no parity, 8 bits, 1 stop bit and no flow control.
4. Open a command window in the <installation>\demo folder and enter:
run_gpio_test.bat
This batch file sets the proper environment variables and creates the xmd.ini script of commands to be used by the Xilinx Microprocessor Debugger (XMD) tool to program the PL bitstream, initialize the processor, download the application code, and begin execution on the system by performing the following commands automatically: source load_bits.tcl connect arm hw source ps7_init.tcl ps7_init dow gpio_test_0.elf run exit
Zynq 7000 SoC
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Key Features• Processor – Zynq-7000 AP SoC• Memory – 512 MB DDR3 – 256 Mb Quad-SPI Flash – 4GB SDcard
• Communication– Onboard USB-JTAG Programming – 10/100/1000 Ethernet – USB OTG 2.0 and USB-UART
• Expansion Ports – Pmods3
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A General View of Embedded Systems
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Source: ETHZ, Prof. Lothar Thiele
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System-on-a-Board
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Source: The Zynq Book
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System-on-a-Chip (SoC)
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• Higher performance• Lower power use• Small form factor• Reduced cost• flexibility
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How Are FPGAs used in the Past?
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Source: The Zynq Book
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How Are FPGAs used in the Past?
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Source: The Zynq Book
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Zynq – All Programmable SoC
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Source: The Zynq Book
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Generic Embedded Architecture
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Source: The Zynq Book
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Generic Embedded Architecture – Mapping to Zynq
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Source: The Zynq Book
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Zynq 7000 SoC
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Introducing Xilinx Zynq™-7000 AP SoC
● Complete ARM®-based Processing System ○ Dual ARM Cortex™-A9 MPCore™, processor centric ○ Integrated memory controllers & peripherals ○ Fully autonomous to the Programmable Logic
● Tightly Integrated Programmable Logic ○ Used to extend Processing System ○ Scalable density and performance ○ Over 3000 internal interconnects
● Flexible Array of I/O ○ Wide range of external multi-standard I/O ○ High performance integrated serial transceivers ○ Analog-to-Digital Converter inputs
7 Series Programmable
Logic
Common Peripherals
Custom
Peripherals
Common Accelerators
Custom Accelerators
Common Peripherals
Processing System
Memory Interfaces
ARM®
Dual Cortex-A9 MPCore™ System
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Zynq-7000 SoC Block Diagram
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Zynq-7000 AP SoC Block Diagram
Zynq Architecture 12-5 © Copyright 2012 Xilinx
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PS and PL• PS: Processing system, hard silicon core – Dual ARM Cortex-A9 processor based– Multiple peripherals
• PL: Programmable logic– Shares the same 7 series programmable logic as • Artix-based devices: Z-7010 and Z-7020 (high-range I/O
banks only)• Kintex-based devices: Z-7030 and Z-7045 (mix of high-range
and high-performance I/O banks)
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PS Components
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Zynq-7000 AP SoC Block Diagram
Zynq Architecture 12-5 © Copyright 2012 Xilinx
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PS Components• Application processing unit (APU) • I/O peripherals– Multiplexed I/O (MIO), – extended multiplexed I/O (EMIO)
• Memory interfaces • PS interconnect • DMA• Timers • General interrupt controller (GIC) • On-chip memory (OCM)• Debug controller: ARM CoreSight
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Block Diagram – APU
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Source: The Zynq Book
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ARM Cortex–A9 Processor• Dual-core processor cluster• 2.5 DMIP/MHz per processor• Harvard architecture– Self-contained 32KB L1 caches for instructions and
data • External memory based 512KB L2 cache • Automatic cache coherency between processor
cores • Up to 1 GHz operation (fastest speed grade)
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Architecture – NEON
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Source: The Zynq Book
For image and video processing
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PS Peripherals
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• Multiplexed Input/Output (MIO) – Multiplexed output of
peripheral and static memories
• Extended MIO– Extension with PL side IOs– Additional interface with
PL cores
PS Common Peripherals
� Two USB 2.0 OTG/Device/Host – ULPI, 12 Endpoints – Full and High Speed support
� Two Tri- Mode GigE (10/100/1000) – IEEE1588 rev 2.0
� Two SD/SDIO interfaces – Memory, IO and combo cards
� Two CAN 2.0B, SPI , I2C , UART
� Four GPIO 32bit Blocks
� Multiplexed Input/Output (MIO) – Multiplexed output of peripheral and static memories – Two I/O Banks: each selectable - 1.8V, 2.5V or 3.3V – Configured using new feature in XPS
� Extended MIO – Enables use of Select IO with PS peripherals
2x GigE with DMA
2x USB with DMA
2x SDIO with DMA
I/O MUX
2x SPI
2x I2C
2x CAN
2x UART GPIO
Extended MIO
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Static Memory Controllers
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PS – PL Interface• AXI high-performance slave ports (HP0-HP3) – Configurable 32-bit or 64-bit data width – Access to OCM and DDR only – Conversion to processing system clock domain – AXI FIFO Interface (AFI) are FIFOs (1KB) to smooth large
data transfers • AXI general-purpose ports (GP0-GP1) – Two masters from PS to PL – Two slaves from PL to PS – 32-bit data width – Conversation and sync to processing system clock domain
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Zynq-7000 SoC Block Diagram
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Zynq-7000 AP SoC Block Diagram
Zynq Architecture 12-5 © Copyright 2012 Xilinx
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PS – PL Interface
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PS – PL Interface• DMA, interrupts, events signals – Processor event bus for signaling event information to
the CPU– PL peripheral IP interrupts to the PS general interrupt
controller (GIC)• Extended multiplexed I/O (EMIO) allows PS
peripheral ports access to PL logic and device I/O pins
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Memory Map• The Cortex-A9 processor
uses 32-bit addressing • All PS/PL peripherals are
memory mapped to the A9 cores
• All PL slave peripherals are located between– 4000_0000 -- 7FFF_FFFF
(connected to GP0)– 8000_0000 -- BFFF_FFFF
(connected to GP1) 25
The Cortex-A9 processor uses 32-bit addressing All PS peripherals and PL peripherals are memory mapped to the Cortex-A9 processor cores All slave PL peripherals will be located between 4000_0000 and 7FFF_FFFF (connected to GP0) and 8000_0000 and BFFF_FFFF (connected to GP1)
Memory Map
Zynq Architecture 12-15 © Copyright 2012 Xilinx
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AXI Interface
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AXI is Part of ARM’s AMBA
AMBA
APB AHB AXI
Older Performance Newer
AMBA 3.0 (2003)
AMBA: Advanced Microcontroller Bus Architecture AXI: Advanced Extensible Interface
Zynq Architecture 12-31 © Copyright 2012 Xilinx
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Basic AXI Protocol
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Basic AXI Signaling – 5 Channels
1. Read Address Channel 2. Read Data Channel 3. Write Address Channel 4. Write Data Channel 5. Write Response Channel
Zynq Architecture 12-33 © Copyright 2012 Xilinx
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AXI4—Lite Protocol
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The AXI Interface—AX4-Lite
No burst Data width 32 or 64 only – Xilinx IP only supports 32-bits
Very small footprint Bridging to AXI4 handled automatically by AXI_Interconnect (if needed)
AXI4-Lite Read
AXI4-Lite Write
Zynq Architecture 12-34 © Copyright 2012 Xilinx
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AXI4 Protocol
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The AXI Interface—AXI4
Sometimes called “Full AXI” or “AXI Memory Mapped” – Not ARM-sanctioned names
Single address multiple data – Burst up to 256 data beats
Data Width parameterizable – 1024 bits
AXI4 Read
AXI4 Write
Zynq Architecture 12-35 © Copyright 2012 Xilinx
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AXI4—Stream Protocol
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The AXI Interface—AXI4-Stream
No address channel, no read and write, always just master to slave – Effectively an AXI4 “write data” channel
Unlimited burst length – AXI4 max 256 – AXI4-Lite does not burst
Virtually same signaling as AXI Data Channels – Protocol allows merging, packing, width
conversion – Supports sparse, continuous, aligned,
unaligned streams
AXI4-Stream Transfer
Zynq Architecture 12-36 © Copyright 2012 Xilinx
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Basic Zynq Design Flow
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Source: The Zynq Book
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Hardware Development
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Hardware Development
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Software Development
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• BSP includes low-level SW routing interfacing with HW• Refreshed by SDK when HW base is changed
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Figure 1 - ZedBoard Hardware Block Diagram
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References• Zedboard Hardware User Guide• The Zynq Book– Chapter 1, 2, 3
• The Zynq 7000 SoC Technical Reference Manual
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