CDA 4253 FPGA System Design Sequential Circuit Building Blocks Hao Zheng Dept of Comp Sci & Eng USF.
CDA 4253 FPGA System Design Introduction to VHDL -...
-
Upload
truongcong -
Category
Documents
-
view
251 -
download
3
Transcript of CDA 4253 FPGA System Design Introduction to VHDL -...
![Page 1: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/1.jpg)
CDA4253FPGASystemDesignIntroductiontoVHDL
Hao ZhengDept of Comp Sci & Eng
USF
![Page 2: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/2.jpg)
2
Reading
• P.Chu,FPGAPrototypingbyVHDLExamples- Chapter1,Gate-levelcombinationalcircuits
• XilinxXSTUserGuide- Xilinxspecificlanguagesupport
• TwopurposesofusingVHDL:- Simulation- Synthesis – focusofthiscourse
![Page 3: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/3.jpg)
3
Recommended reading
• Wikipedia – The Free On-line Encyclopedia
VHDL - http://en.wikipedia.org/wiki/VHDLVerilog - http://en.wikipedia.org/wiki/Verilog
![Page 4: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/4.jpg)
4
BriefHistoryofVHDL
![Page 5: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/5.jpg)
5
• VHDLisalanguagefordescribingdigitallogicsystemsusedbyindustryworldwide
VHDL isanacronymforVHSIC(VeryHighSpeedIntegratedCircuit)HardwareDescriptionLanguage
• Now,thereareextensionstodescribeanalogdesigns.
VHDL
![Page 6: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/6.jpg)
6
GenesisofVHDL– State ofartcirca1980
-Multiple design entry methods and hardware description languages in use-No or limited portability of designs between CAD tools from different vendors-Objective: shortening the time from a design
concept to implementation from 18 months to 6 months
![Page 7: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/7.jpg)
7
A Brief History of VHDL
• July 1983: a DoD contract for the development of VHDL awarded to-Intermetrics-IBM-Texas Instruments
• August 1985: VHDL Version 7.2 released• December 1987:
VHDL became IEEE Standard 1076-1987 and in 1988 an ANSI standard
![Page 8: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/8.jpg)
8
Subsequent versions of VHDL
- IEEE-1076 1987- IEEE-1076 1993 ← most commonly supported by
CAD tools- IEEE-1076 2000 (minor changes)- IEEE-1076 2002 (minor changes)- IEEE-1076 2008
![Page 9: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/9.jpg)
9
Verilog
![Page 10: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/10.jpg)
10
- Essentially identical in function to VHDL- Simpler and syntactically different
• C-like- Gateway Design Automation Co., 1985- Gateway acquired by Cadence in 1990- IEEE Standard 1364-1995 (Verilog-95)- Early de facto standard for ASIC design- Two subsequent versions
• Verilog 2001 (major extensions) ← dominant version used in industry
• Verilog 2005 (minor changes)- Programming language interface to allow connection to non-
Verilog code
Verilog
![Page 11: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/11.jpg)
11
VHDL vs. Verilog
Government Developed
Commercially Developed
Ada based C based
Strongly Type Cast Mildly Type Cast
Case-insensitive Case-sensitive
Difficult to learn Easier to Learn
More Powerful Less Powerful
![Page 12: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/12.jpg)
12
Features of VHDL/Verilog
• Technology/vendor independent
• Portable
• Reusable
![Page 13: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/13.jpg)
13
GoodVHDL/VerilogBookscomingsoon
![Page 14: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/14.jpg)
14
VHDLFundamentals
![Page 15: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/15.jpg)
15
Naming and Labeling (1)
• VHDL is case insensitive.Example:
Names or labelsdatabusDatabusDataBusDATABUS
are all equivalent
![Page 16: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/16.jpg)
16
Naming and Labeling (2)General rules of thumb (according to VHDL-87)
1. All names should start with an alphabet character (a-z or A-Z)
2. Use only alphabet characters (a-z or A-Z) digits (0-9) and underscore (_)
3. Do not use any punctuation or reserved characters within a name (!, ?, ., &, +, -, etc.)
4. Do not use two or more consecutive underscore characters (_ _) within a name (e.g., Sel_ _A is invalid)
5. No forward slashes “/” in names.6. All names and labels in a given entity and architecture
must be unique.
![Page 17: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/17.jpg)
17
Extended IdentifiersAllowed only in VHDL-93 and higher:1. Enclosed in backslashes2. May contain spaces and consecutive underscores3. May contain punctuation and reserved characters within a
name (!, ?, ., &, +, -, etc.)4. VHDL keywords allowed5. Case sensitive
Examples: \rdy\ \My design\ \!a\\RDY\ \my design\ \-a\
Should not be used to avoid confusioin!
![Page 18: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/18.jpg)
18
Literals
• Numeric:32,-16,3.1415927• Bits:‘1’,‘0’• Strings:“Hello”• Bitstrings:B”1111_1111”,O”353”,X”AA55”• Concatenation:“1111”&“0000”=>“1111_0000”
![Page 19: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/19.jpg)
19
Objects
• Signal – modelrealphysicalwiresforcommunications- Orphysicalstorageofinformaton
• Variable – aprogrammingconstructtomodeltemporarystorage
• Constant – itsvalueneverchangesafterinitialization
![Page 20: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/20.jpg)
20
Comments• Comments in VHDL are indicated with
a “double dash”, i.e., “--”§ Comment indicator can be placed anywhere in the line§ Any text that follows in the same line is treated asa comment
§ Carriage return terminates a comment§ No method for commenting a block extending over a
couple of lines
• Examples:-- main subcircuit
Data_in <= Data_bus; -- reading data from the input FIFO
![Page 21: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/21.jpg)
21
• Explain function of module to other designers• Explanatory, not Just restatement of code• Placed close to the code described- Put near executable code, not just in a header
Comments
![Page 22: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/22.jpg)
22
Free Format
• VHDL is a “free format” languageNo formatting conventions, such as spacing or indentation imposed by VHDL compilers. Space, tabs, and carriage return treated the same way.Example:
if (a=b) then
or
if (a=b) then
orif (a =
b) then
are all equivalent
![Page 23: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/23.jpg)
23
Readability Standards & Coding StyleAdopt readability standards based on the
textbook by Chu
Use coding style recommended in OpenCores Coding Guidelines
Available at the course web page
Penalty may be enforced for not followingthese recommendations!!!
![Page 24: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/24.jpg)
24
DescribingDesigns
![Page 25: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/25.jpg)
25
Example: NAND Gate
ab
zDesignname
andInterface
NAND
entity nand_gate isport( a:in STD_LOGIC;
b:in STD_LOGIC;z :out STD_LOGIC);
end nand_gate;
![Page 26: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/26.jpg)
26
Example: NAND Gate – Function
a b z0 0 10 1 11 0 11 1 0
ab
z
ARCHITECTUREmodel OF nand_gate ISBEGIN
z <=a NAND b;ENDmodel;
![Page 27: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/27.jpg)
27
Example VHDL Code• 3 sections of VHDL code to describe a design.• File extension for a VHDL file is .vhd• Name of the file should be the same as the entity name
(nand_gate.vhd) [OpenCores Coding Guidelines]
LIBRARY DECLARATION
ENTITY DECLARATION
ARCHITECTURE BODY
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY nand_gate IS
PORT( a : IN STD_LOGIC;
b : IN STD_LOGIC;
z : OUT STD_LOGIC);
END nand_gate;
ARCHITECTURE model OF nand_gate IS
BEGIN
z <= a NAND b;
END model;
![Page 28: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/28.jpg)
28
Design Entity - most basic building block of a design.
One entity can have many different architectures.
entity declaration
architecture 1
architecture 2
architecture 3
design entity
Design Entity
![Page 29: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/29.jpg)
29
ENTITY nand_gate IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
z : OUT STD_LOGIC
);
END ENTITY nand_gate;
Entity name Port names Port type Semicolon
No Semicolon after last port
Port modes (data flow directions)
Entity Declaration
• Entity Declaration describes an interface of the component, i.e. input and output ports.
![Page 30: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/30.jpg)
30
Entity Declaration – Simplified Syntax
ENTITY entity_name IS
PORT (
port_name : port_mode signal_type;
port_name : port_mode signal_type;
………….
port_name : port_mode signal_type
);
END ENTITY entity_name;
![Page 31: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/31.jpg)
31
a
EntityPort signal
Driver residesoutside the entity
Port Mode – IN
![Page 32: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/32.jpg)
32
Entity Port signal
Driver residesinside the entity
Output cannot be read within the entity
z
c <= z
c
Port Mode – OUT
![Page 33: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/33.jpg)
33
Port signal
EntityDriver residesinside the entity
Signal x can beread inside the entity
x
c
z
z <= xc <= x
Port Mode – OUT (with Extra Signal)
![Page 34: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/34.jpg)
34
Signal can beread inside the entity
EntityPort signal
Driver may reside both inside and outside of the entity
a
PortMode– INOUT
![Page 35: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/35.jpg)
35
PortModes– Summary
The Port Mode of the interface describes the direction in which data travels with respect to the component- In: Data comes into this port and can only be read within
the entity. It can appear only on the right side of a signal or variable assignment.
- Out: The value of an output port can only be updated within the entity. It cannot be read. It can only appear on the left side of a signal assignment.
- Inout: The value of a bi-directional port can be read and updated within the entity model. It can appear on both sides of a signal assignment.
![Page 36: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/36.jpg)
36
Architecture (Architecture body)
• Describes an implementation of a design entity
• Architecture example:
ARCHITECTURE dataflow OF nand_gate ISBEGIN
z <=a NAND b;END [ARCHITECTURE] dataflow;
Logic operators: NOT, AND, OR, NAND, NOR, XOR, XNOR
![Page 37: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/37.jpg)
37
Architecture – Simplified Syntax
ARCHITECTURE architecture_name OF entity_name IS
Declarations
BEGIN
Concurrent statements
END [ARCHITECTURE] architecture_name;
![Page 38: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/38.jpg)
38
Entity Declaration & ArchitectureLIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY nand_gate IS
PORT( a : IN STD_LOGIC;
b : IN STD_LOGIC;
z : OUT STD_LOGIC);
END ENTITY nand_gate;
ARCHITECTURE dataflow OF nand_gate IS
BEGIN
z <= a NAND b;
END ARCHITECTURE dataflow;
![Page 39: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/39.jpg)
39
Tips & Hints
Place each entity in a different file.
The name of each file should be exactly the sameas the name of an entity it contains.
These rules are not enforced by all toolsbut are worth following in order to increasereadability and portability of your designs
![Page 40: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/40.jpg)
40
Place the declaration of each port, signal, constant, and variable
in a separate linefor better readability
These rules are not enforced by all toolsbut are worth following in order to increasereadability and portability of your designs
Tips & Hints
![Page 41: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/41.jpg)
41
Libraries
![Page 42: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/42.jpg)
42
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY nand_gate IS
PORT( a : IN STD_LOGIC;
b : IN STD_LOGIC;
z : OUT STD_LOGIC);
END ENTITY nand_gate;
ARCHITECTURE dataflow OF nand_gate IS
BEGIN
z <= a NAND b;
END ARCHITECTURE dataflow;
Library Declarations
Use all definitions from the packagestd_logic_1164
Library declaration
![Page 43: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/43.jpg)
43
Library Declarations – Syntax
LIBRARY library_name;
USE library_name.package_name.package_parts;
![Page 44: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/44.jpg)
44
Structure of a Library
PACKAGE 1 PACKAGE 2
TYPESCONSTANTSFUNCTIONS
PROCEDURESCOMPONENTS
TYPESCONSTANTSFUNCTIONS
PROCEDURESCOMPONENTS
LIBRARY
![Page 45: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/45.jpg)
45
• ieee
• std
• work – current working directory
Libraries
Need to be explicitlydeclared
Visible by default
Specifies digital logic system,including STD_LOGIC, and STD_LOGIC_VECTOR types
Specifies built-in data types(BIT, BOOLEAN, INTEGER, REAL, SIGNED, UNSIGNED, etc.), arithmetic operations, basic type conversion functions, basic text i/o functions, etc.
Holds current designs after compilation
![Page 46: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/46.jpg)
46
OperatorsinStandardVHDL
RTL Hardware Design by P. Chu
Chapter 3 35
Operators in standard VHDL
![Page 47: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/47.jpg)
47
StandardVHDL– DataTypes
• integer-Minimalrange:-(2^31– 1)to2^31– 1
• boolean:{true,false}• bit: {‘1’,‘0’}• bit_vector:stringofbits.
![Page 48: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/48.jpg)
48
STD_LOGIC Demystified
![Page 49: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/49.jpg)
49
STD_LOGICLIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY nand_gate IS
PORT( a : IN STD_LOGIC;
b : IN STD_LOGIC;
z : OUT STD_LOGIC);
END nand_gate;
ARCHITECTURE dataflow OF nand_gate IS
BEGIN
z <= a NAND b;
END dataflow;
![Page 50: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/50.jpg)
50
BITversusSTD_LOGIC
• VHDLstandardBIT type- Canonlymodelavalueof‘0’ or‘1’
• STD_LOGIC canmodelninevalues- ’U’,’X’,‘0’,’1’,’Z’,’W’,’L’,’H’,’-’- Usefulmainlyforsimulation- ‘0’,’1’,‘X’and‘Z’ aresynthesizable
(yourcodesshoulduseonlythesefourvalues)
![Page 51: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/51.jpg)
51
STD_LOGIC type demystified
Value Meaning
‘U’ Uninitialized
‘X’ Forcing (Strong driven) Unknown
‘0’ Forcing (Strong driven) 0
‘1’ Forcing (Strong driven) 1
‘Z’ High Impedance
‘W’ Weak (Weakly driven) Unknown
‘L’ Weak (Weakly driven) 0.Models a pull down.
‘H’ Weak (Weakly driven) 1. Models a pull up.
‘-’ Don't Care
![Page 52: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/52.jpg)
52
More on STD_LOGIC Meanings (1)
‘1’
‘0’
‘X’ Contention on the bus
![Page 53: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/53.jpg)
53
More on STD_LOGIC Meanings (2)
![Page 54: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/54.jpg)
54
Resolving Logic Levels
U X 0 1 Z W L H -U U U U U U U U U UX U X X X X X X X X0 U X 0 X 0 0 0 0 X1 U X X 1 1 1 1 1 XZ U X 0 1 Z W L H XW U X 0 1 W W W W XL U X 0 1 L W L W XH U X 0 1 H W W H X- U X X X X X X X X
![Page 55: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/55.jpg)
55
STD_LOGICRules
• Inthiscourse,useonlystd_logic orstd_logic_vector forallentityinputoroutputports
• DoNOT useinteger,unsigned,signed,bitforports- Youcanusetheminsideofarchitecturesifdesired- Youcanusethemingenerics
• Insteadusestd_logic_vector andaconversionfunctioninsideofyourarchitecture[ConsistentwithOpenCores CodingGuidelines]
![Page 56: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/56.jpg)
56
Signals Modeling Wires and Buses
SIGNAL a : STD_LOGIC;
SIGNAL b : STD_LOGIC_VECTOR(7 DOWNTO 0);
wirea
busb
1
8
![Page 57: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/57.jpg)
57
StandardLogicVectors
SIGNAL a: STD_LOGIC;
SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL c: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL d: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL e: STD_LOGIC_VECTOR(8 DOWNTO 0);
……….
a <= ‘1’; --assign a with logic ONE
b <= ”0000”; --Binary base assumed by default
c <= B”0000“; --Binary base explicitly specified
d <= X”AF67”; -- Hexadecimal base
e <= O”723”; -- Octal base
![Page 58: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/58.jpg)
58
VectorsandConcatenation
SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL c, d, e: STD_LOGIC_VECTOR(7 DOWNTO 0);
a <= ”0000”;
b <= ”1111”;
c <= a & b; -- c = ”00001111”
d <= ‘0’ & ”0001111”; -- d <= ”00001111”
e <= ‘0’ & ‘0’ & ‘0’ & ‘0’ & ‘1’ & ‘1’ &
‘1’ & ‘1’; -- e <= ”00001111”
![Page 59: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/59.jpg)
59
MergingWiresandBuses
SIGNAL addr : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL data : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL ctrl : STD_LOGIC_vector(1 downto 0);
SIGNAL bus : STD_LOGIC_VECTOR(10 DOWNTO 0);
bus <= addr & data & ctrl;
4
5
10
2
addr
data
ctrl
bus
![Page 60: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/60.jpg)
60
Splittingbuses
SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL b: STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL c: STD_LOGIC;
SIGNAL d: STD_LOGIC_VECTOR(9 DOWNTO 0);
a <= d(9 downto 6);
b <= d(5 downto 1);
c <= d(0);
4
5
10
a
b
c
d
![Page 61: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/61.jpg)
61
TypesofVHDLDescription(ModelingStyles)
![Page 62: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/62.jpg)
62
Design Entity - most basic building block of a design.
One entity can have many different architectures.
entity declaration
architecture 1
architecture 2
architecture 3
design entity
Design Entity
![Page 63: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/63.jpg)
63
TypesofVHDLDescriptions
Components andinterconnects
structural
VHDL Descriptions
dataflow
Concurrent statements
behavioral
• Registers• State machines• Decoders
Sequential statements
Subset most suitable for synthesis
• Testbenches
![Page 64: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/64.jpg)
64
xor3 Example
![Page 65: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/65.jpg)
65
Entityxor3 Gate
LIBRARY ieee;USE ieee.std_logic_1164.all;
ENTITY xor3 ISPORT( A: IN STD_LOGIC;
B: IN STD_LOGIC;C: IN STD_LOGIC;Result : OUT STD_LOGIC);
endENTITY xor3;
![Page 66: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/66.jpg)
66
Dataflow Modeling
![Page 67: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/67.jpg)
67
DataflowArchitecture- xor3 Gate
ARCHITECTURE dataflow OF xor3 IS
SIGNAL U1_OUT: STD_LOGIC;
BEGIN
U1_OUT <= A XOR B;
Result <= U1_OUT XOR C;
END ARCHITECTURE dataflow;
U1_OUT
![Page 68: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/68.jpg)
68
DataflowDescription
• Describes how data moves through the various processing steps of the system. - Uses series of concurrent statements to realize logic. - Most useful style when series of Boolean equations can represent a
logic à used to implement simple combinational logic
- Dataflow code also called concurrent code• Concurrent statements are evaluated at the same time; thus, the order of
these statements does NOT matter- This is not true for sequential/behavioral statements
U1_out <= A XOR B;
Result <= U1_out XOR C;
Result <= U1_out XOR C;
U1_out <= A XOR B;
Describe the same behavior
![Page 69: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/69.jpg)
69
Event-DrivenSemantics
• Whenaconcurrentstatementisevaluated?
• Aneventisachangeofvalueonasignal.• Considertheexampleinthepreviousslide.
when there is an event on a signal on the right hand side of an assignment.
U1_out <= A XOR B;
Result <= U1_out XOR C;
Result <= U1_out XOR C;
U1_out <= A XOR B;
![Page 70: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/70.jpg)
70
Event-DrivenSemantics
U1_out <= A XOR B;
Result <= U1_out XOR C;
Result <= U1_out XOR C;
U1_out <= A XOR B;
0A 0B 0C 0U1_out 0Result 0
![Page 71: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/71.jpg)
71
Event-DrivenSemantics
U1_out <= A XOR B;
Result <= U1_out XOR C;
Result <= U1_out XOR C;
U1_out <= A XOR B;
0 1A 0 1B 0 0C 0 0U1_out 0 0Result 0 0
![Page 72: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/72.jpg)
72
Event-DrivenSemantics
U1_out <= A XOR B;
Result <= U1_out XOR C;
Result <= U1_out XOR C;
U1_out <= A XOR B;
0 1 1 + tA 0 1 1B 0 0 0C 0 0 0U1_out 0 0 1Result 0 0 0
![Page 73: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/73.jpg)
73
Event-DrivenSemantics
U1_out <= A XOR B;
Result <= U1_out XOR C;
Result <= U1_out XOR C;
U1_out <= A XOR B;
0 1 1 + t 1 + 2tA 0 1 1 1B 0 0 0 0C 0 0 0 0U1_out 0 0 1 1Result 0 0 0 1
![Page 74: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/74.jpg)
74
Event-DrivenSemantics– AnotherExample
U1_out <= A XOR B;
Result <= U1_out XOR C;
0 1A 0 1B 0 0C 0 1U1_out 0 0Result 0 0
![Page 75: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/75.jpg)
75
Event-DrivenSemantics– AnotherExample
U1_out <= A XOR B;
Result <= U1_out XOR C;
0 1 1 + tA 0 1 1B 0 0 0C 0 1 1U1_out 0 0 1Result 0 0 1
![Page 76: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/76.jpg)
76
Event-DrivenSemantics– AnotherExample
U1_out <= A XOR B;
Result <= U1_out XOR C;
0 1 1 + t 1 + 2tA 0 1 1 1B 0 0 0 0C 0 1 1 1U1_out 0 0 1 1Result 0 0 1 0
![Page 77: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/77.jpg)
77
Structural Modeling
![Page 78: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/78.jpg)
78
StructuralArchitecture– xor3Gate
ABC
Resultxor3I1I2
Y I1I2
Y
U1_OUT
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY xor2 IS
PORT( I1 : IN STD_LOGIC;
I2 : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END ENTITY xor2;
ARCHITECTURE dataflow OF xor2 IS
BEGIN
Y <= I1 xor I2;
END ARCHITECTURE dataflow;
xor2.vhd
![Page 79: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/79.jpg)
79
StructuralArchitectureinVHDL93
ARCHITECTURE structural OF xor3 IS
SIGNAL U1_OUT: STD_LOGIC;
BEGIN
U1: entity work.xor2(dataflow) –- VHDL93 style
PORT MAP (I1 => A, I2 => B, Y => U1_OUT);
U2: entity work.xor2(dataflow)
PORT MAP (I1 => U1_OUT, I2 => C, Y => Result);
END ARCHITECTURE structural;
ABC
Resultxor3I1I2
Y I1I2
Y
U1_OUT
![Page 80: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/80.jpg)
80
StructuralArchitectureinVHDL93
inst_label: entity lib_name.entity_name(arch_name)
PORT MAP (
port1 => actual_signal1,
port2 => actual_signal2,
...
);
General Syntax
Actual signals can be• ports of the entity where the component is instantiated• signals declared in the architecture body
![Page 81: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/81.jpg)
81
I1I2
Y I1I2
Y
U1_OUT
StructuralArchitectureinVHDL87ARCHITECTURE structural OF xor3 IS
SIGNAL U1_OUT: STD_LOGIC;COMPONENT xor2
PORT(I1 : IN STD_LOGIC;I2 : IN STD_LOGIC;Y : OUT STD_LOGIC);
END COMPONENT;
BEGINU1: xor2 PORT MAP (I1 => A, I2 => B, Y=> U1_OUT);
U2: xor2 PORT MAP (I1 => U1_OUT,I2 => C,Y => Result);
END structural;
ABC
Resultxor3
![Page 82: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/82.jpg)
82
StructuralDescription
• Allowsdivide-n-conquerforlargedesigns.• Thisstyleistheclosesttoschematiccaptureandutilizessimplebuildingblockstocomposelogicfunctions.
• Componentsareinterconnectedinahierarchicalmanner.
• Structuraldescriptionsmayconnectsimplegatesorcomplex,abstractcomponents.
• Structuralstyleisusefulwhenexpressingadesignthatisnaturallycomposedofsub-blocks.
![Page 83: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/83.jpg)
83
Behavioral Modeling
![Page 84: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/84.jpg)
84
BehavioralArchitecture– xor3Gate
ARCHITECTURE behavioral OF xor3 ISBEGINxor3_behave: PROCESS (A, B, C)BEGIN
IF ((A XOR B XOR C) = '1') THENResult <= '1';
ELSEResult <= '0';
END IF;END PROCESS xor3_behave;
END ARCHITECTURE behavioral;
![Page 85: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/85.jpg)
85
BehavioralDescription
• Itdescribeswhathappensontheinputsandoutputsoftheblackbox(nomatterhowadesignisactuallyimplemented).- Focusonfunctionsmappinginputstooutputs- Similartodataflowstyle,-MorelikesequentialSWprogramming.
• Thisstyleusesprocess statements in VHDL.- Aprocessitselfisaconcurrent statement.- Aprocessconsistofsequential statements.
• Morewillbecoveredlater.
![Page 86: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/86.jpg)
86
VerificationandTestBench
![Page 87: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/87.jpg)
87
Design Testing and Testbenches
• After a design is done, it needs to be tested.• During testing, design inputs are driven by
various test vectors, and• Outputs are monitored and checked.
Test vector generator
UUT/DUT
Monitor
![Page 88: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/88.jpg)
88
Testbench in VHDL
Test vector generator
UUT/DUT
Monitor
testbench
library ieee;use ieee.std_logic_1164.all;
ENTITY testbench ISEND testbench;
![Page 89: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/89.jpg)
89
ARCHITECTURE tb_arch OF testbench IS-- signal declarationssignal A, B, C, Result : std_logic;
BEGIN-- Instantiate the design under test.
uut: entity work.xor3(structural)port map (A => A, B => B, ... );
-- test vector generatortest_gen: processbegin
-- generate sequence of vectors to-- drive design inputs A, B, and C.
end process;end tb_arch;
![Page 90: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/90.jpg)
90
ARCHITECTURE tb_arch OF testbench IS-- signal declarationssignal A, B, C, Result : std_logic;
BEGIN-- DUT instance...-- test vector generatorprocessbegin
A <= ‘1’; -- first test vectorB <= ‘0’;C <= ‘0’;wait for 20ns; -- wait for circuit
-- to stablize...
end process;end tb_arch;
![Page 91: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/91.jpg)
91
Backup
![Page 92: CDA 4253 FPGA System Design Introduction to VHDL - USFhaozheng/teaching/cda4253/slides/vhdl-1.pdf · CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci &](https://reader031.fdocuments.net/reader031/viewer/2022021820/5aedcf4c7f8b9a572b8bd293/html5/thumbnails/92.jpg)
92
TypesofVHDLDescriptions:AlternativeView
Components & interconnects
Structural
VHDL Descriptions
dataflow
Concurrent statements
algorithmic
Sequential statements
Behavioral