CDA 4213/CIS 6930 CMOS VLSI Design Lecture 14 · CMOS VLSI Design Lecture 14. Last ... • Familiar...

23
CDA 4213/CIS 6930 CDA 4213/CIS 6930 CMOS VLSI Design CMOS VLSI Design Lecture 14 Lecture 14

Transcript of CDA 4213/CIS 6930 CMOS VLSI Design Lecture 14 · CMOS VLSI Design Lecture 14. Last ... • Familiar...

Page 1: CDA 4213/CIS 6930 CMOS VLSI Design Lecture 14 · CMOS VLSI Design Lecture 14. Last ... • Familiar with the design, verification and assertion languages: RTL, VHDL, ... • Scripting

CDA 4213/CIS 6930CDA 4213/CIS 6930

CMOS VLSI DesignCMOS VLSI Design

Lecture 14Lecture 14

Page 2: CDA 4213/CIS 6930 CMOS VLSI Design Lecture 14 · CMOS VLSI Design Lecture 14. Last ... • Familiar with the design, verification and assertion languages: RTL, VHDL, ... • Scripting

Last official class on Thursday, December 4.Exam Tuesday, December 9.

Exam is comprehensive and includes:lectures, notes, videos, quizzes, homework, exams.

Chapters 1, 4, 5, 7, 8, 12, 14, 15.

Page 3: CDA 4213/CIS 6930 CMOS VLSI Design Lecture 14 · CMOS VLSI Design Lecture 14. Last ... • Familiar with the design, verification and assertion languages: RTL, VHDL, ... • Scripting

Testing, Debugging, and Verification

Chapter 15

DesignSimulation

LayoutFabrication

Test

Page 4: CDA 4213/CIS 6930 CMOS VLSI Design Lecture 14 · CMOS VLSI Design Lecture 14. Last ... • Familiar with the design, verification and assertion languages: RTL, VHDL, ... • Scripting

Test

What is test?What are we testing?How are we testing?

When are we testing?What are we looking for?

How do we find it?How do we know it when we see it?

What are considerations/constraints?

(Compare metrology)

Page 5: CDA 4213/CIS 6930 CMOS VLSI Design Lecture 14 · CMOS VLSI Design Lecture 14. Last ... • Familiar with the design, verification and assertion languages: RTL, VHDL, ... • Scripting

Debug also called diagnosis.We will call it diagnosis.Hence, test & diagnosis.

(compare diagnosis with prognosis).

What is diagnosis?When do we diagnose?How do we diagnose?

Is it structured? Ad hoc? Crap shoot?What are considerations/constraints?

Page 6: CDA 4213/CIS 6930 CMOS VLSI Design Lecture 14 · CMOS VLSI Design Lecture 14. Last ... • Familiar with the design, verification and assertion languages: RTL, VHDL, ... • Scripting

VerificationSoC Design Verification Engineer

Location: San Diego, California

Summary:

As verification is a rapidly changing field and consumes the majority of the design process, developing and deploying new verification methodologies is an essential part of the work you will do. Assertions, simulation, formal verification, HW-SW co-verification and constraint/HVL-based verification are all tools in our verification toolbox you will use on a daily basis.

Duties:

You will be responsible for understanding the expected functionality of designs, developing corresponding testplans, designing and developing components of our verification environment, and applying these to verify complex designs until coverage goals are achieved in order to ensure the continued commercial success of our high-quality products. These designs are wireless SOCs targeted for high-performance Smartphones and Tablets.

Skills/Experience Required:

• Strong critical thinking, problem solving and test planning skills.• Design verification experience (developing test plan, test bench, tests, assertions, functional & code coverage, debugging tests and designs).• General knowledge in ASIC design process, digital design, design (hw/sw) verification tools and techniques, computer architecture, etc.• Familiar with the design, verification and assertion languages: RTL, VHDL, Verilog, SystemVerilog, SystemVerilog Assertions (SVA), Vera, e-Specman, etc.• Knowledge of SOC, ARM processor, AMBA bus, DDR, or peripherals is preferred.• Scripting and automation skills: Unix/Linux shell programming, Perl, Makefile, revision management (e.g. CVS, ClearCase) is a plus.

Education: BS/MS/PhD in Computer Engineering, Electrical Engineering or Computer Science.

Page 7: CDA 4213/CIS 6930 CMOS VLSI Design Lecture 14 · CMOS VLSI Design Lecture 14. Last ... • Familiar with the design, verification and assertion languages: RTL, VHDL, ... • Scripting

Jobs at Jobs at Encore SemiEncore Semi

Frontend Design Automation Santa Clara, CA 4509617

Senior ASIC Engineer (Design, Synthesis, Low Power) San Diego, CA 4509614

Place and Route Flow Development Engineer San Diego, CA 4509611

IP Modeling and Timing Analysis Flow Development San Diego, CA 4509608

IP Modeling and Timing Analysis Flow Development San Diego, CA 4509605

Design Verification and Post Silicon Validation (low power design exp) San Diego, CA 4509602

Memory System Performance Engineer San Diego, CA 4509596

Physical Design Engineer for DDR PHYs San Diego, CA 4509593

Digital and Mixed-Signal Circuit Design Verification Engineer (USB3.0, USB2.0 and PCIe2.0 protocol) San Diego, CA 4509590

SoC Design Verification Engineer San Diego, CA 4509587

Senior Verification Design Automation Engineer San Diego, CA 4509581

Senior Digital Design Engineer (ASIC/RTL design, synthesis, and timing closure) San Diego, CA 4509578

Senior Front-End Design Automation Engineer San Diego, CA 4509575

Physical Design Implementation in advanced CMOS technologies (Floorplanning, Power-Grid, Low Power, ICC PnR, PT STA/SI/PX) San Diego, CA 4509569

Physical Design Advanced Technology Engineer (ICC or Olympus) San Diego, CA 4509563

Design Verification and Methodology Deployment Engineer San Diego, CA 4509557

Silicon Validation and Emulation (SVE) Project Manager San Diego, CA 4509554

System on Chip (SoC) Project Manager San Diego, CA 4509551

Technology Foundation IP Development Project Manager San Diego, CA 4509545

Physical Design Project Manager San Diego, CA 4509542

Page 8: CDA 4213/CIS 6930 CMOS VLSI Design Lecture 14 · CMOS VLSI Design Lecture 14. Last ... • Familiar with the design, verification and assertion languages: RTL, VHDL, ... • Scripting

Jobs at Jobs at Encore SemiEncore Semi

Design for Test (DFT) Project Manager San Diego, CA 4509527

SerDes Technical Project Manager San Diego, CA 4509506

DDR Project Manager San Diego, CA 4509494

Core/IP Development Project Manager San Diego, CA 4509485

Java Database Developer Santa Clara, CA 4509473

Java Database Developer San Diego, CA 4509464

Validation Content Development (ARMv7/v8 or Cortex-A9/A15/A53/A57) San Diego, CA 4509455

System and SOC Debug (ARMv7/v8 or Cortex-A9/A15/A53/A57) San Diego, CA 4509449

Validation Execution (TCU, PVT, Regression, Post Silicon, Fmax, Automation) San Diego, CA 4509446

Validation Content Development (ARMv7/v8 or Cortex-A9/A15/A53/A57) Austin, TX 4509443

Cadence EDI Auto-Place-and-Route Expert Santa Clara, CA 4509440

Cadence EDI Auto-Place-and-Route Expert Chandler, AZ 4509434

Senior Cadence Design Automation Engineer Santa Clara, CA 4509425

Senior Cadence Design Automation Engineer Chandler, AZ 4509419

High-Speed Analog Circuit Design Engineer San Jose, CA 4509407

Lead Layout Design Engineer San Jose, CA 4509101

Physical Design & Methodology Engineer (ChipBench, ChipEdit) San Jose, CA 4509092

High-Speed Logic Design Engineer San Jose, CA 4508717

Core/IP Analog Circuit Design Engineer for SerDes San Jose, CA 4508714

Core/IP Analog Circuit Design Engineer for SerDes Raleigh, NC 4508339

Page 9: CDA 4213/CIS 6930 CMOS VLSI Design Lecture 14 · CMOS VLSI Design Lecture 14. Last ... • Familiar with the design, verification and assertion languages: RTL, VHDL, ... • Scripting

Jobs at Jobs at Encore SemiEncore Semi

High-Speed Analog Circuit Design Engineer Raleigh, NC 4508189

Lead Layout Design Engineer Raleigh, NC 4508180

Physical Design & Methodology Engineer (ChipBench, ChipEdit) Raleigh, NC 4508177

High-Speed Logic Design Engineer Raleigh, NC 4508174

Core/IP Analog Circuit Design Engineer for SerDes Hopewell Junction, NY 4508171

High-Speed Analog Circuit Design Engineer Hopewell Junction, NY 4508168

Lead Layout Design Engineer Hopewell Junction, NY 4508165

Physical Design & Methodology Engineer (ChipBench, ChipEdit) Hopewell Junction, NY 4508162

High-Speed Logic Design Engineer Hopewell Junction, NY 4508159

Core/IP Analog Circuit Design Engineer for SerDes Essex Junction, VT 4508150

High-Speed Analog Circuit Design Engineer Essex Junction, VT 4508147

Lead Layout Design Engineer Essex Junction, VT 4508144

Physical Design & Methodology Engineer (ChipBench, ChipEdit) Essex Junction, VT 4508132

High-Speed Logic Design Engineer Essex Junction, VT 4508123

Core/IP Analog Circuit Design Engineer for SerDes Austin, TX 4508120

High-Speed Analog Circuit Design Engineer Austin, TX 4508114

Lead Layout Design Engineer Austin, TX 4508093

Physical Design & Methodology Engineer (ChipBench, ChipEdit) Austin, TX 4508084

High-Speed Logic Design Engineer Austin, TX 4505024

Senior Memory Layout Engineer San Jose, CA 4505018

Page 10: CDA 4213/CIS 6930 CMOS VLSI Design Lecture 14 · CMOS VLSI Design Lecture 14. Last ... • Familiar with the design, verification and assertion languages: RTL, VHDL, ... • Scripting

Jobs at Jobs at Encore SemiEncore Semi

Senior Memory Circuit Design Engineer San Jose, CA 4505015

Senior Memory Layout Engineer Rochester, MN 4505012

Senior Memory Circuit Design Engineer Rochester, MN 4505009

Senior Memory Layout Engineer Raleigh, NC 4505006

Senior Memory Circuit Design Engineer Raleigh, NC 4505003

Senior Memory Layout Engineer Fishkill, NY 4505000

Senior Memory Circuit Design Engineer Hopewell Junction, NY 4504988

Senior Memory Layout Engineer Burlington, VT 4504973

Senior Memory Circuit Design Engineer Essex Junction, VT 4504955

Senior Memory Layout Engineer Austin, TX 4504931

Senior Memory Circuit Design Engineer Austin, TX 4504925

Design for Power (DFP) Engineer (experience using MVRC and/or VSI-LP or Conformal LP) Sunnyvale, CA 4504922

Design for Power (DFP) Engineer (experience using MVRC and/or VSI-LP or Conformal LP) Markham, ON 4504913

Design for Power (DFP) Engineer (experience using MVRC and/or VSI-LP or Conformal LP) Boxborough, MA 4504907

Design for Power (DFP) Engineer (experience using MVRC and/or VSI-LP or Conformal LP) Austin, TX 4504904

Page 11: CDA 4213/CIS 6930 CMOS VLSI Design Lecture 14 · CMOS VLSI Design Lecture 14. Last ... • Familiar with the design, verification and assertion languages: RTL, VHDL, ... • Scripting

Encore SemiEncore SemiManagement Team

Grant Miller

COO & CFO

Mario J Lucarelli

Vice President of Business Development

William Ruby

VP Sales & Technology Solutions

Mark Mason

Director of Hardware Engineering

Chris Gray

Director of Embedded Software Engineering

Javier Leon

Director of Recruiting

Urban Jangren

Former President, now Advisor

Page 12: CDA 4213/CIS 6930 CMOS VLSI Design Lecture 14 · CMOS VLSI Design Lecture 14. Last ... • Familiar with the design, verification and assertion languages: RTL, VHDL, ... • Scripting

Back to test, diagnosis, and verification...

Page 13: CDA 4213/CIS 6930 CMOS VLSI Design Lecture 14 · CMOS VLSI Design Lecture 14. Last ... • Familiar with the design, verification and assertion languages: RTL, VHDL, ... • Scripting

Tools:

Software-

Hardware-

Page 14: CDA 4213/CIS 6930 CMOS VLSI Design Lecture 14 · CMOS VLSI Design Lecture 14. Last ... • Familiar with the design, verification and assertion languages: RTL, VHDL, ... • Scripting
Page 15: CDA 4213/CIS 6930 CMOS VLSI Design Lecture 14 · CMOS VLSI Design Lecture 14. Last ... • Familiar with the design, verification and assertion languages: RTL, VHDL, ... • Scripting
Page 16: CDA 4213/CIS 6930 CMOS VLSI Design Lecture 14 · CMOS VLSI Design Lecture 14. Last ... • Familiar with the design, verification and assertion languages: RTL, VHDL, ... • Scripting
Page 17: CDA 4213/CIS 6930 CMOS VLSI Design Lecture 14 · CMOS VLSI Design Lecture 14. Last ... • Familiar with the design, verification and assertion languages: RTL, VHDL, ... • Scripting

Tools and terminology:

TesterProbe cardTest boardTest equipmentZif socketsLoad boardPCBTest programTest VectorsAssertionsReceiver/DriverPin configurationLevelsTimingFPGABICS

RZ, NRZ, SBZDUTDUT boardHandlerExhaustive testing*ATPGDirect v RandomRegression TestingVersion controlBare diePackaged partWafer levelSchmoo plotE-beamSyndromeIEEE 1149.1

FIBSEMAFMLVPPICAControllabilityObservabilityRepeatabilityBISTIDDQPRSG/LFSRCRCJTAGDFMBILBOBoundary scan

Page 18: CDA 4213/CIS 6930 CMOS VLSI Design Lecture 14 · CMOS VLSI Design Lecture 14. Last ... • Familiar with the design, verification and assertion languages: RTL, VHDL, ... • Scripting

15.5 Manufacturing Test Principles

Fault ModelsStuck-At FaultsShort-Circuit and Open-Circuit FaultsObservabilityControllabilityRepeatabilitySurvivabilityFault Coverage: To achieve world-class quality levels, circuits are required to have >98.5% FC.ATPGDelay Fault Testing

Page 19: CDA 4213/CIS 6930 CMOS VLSI Design Lecture 14 · CMOS VLSI Design Lecture 14. Last ... • Familiar with the design, verification and assertion languages: RTL, VHDL, ... • Scripting

15.6 Design for Testability

Ad Hoc Testing: Only useful for small designs where scan, ATPG, and BIST are not available.

– Partitioning large sequential circuits– Adding test points– Adding multiplexors– Providing for easy state reset

Scan Design: Evolved to provide observability and controllability at each register.

– Scan chain: D-type FF and MUX.– Parallel scan

Page 20: CDA 4213/CIS 6930 CMOS VLSI Design Lecture 14 · CMOS VLSI Design Lecture 14. Last ... • Familiar with the design, verification and assertion languages: RTL, VHDL, ... • Scripting

15.6.3 Built-In Self-Test (BIST) also called BILBO.

What are advantages/disadvantages?Area, pads, speed, power...

Methods:Signature AnalysisCyclic Redundancy Checking

– PRSG from and LFSR– Signature Analyzer– Syndrome

Page 21: CDA 4213/CIS 6930 CMOS VLSI Design Lecture 14 · CMOS VLSI Design Lecture 14. Last ... • Familiar with the design, verification and assertion languages: RTL, VHDL, ... • Scripting

15.6.4 IDDQ Testing

Quiescent current testing (compared with transient current testing).The trick is discerning between faulty and fault-free current.

– This is where BICS comes in (sound familiar?)

Page 22: CDA 4213/CIS 6930 CMOS VLSI Design Lecture 14 · CMOS VLSI Design Lecture 14. Last ... • Familiar with the design, verification and assertion languages: RTL, VHDL, ... • Scripting

15.7 Boundary Scan

JTAG IEEE 1149.1Chip level testingBoard level testingAccess through the TAP

Page 23: CDA 4213/CIS 6930 CMOS VLSI Design Lecture 14 · CMOS VLSI Design Lecture 14. Last ... • Familiar with the design, verification and assertion languages: RTL, VHDL, ... • Scripting

End of Lecture


Solution CMOS VLSI Design 4th (Odd)

Solution CMOS VLSI Design 4th (Odd)

CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design Harris Lab 1: Gate Design

CMOS VLSI Design Harris Lab 1: Gate Design

VLSI Design CMOS Transistor Theory

VLSI Design CMOS Transistor Theory

Introduction to CMOS VLSI Design Nonideal Transistors.

Introduction to CMOS VLSI Design Nonideal Transistors.

CMOS VLSI Design - eas.uccs.educwang/ECE4340/Chapter1_2.pdf · 1 CMOS VLSI Design Circuits & Layout CMOS VLSI Design Slide 2 Outline A Brief History CMOS Gate Design Pass Transistors

CMOS VLSI Design - eas.uccs.educwang/ECE4340/Chapter1_2.pdf · 1 CMOS VLSI Design Circuits & Layout CMOS VLSI Design Slide 2 Outline A Brief History CMOS Gate Design Pass Transistors

Principles of Cmos Vlsi Design

Principles of Cmos Vlsi Design

Introduction to CMOS VLSI Design CMOS Transistor Theory.

Introduction to CMOS VLSI Design CMOS Transistor Theory.

CMOS VLSI Design MIPS Processor Example

CMOS VLSI Design MIPS Processor Example

Lecture 11: Adders - CMOS VLSI Design

Lecture 11: Adders - CMOS VLSI Design

VLSI Digital Systems Design - Courses · cmpe222_03process_ppt.ppt 1 VLSI Digital Systems Design CMOS Processing

VLSI Digital Systems Design - Courses · cmpe222_03process_ppt.ppt 1 VLSI Digital Systems Design CMOS Processing

CMOS Analog VLSI Design EE: 618

CMOS Analog VLSI Design EE: 618

Introduction to CMOS VLSI Design Adders

Introduction to CMOS VLSI Design Adders

Introduction to CMOS VLSI Design (E158) Harris Lab …pages.hmc.edu/harris/class/e158/01/lab1.pdfIntroduction to CMOS VLSI Design (E158) Harris Lab 1: ... Electric VLSI Design System

Introduction to CMOS VLSI Design (E158) Harris Lab …pages.hmc.edu/harris/class/e158/01/lab1.pdfIntroduction to CMOS VLSI Design (E158) Harris Lab 1: ... Electric VLSI Design System

Subject Code 17M21EC111 Semester Session 2018-19 Month ...CMOS technology, VLSI design methodologies, VLSI design flow, Design hierarchy, VLSI design styles 3 7. Design interface CMOS

Subject Code 17M21EC111 Semester Session 2018-19 Month ...CMOS technology, VLSI design methodologies, VLSI design flow, Design hierarchy, VLSI design styles 3 7. Design interface CMOS

Introduction to CMOS VLSI Design - ocw.titech.ac.jp

Introduction to CMOS VLSI Design - ocw.titech.ac.jp

VLSI Design CMOS Technology - asic-reliability.com€¦ · VLSI Design: CMOS Technology 1 VLSI Design CMOS Technology Frank Sill Torres. Universidade Federal de Minas Gerais (UFMG),

VLSI Design CMOS Technology - asic-reliability.com€¦ · VLSI Design: CMOS Technology 1 VLSI Design CMOS Technology Frank Sill Torres. Universidade Federal de Minas Gerais (UFMG),

WesteEshraghian Principles of Cmos Vlsi Design

WesteEshraghian Principles of Cmos Vlsi Design

Introduction to CMOS VLSI Designkogge/courses/cse40462-VLSI-fa18/www/Public/... · CMOS VLSI Design Standard Cell Layout Layout Slide 17 Layout CMOS VLSI Design Slide 18 Gate Layout

Introduction to CMOS VLSI Designkogge/courses/cse40462-VLSI-fa18/www/Public/... · CMOS VLSI Design Standard Cell Layout Layout Slide 17 Layout CMOS VLSI Design Slide 18 Gate Layout

EE466: VLSI Design Lecture 7: Circuits & Layout. CMOS VLSI Design1: Circuits & LayoutSlide 2 Outline CMOS Gate Design Pass Transistors CMOS Latches &

EE466: VLSI Design Lecture 7: Circuits & Layout. CMOS VLSI Design1: Circuits & LayoutSlide 2 Outline CMOS Gate Design Pass Transistors CMOS Latches &