CBP 2009Comp 3014 The Nature of Computing 1 Laundry Model Washer Drier Store Basket Wardrobe.

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CBP 2009 Comp 3014 The Nature of C omputing 1 Laundry Model Washer Drier Store Basket Wardrobe

Transcript of CBP 2009Comp 3014 The Nature of Computing 1 Laundry Model Washer Drier Store Basket Wardrobe.

CBP 2009 Comp 3014 The Nature of Computing

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Laundry Model

Washer Drier Store Basket Wardrobe

CBP 2009 Comp 3014 The Nature of Computing

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Process Steps

Wash then Dry

1 load takes 2 hours

idle

idle running

running

time

time

9.00 10.00 11.00

1. Load the washer at 9.00

2. Done at 10, load the drier

3. Drier Done at 11

0.5

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Sequential Process

3 loads takes 6 hours

time

9.00 15.00 11.00

1. Load washer at 9.00

2. Done at 10, load drier

3. Drier Done at 11

4. Reload washer at 11

5. Done at 12, load drier

6. Drier done at 13

7. Reload washer at 13

8. Done at 14, load drier

9. Done at 15

13.00

0.5

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Overlapping Process

3 loads takes 4 hours

time

9.00 15.00 11.00

1. Load washer at 9.00

2. Done at 10, load drier reload washer

3. Both Done at 11. Reload drier reload washer

4. Both done at 12. Reload drier

5. Drier done at 13

13.00

From 10.00 till 11.00 both washer and dryer running concurrently

0.75

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Washing Pipeline Filling

time

9.00 11.00 13.00 15.00 17.00

18.00

5 loads in 9 hours

5 Cycles !!!1. Get

washing2. Wash3. Dry4. Store5. Put away

0.55

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Washing Pipeline Fulltime

9.00 11.00 13.00 15.00 17.00

Pipe Full gives 1 load per hour 1.0

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Can we Pipeline SAM ?

Data Memory

Instruction reg

Code Memory

ALU

r1

r2

r0X

Y

W

X Y

W

0

1

7mar

mdr

1.Fetch

2.Dec/Reg

3.ALU 4.Mem

5.RW

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Pipelined Sam4

Data Memory

0

1

7

X

Y

W

Y

W

r1

r2

r0

X

Code Memory

1.Fetch

2.Dec/Reg

3.ALU 4.Mem 5.RW

Buffer

time

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5 Stages in Pipeline

AL

UMem Reg Mem Reg

add r3,r1,r2 r1,r2 r3add

Let’s take the instruction add r3,r1,r2 and show which stage is needed for each part of the instruction.

1.Fetch 2.Dec/Reg

3.ALU 4.Mem 5.RW

time

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ld r0 Mem r3

Two Instructions

ld r3,[r0+2]

Two instructions into the pipeline

add r4,r1,r2 AL

Uadd r1,r2 r4

r0

2

time

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Structural Hazard

AL

UMem Reg Mem Reg

AL

UMem Reg Mem Reg

AL

UMem Reg Mem Reg

AL

UMem Reg Mem Reg

AL

UMem Reg Mem Reg

Here we are being asked to read from memory and write to it simultaneously. Impossible!

Write (store)

Read (fetch

)

Solution – Use separate code and data memories

add r4,r1,r2

st r0,[5]

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Hazardous Washing

time

9.00 11.00 13.00 15.00 17.00

18.00

Washing basket containes both clean and dirty

washing!

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Code and Data Memories

AL

UMem Reg Mem Reg

AL

UMem Reg Mem Reg

AL

UMem Reg Mem Reg

AL

UMem Reg Mem Reg

AL

UMem Reg Mem Reg

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add r1,r2 r3

Data Hazard

add r3,r1,r2

but need r3 here

EARLIER !

add r4,r1,r3 add r1,r3 r4

r3 set heretime

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Data Hazard

AL

UMem Reg Mem Reg

AL

UMem Reg Mem Reg

AL

UMem Reg Mem Reg

AL

UMem Reg Mem Reg

AL

UMem Reg Mem Reg

add r3,r1,r2

add r4,r1,r3

Need value of r3 for second instruction before the first is complete.

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Pipeline Stalls

AL

UMem Reg Mem Reg

AL

UMem Reg Mem Reg

AL

UMem Reg Mem Reg

Mem

AL

UReg Mem RegStall Stall

AL

UMem Reg Mem Reg

add r3,r1,r2

add r4,r1,r3

Resolve Hazard – Insert delay into second instruction stream. ‘Stall’ Cycles.

But this needs extra electronics on the chip. Complex and Costly.