CBM workshop – GSI, April 18th – 20th 2007. A. Rivetti Pixel detector development for PANDA...
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Transcript of CBM workshop – GSI, April 18th – 20th 2007. A. Rivetti Pixel detector development for PANDA...
CBM workshop – GSI, April 18th – 20th 2007. A. Rivetti
Pixel detector development for PANDA
A. Rivetti INFN – Sezione di Torino
CBM workshop – GSI, April 18th – 20th 2007. A. Rivetti
Major requirements
In PANDA the MVD is expected to contribute also to particle ID via dE/dx.
Dynamic range: up to 2.5 MeV of deposited energy (700000 electrons).
Low momentum particles => low material budget.
About 120 modules and 1300 front-end chip will be needed.
Asymmetric hit rate distribution.
Global estimated rate: 1.025 GHz (50 Gbit/s)
Maximum hit rate per module: 34 MHz (1.7 Gbit/s)
Maximum hit rate per front-end chip: 5.8 MHz (290 Mbit/s)
Triggerless read-out
Front-end power < 200mW/chip.
Pixel size: 100 m x 100 m
CBM workshop – GSI, April 18th – 20th 2007. A. Rivetti
Motivations for R&D
Custom front-end design motivated by the combination of:
Large dynamic range.
Pixel form factor.
Triggerless read-out.
Material budget
Eg. Tests done in Juelich show that the ATLAS chip used in “PANDA
mode” is at the limit of rate required and would dissipate 330 mW/chip.
In this presentation:
Architecture of the front-end.
Results from a first prototype.
R&D work on epitaxial silicon sensors.
CBM workshop – GSI, April 18th – 20th 2007. A. Rivetti
FE chip FE chip FE chip FE chip
Detector Data Concentrator
to DAQ
Inside the mvd
Counting room
First stage
Third stage
Detector Setup System
Detector Control System
ReadOut BoardROB
Second stage
Outside the mvd
FE chip FE chip FE chip FE chip
Detector Data Concentrator
to DAQ
Inside the mvd
Counting room
First stage
Third stage
Detector Setup System
Detector Control System
ReadOut BoardROB
Second stage
Outside the mvd
Pixel read-out chain
CBM workshop – GSI, April 18th – 20th 2007. A. Rivetti
Front – end chip
Pixel matrix
Read – out logic
Basic features:
Chip size O(1 cm2 ).
Technology 0.13 m CMOS.
Adequate radiation tolerance.
Buttable on three sides.
Capable of handling sensors of both
polarities.
In each pixel: hit time and charge
CBM workshop – GSI, April 18th – 20th 2007. A. Rivetti
3 tasks run simultaneously:
• Hit detection in pixel and storage of time stamp
• Readout of pixel data into the column FiFos
• Readout of FiFos out of the FE
Column read-out ATLAS-like. Chip read-out optimized for triggerless environment
A first architecture
CBM workshop – GSI, April 18th – 20th 2007. A. Rivetti
Event ordering
Three circuits in the chip ensures the proper time ordering of the hits in case of counter overflow.
The column controller, which generates a counter-overflow signal when the counter overflows after all “old” data in a column was read out.
The read-out controller. If a FIFO shows a CO event, its read-out is stopped till all the FIFO show a CO event.
The EoC event generator. The EoC is generated when all the FIFO show a CO event. The EoC mark is sent outside the chip and the CO flags are cleared.
CBM workshop – GSI, April 18th – 20th 2007. A. Rivetti
Architecture simulations
Combined Monte-Carlo – VHDL simulations.
Simulation based on a sample of 120000 events on pbar on copper with a beam momentum of 4 GeV/c.
Full read-out cycle simulated on 68000 events.
800 hit lost (1.18 %)
Reasons for losses:
hit below threshold (set at 1200 electrons)
Pile-up on the ToT (0.5 %)
CBM workshop – GSI, April 18th – 20th 2007. A. Rivetti
Front-end readout time (1)
CBM workshop – GSI, April 18th – 20th 2007. A. Rivetti
Front-end readout time (2)
CBM workshop – GSI, April 18th – 20th 2007. A. Rivetti
First prototype for PANDA
A first prototype was designed and tested.
Aim of the exercise: gain experience with the technology (very complex!) and explore the analogue performance.
32 pixel cells with preamplifier with ToT and comparator.
Goal: keep the analogue power consumption below 12 W pixel at 1.2V supply
Pixel cell Pixel cell Pixel cell Pixel cell Pixel cell Pixel cell Pixel cell Pixel cell
4 Analog Outputs
4 Digital Outputs
4 Calibration Inputs
3-bit Selection Bus
8 Selectable pixel groups 6 Inputs
CBM workshop – GSI, April 18th – 20th 2007. A. Rivetti
Inside the pixel cell
CFB
INCAL
CCAL IN OUT_DIGITAL
OUT_ANALOGUE
VREF_D
Preamplifier Discriminator
Leakage Compensation
ILC
IFB
VREF_P
TOT
VA
CBM workshop – GSI, April 18th – 20th 2007. A. Rivetti
Preamp schematic
Leakage compensation Amplifier
Active feedback
Single stage preamplifier design to minimize power consumption
Feedback capacitor of 10fF nominal value
Calibration capacitor of 30 fF
CBM workshop – GSI, April 18th – 20th 2007. A. Rivetti
Comparator schematic
CBM workshop – GSI, April 18th – 20th 2007. A. Rivetti
Test board
The chip has been wired bonded to a small sensor provided by ITC – IRST (Trento).
CBM workshop – GSI, April 18th – 20th 2007. A. Rivetti
Chip and sensor detail
Fe chip
IRST sensor
CBM workshop – GSI, April 18th – 20th 2007. A. Rivetti
Performance example
CBM workshop – GSI, April 18th – 20th 2007. A. Rivetti
Preamp response to 0.5fC
Noise@ 0pF: 98 e- rms
CBM workshop – GSI, April 18th – 20th 2007. A. Rivetti
ToT linearity
0,00
1000,00
2000,00
3000,00
4000,00
5000,00
6000,00
0,00 10,00 20,00 30,00 40,00
Input charge (fC)
To
T(n
s)
Only the region up to 32fC can be explored through the injection capacitor Preamplifier saturates at 12 fC.
CBM workshop – GSI, April 18th – 20th 2007. A. Rivetti
A first spectrum
ENC: 440 rms electronsInput capacitance about 1.5 pF
CBM workshop – GSI, April 18th – 20th 2007. A. Rivetti
Epitaxial silicon sensor
Highly doped Cz substrate: = 0.01 – 0.02 cm
Lightly doped epitaxial layer = 50 cm Several studies indicate that sensor build on epi wafer have good radiation tolerance. Interest for PANDA: radiation tolerance adequate with standard p-type design.
Wafers supplied by ITME and processed by ITC-IRST in Trento
Substrate properties:
Diameter: 100 ± 0.5 mm.Doping type: n/Sb.Thickness 525 ± 25 m.Resistivity: 0.01 – 0.02 cm.
Epi layer properties:
Doping type n/P. Thickness 50/75/100 m. Variation: <4%/8%/8% Resistivity: 2500 – 5000 cm.
CBM workshop – GSI, April 18th – 20th 2007. A. Rivetti
Epi assemblies
Low cost R&D reusing existing electronics and sensor design:Electronics: ALICE front-end chip provided by CERNSensor: masks developed by INFN-Ferrara for the P326 project.
Three types of epi assemblies:3 with 150 m total thickness (100 m epi)7 with 120 m total thickness (75 m epi)1 with 100 m total thickness (50 m epi)
Several wafers cracked during thinning (problem more severe on thicker wafer) Problem probably due to stresses on the epi layer: work in progress to fix it Good assemblies were however delivered and will be tested in May.
CBM workshop – GSI, April 18th – 20th 2007. A. Rivetti
Summary
The R&D for a custom pixel detector for PANDA has been started.
The architecture of front-end chip is under development. Design is not yet frozen, many changes still possible! A first analogue prototype has been designed and tested in
0.13m. Good performance obtained for noise, dynamic range,
linearity. The analogue part has been operated with 12 W/pixel. The results are in reasonable agreement with simulations. The technology is significantly more complex than the 0.25
m, but it offers several interesting options (triple-well NMOS, analogue components, thicker oxide devices for I/Os, etc..)
CBM workshop – GSI, April 18th – 20th 2007. A. Rivetti
Credits
Thanks to the many people working on the project in several ways…
D. Calvo, P. Deremigis, G. Mazza, S. Martoiu, M. Mignone, R. Wheadon,
K. Brinkmann, F. Huegging, T. Stocksmann, R. Jäkel, M. Mertens, J . Ritman…
Thanks to the organizers for the invitation!
CBM workshop – GSI, April 18th – 20th 2007. A. Rivetti
Discussion slides
CBM workshop – GSI, April 18th – 20th 2007. A. Rivetti
Some design considerations in 0.13 m
Mobility very different between PMOS and NMOS devices (kN/kP~6).
The use of NMOS transistor to control small currents becomes problematic (problem much more severe than in 0.25 m).
NMOS input with triple-well and splitted PMOS current sources is probably the best compromise.
CBM workshop – GSI, April 18th – 20th 2007. A. Rivetti
Issues related to ToT technique
The preamplifier saturates at 12 fC, but the ToT preserves good “linearity” at least up to 40 fC.
Caveat: in the saturated region the open-loop gain of the input stage drops down, making the system more prone to cross-talk.
Leakage compensation Amplifier
Active feedback
Cin=Cf(1+A0)>>CdCf=10fF, Cd=200fFCin=Cd for A0=20
CBM workshop – GSI, April 18th – 20th 2007. A. Rivetti
Mastering cross talk
The cross-talk with a saturated preamplifier can go up to 20%. Possible remedies:
1. Guard-ring connected to ground 2. Two stage preamplifier, with first stage working always in linearity
hit event
no hit event
Pixel Matrix Adjacent Coupled Detectors
CC Jin2= 0
Jin1 0
Particle hit
Jin2 CD -+
Cf
Vo2
CSA02detector02
Jin1 CD -+
Cf
Vo1
CSA01detector01
Equivalent Circuit
hit event
no hit event
Injectedcharge
CC
CBM workshop – GSI, April 18th – 20th 2007. A. Rivetti
Energy deposited in pixel
CBM workshop – GSI, April 18th – 20th 2007. A. Rivetti
Hits per module
CBM workshop – GSI, April 18th – 20th 2007. A. Rivetti
Time to store hit in a FIFO