Carbon Nanotube Field Effect Transistors Based Low … Nanotube Field Effect Transistors Based Low...

9
Carbon Nanotube Field Effect Transistors Based Low THD and Noise-Immune Double Stage Differential Amplifier for Nanoelectronics Subrata Biswas, Poly Kundu, Md. Hasnat Kabir, Md. Moidul Islam, Sagir Ahmed, Nadia Islam Aditi AbstractDouble Stage Differential Amplifier comprises many advantages by operating differential inputs. It provides excellent immunity to external noise which is certainly a flawless advantage for low-power devices and also reduces Low-Order Harmonics (LOH). This paper presents the design of a double stage differential amplifier using Carbon Nanotube Field Effect Transistors (CNTFETs). The key approach of the proposed design is to reduce the Total Harmonic Distortion (THD), Low-Order Harmonics (LOH), output delay and to achieve a high trans- conductance gain, gm. The paper also carries the significant comparisons between conventional differential amplifier and the proposed design. Both circuits have been simulated by using HSPICE model of CNTFET. The optimized threshold voltage is 0.309V and given bias is 1V only. The Fast Fourier Transform (FFT) and Fourier analysis also shows an outstanding result compared to the conventional one. Moreover, the output voltage is closely zero at common-mode operation which yields a very high Common-Mode Rejection Ratio (CMRR). From the analysis in both common-mode and differential-mode inputs the proposed design was proven to be robustly noise-immune. Keywords- Carbon Nanotube Field Effect Transistor (CNTFET); HSPICE; Current Sink; Total Harmonic Distortion; Low-Order Harmonics; Common Mode Rejection Ratio. I. INTRODUCTION In data-transmission, audio signaling, telephone systems using differential amplifiers are a common approach. It is one of the most versatile circuits used in analog circuit design. These are also widely used in the electronics industry and are generally preferred over their single-ended counterparts because of their better common-mode noise rejection, reduced harmonic distortion, and increased output voltage swing [1]-[3]. They can be readily adapted to function as an operational amplifier, a comparator, a sense amplifier and as a front-end buffer stage for another circuit. These amplifiers are also well-suited for driving differential transmission lines; active termination provides for increased efficiency. The differential amplifier is often a building block or sub- circuit used within high quality integrated circuit amplifiers, linear and nonlinear signal processing circuits, and even certain logic gates and digital interfacing circuits. They are used where linear amplification is required by minimizing the distortion. A double stage differential amplifier circuit is a special type of amplifier that has two inputs and two outputs. This device amplifies input signals on the two input lines that are out of phase and rejects input signals that have a common phase such as induced noise. The common-mode feedback is accomplished by the use of a common mode feedback circuit that monitors the two differential amplifier output lines and provides a feedback signal that adjusts the amplifier's bias current, thereby rejecting the unwanted common-mode signals on the amplifier's output. Symmetry in the two feedback paths is important to have good CMRR performance. In this paper a comprehensive analysis is done on both common-mode and differential-mode signals. In recent years, there has been an increasing demand for a system-on-chip configuration (SOC) and reduction of power consumption, in response to which the CMOS has been widely used. CMOS differential amplifiers are used for various applications because a number of advantages can be derived from these types of amplifiers, as compared to single-ended amplifiers. A single ended amplifier suffers from the lack of common-mode rejection and are highly sensitive to surrounding noisy circuitry [4]-[7]. But in the traditional MOSFET structure, bulk silicon is used as the channel material. As today’s very large scale integration (VLSI) systems mostly rely on silicon MOS technology, the Industry Technology Roadmap (ITR) has predicted that in the nano-regimes, the expected high density will encounter substantial difficulties in terms of physical phenomena and technology limitations, possibly preventing the continued improvements in figures of merit, such as low power and high performance. Nano-scaled alternatives to bulk silicon transistors are therefore being pursued [8]. Hence, to reduce the channel length of MOSFET a new type of transistor has been recently introduced named CNTFET (Carbon Nanotube Field Effect Transistor). Carbon nanotubes (CNTs) are a new form of carbon with unique electrical and mechanical properties [9]- [10]. Its diameter is in nanometer scale. Hence, in this paper MOSFET-like CNTFETs are used for the design and simulation purpose. Now, Power dissipation has become an issue in the designing of devices with low input power. Previously, Static power consumed only 10% of the power supply but with advancement is fabrication technology it has now become comparable to dynamic power [11]. At the 90 nm technology static power may consume up to 42% of total power [12]. To achieve less power consumption CNTFETs can contribute a lot. DOI: 10.5176/2251-3701_3.2.120 GSTF Journal of Engineering Technology (JET) Vol.3 No.2, July 2015 ©The Author(s) 2015. This article is published with open access by the GSTF 7 Received 16 Apr 2015 Accepted 13 May 2015 10.7603/s40707-014-0006-2

Transcript of Carbon Nanotube Field Effect Transistors Based Low … Nanotube Field Effect Transistors Based Low...

Carbon Nanotube Field Effect Transistors Based Low THD and Noise-Immune Double Stage Differential

Amplifier for Nanoelectronics

Subrata Biswas, Poly Kundu, Md. Hasnat Kabir, Md. Moidul Islam, Sagir Ahmed, Nadia Islam Aditi

Abstract— Double Stage Differential Amplifier comprises many advantages by operating differential inputs. It provides excellent immunity to external noise which is certainly a flawless advantage for low-power devices and also reduces Low-Order Harmonics (LOH). This paper presents the design of a double stage differential amplifier using Carbon Nanotube Field Effect Transistors (CNTFETs). The key approach of the proposed design is to reduce the Total Harmonic Distortion (THD), Low-Order Harmonics (LOH), output delay and to achieve a high trans-conductance gain, gm. The paper also carries the significant comparisons between conventional differential amplifier and the proposed design. Both circuits have been simulated by using HSPICE model of CNTFET. The optimized threshold voltage is 0.309V and given bias is 1V only. The Fast Fourier Transform (FFT) and Fourier analysis also shows an outstanding result compared to the conventional one. Moreover, the output voltage is closely zero at common-mode operation which yields a very high Common-Mode Rejection Ratio (CMRR). From the analysis in both common-mode and differential-mode inputs the proposed design was proven to be robustly noise-immune.

Keywords- Carbon Nanotube Field Effect Transistor (CNTFET); HSPICE; Current Sink; Total Harmonic Distortion; Low-Order Harmonics; Common Mode Rejection Ratio.

I. INTRODUCTION

In data-transmission, audio signaling, telephone systems using differential amplifiers are a common approach. It is one of the most versatile circuits used in analog circuit design. These are also widely used in the electronics industry and are generally preferred over their single-ended counterparts because of their better common-mode noise rejection, reduced harmonic distortion, and increased output voltage swing [1]-[3]. They can be readily adapted to function as an operational amplifier, a comparator, a sense amplifier and as a front-end buffer stage for another circuit. These amplifiers are also well-suited for driving differential transmission lines; active termination provides for increased efficiency.

The differential amplifier is often a building block or sub-circuit used within high quality integrated circuit amplifiers, linear and nonlinear signal processing circuits, and even certain logic gates and digital interfacing circuits. They are used where linear amplification is required by minimizing the distortion. A double stage differential amplifier circuit is a special type of

amplifier that has two inputs and two outputs. This device amplifies input signals on the two input lines that are out of phase and rejects input signals that have a common phase such as induced noise. The common-mode feedback is accomplished by the use of a common mode feedback circuit that monitors the two differential amplifier output lines and provides a feedback signal that adjusts the amplifier's bias current, thereby rejecting the unwanted common-mode signals on the amplifier's output. Symmetry in the two feedback paths is important to have good CMRR performance. In this paper a comprehensive analysis is done on both common-mode and differential-mode signals.

In recent years, there has been an increasing demand for a system-on-chip configuration (SOC) and reduction of power consumption, in response to which the CMOS has been widely used. CMOS differential amplifiers are used for various applications because a number of advantages can be derived from these types of amplifiers, as compared to single-ended amplifiers. A single ended amplifier suffers from the lack of common-mode rejection and are highly sensitive to surrounding noisy circuitry [4]-[7]. But in the traditional MOSFET structure, bulk silicon is used as the channel material. As today’s very large scale integration (VLSI) systems mostly rely on silicon MOS technology, the Industry Technology Roadmap (ITR) has predicted that in the nano-regimes, the expected high density will encounter substantial difficulties in terms of physical phenomena and technology limitations, possibly preventing the continued improvements in figures of merit, such as low power and high performance. Nano-scaled alternatives to bulk silicon transistors are therefore being pursued [8]. Hence, to reduce the channel length of MOSFET a new type of transistor has been recently introduced named CNTFET (Carbon Nanotube Field Effect Transistor). Carbon nanotubes (CNTs) are a new form of carbon with unique electrical and mechanical properties [9]-[10]. Its diameter is in nanometer scale. Hence, in this paper MOSFET-like CNTFETs are used for the design and simulation purpose. Now, Power dissipation has become an issue in the designing of devices with low input power. Previously, Static power consumed only 10% of the power supply but with advancement is fabrication technology it has now become comparable to dynamic power [11]. At the 90 nm technology static power may consume up to 42% of total power [12]. To achieve less power consumption CNTFETs can contribute a lot.

DOI: 10.5176/2251-3701_3.2.120

GSTF Journal of Engineering Technology (JET) Vol.3 No.2, July 2015

©The Author(s) 2015. This article is published with open access by the GSTF

7

Received 16 Apr 2015 Accepted 13 May 2015

10.7603/s40707-014-0006-2

This paper is organized as follows: Section II presents a review of carbon nanotube field effect transistor. Section III describes the device simulation of CNTFET. Section IV represents the research motivation to this work. Analysis of the basic (conventional) differential amplifier is described in Section V. In section VI the proposed design and comprehensive analysis. With Section VII this paper ends with a conclusion. HSPICE simulation results show substantial advantages in terms of noise, speed and power consumption when the CNTFETs are employed for in the proposed design.

II. REVIEW OF CARBON NANOTUBE FIELD EFFECT TRANSISTOR

Carbon Nanotube (CNT) is a Nano-scale tube created as a

rolled sheet of graphite which was discovered in 1991 by Dr. Iijima [13]. Planar graphite is arranged in a hexagonal structure due to its sp2 junctions, this honeycomb structure is also seen in carbon nanotubes on a molecular level (Figure 1). A CNT can be multi-wall (MWCNT) or single-wall (SWCNT) [14]. A MWCNT consists of more than one cylinder whereas a SWCNT is a single cylinder. The diameter of SWCNT can be as small as 0.4nm [15]. A SWCNT could be semiconductor or conductor depending on its chirality. With the appropriate chirality, SWNT can be semiconducting [16]-[19]. The following relation expresses the SWCNT band gap energy [20].

(1)

where Egap is the band gap, γo is the carbon-to-carbon tight-binding overlap energy, ac-c is the nearest neighbor carbon-to-carbon distance (0.142 nm), and d is the diameter of the nanotube. A typical semiconducting SWNT has a band gap of about 0.5 – 0.65 eV [21]. This semiconducting property of the carbon nanotube can be applied to form a field-effect transistor (FET) analogous to the MOSFET [22]. A SWCNT can be semiconducting if the angle of the atom arrangement (chirality) is appropriate. A pair of integers (n, m) describes the chiral vector. If n=m or n-m=3i (where i is an integer) the nanotube is metallic, otherwise the tube is semiconducting. Figure 1. Shows the construction of a graphene sheet.

Every carbon atom on the sheet can be expressed as a function of integers (n, m). A chiral vector Ch is the vector perpendicular to the tube axis T, given by

(2)

Depending on chirality the behavior of CNTFET is changed. It is represented by two pair of integer m and n. The equation for calculating the diameter is given below [19].

(3)

where, ao=0.142nm is the inter-atomic distance between each carbon atom and its neighbor. Figure 2. shows the schematic diagram of CNTFET [23]. Similar to the traditional silicon device, the CNTFET also has four terminals. As shown in Figure 2. the undoped semiconducting nanotubes are placed under the gate as channel region, while heavily doped CNT segments are placed between the gate and the source/drain to allow for a low series resistance in the ON-state [24]. As the gate potential increases, the device is electrostatically turned on or off via the gate. The threshold voltage of the intrinsic CNT channel

can be approximated to the first order as the half bandgap that is an inverse function of the diameter [19], [23], [25]. As the chirality vector changes, the threshold voltage of the CNTFET will also change.

(4)

where, a = 2.49 Å is the carbon to carbon atom distance, Vπ = 3.033 eV is the carbon π–π bond energy in the tight bonding model, e is the unit electron charge, and DCNT is the CNT diameter. CNTs can be configured as n-type and p-type. In the proposed design the threshold voltage of NCNTFET using (18, 0) CNTs as channels is 0.309V calculated from (3)-(4) and DCNT of (18, 0) CNTs is only 1.409 nm.

The I–V characteristic of the CNTFET is shown in Figure 3. The characteristic curve is similar to that of MOSFET. The CNTFET device current is saturated at higher Vds (drain to source voltage), as shown in Figure 3., as channel length increases the ON-current decreases due to energy quantization in the axial direction at a lower gate length in the proposed design of CNTFETs. The calculated threshold voltage, Vth for (5, 0) CNTs is 1.0982V.

Figure 1. Construction of graphene sheet and important parameters for

CNTs is chiral vector [19].

Figure 2. Top view of a CNTFET [23].

Figure 3. I–V characteristics curve of a typical NCNTFET (22nm) for the

chirality vector (5, 0).

GSTF Journal of Engineering Technology (JET) Vol.3 No.2, July 2015

©The Author(s) 2015. This article is published with open access by the GSTF

8

III. DEVICE SIMULATION OF CNTFET

An equivalent circuit model for the channel region of basic CNTFET is given in Figure 4. The three current sources considered in this CNTFET model: (i) the thermionic current contributed by the semiconducting sub-bands (Isemi) with the classical band theory, (ii) the current contributed by the metallic sub-bands (Imetal), and (iii) the leakage current (Ibtbt) caused by the band to band tunneling (BTBT) mechanism through the semiconducting sub-bands [19]. The thermionic current contributed by the semi conducting sub-bands is given by

(5)

where, Vch,DS and Vch,GS denotes the Fermi potential differences near source side within the channel, e is the unit electrical charge, ΔфB is the channel surface potential charge with gate/drain bias, Tm is the transmission probably, k is the Boltzmann constant, T is the temperature in Kelvin and Em,0 is the half band gap of the m-th sub-band. In the sub-threshold region, especially with negative gate bias (nFET), the band-to-band tunneling current from drain to source becomes significant. For metallic sub-bands of metallic nanotubes, the current includes both the electron and hole currents [19]. The simplified equation for Imetal is given by

(6)

where, Tmetal is transmission probability. The above equation shows that Imetal is independent of the channel surface-potential change ΔфB as expected because the density of states (DOS) of metallic CNT is independent of the carrier energy. A voltage controlled current source Ibtbt is included in the device model in order to evaluate the device sub-threshold behavior and the static power consumption [19]. The expression for Ibtbt is given by

(7)

where, Ef is the Fermi level of the doped source/drain nanotube in electron-volt unit. Tbtbt is the Wentzel–Kramers–Brillouin-like transmission coefficient. To model the intrinsic ac response of CNTFET device, a controlled trans-capacitance array among the four electrodes (Gate, Drain, Source, and Substrate) with the Meyer capacitor model has been used [19]. Thereby, the equations for capacitance calculation are given below

(8)

(9)

(10)

(11)

In this paper, all circuits have been simulated in HSPICE. A 22nm process has been used for designing purpose. The CNFET model files are taken from Stanford University [23]. The model files for CMOS (incorporated high-κ/metal gate and

stress effect) are taken from Predict Technology Model (PTM) of Arizona State University [26].

IV. RESEARCH MOTIVATION TO THIS WORK

As technology stepped into submicron region, power dissipation has become an issue in the designing of devices with low input power. The total power dissipation can be found as a summation of dynamic power dissipation and static (leakage) power dissipation which can be given by

(12)

The power consumption effect in the advanced technology is previously mentioned in [11], [12]. The logic gates in the generalized CNTFET library dissipate 28% less power on average than a library of conventional CMOS gates [27]. Therefore, CNTFETs are superlatively considered in this paper to design both conventional differential amplifier and the proposed one. Here some prominent analyses are done between CMOS and CNTFET based logic gate.

A. Performance of CNTFET over CMOS

Performance of CNTFET over CMOSFET can be understood by a simple inverter circuit. The DC analysis curves of CNTFET and CMOS inverter circuits are shown in Figure 5. and Figure 6.

Step by step the gate voltage is increased to 1V. At Vg=0V the Vo is high while at Vg=1V the Vo is low. Of these two DC characteristic curves the inversion slope of CNTFET is steeper.

Figure 4. Equivalent circuit model for the intrinsic channel region of a

CNTFET [19].

Figure 5. DC analysis of CNTFET inverter (22nm).

GSTF Journal of Engineering Technology (JET) Vol.3 No.2, July 2015

©The Author(s) 2015. This article is published with open access by the GSTF

9

The simulated results (energy consumption details) of a CNTFET inverter and CMOS inverter are given in Table I.

From Table I. CNTFET inverter dissipates 98.23% less dynamic power and 50.07% faster than CMOS inverter. Considering impeccable fabrication, Pstatic becomes negligible. To be noted that power dissipated as gate leakage was found to be about 10% of Pstatic for CMOS gates and less than 1% of Pstatic for CNTFET because of the high-κ dielectric used as gate insulator in CNTFETs [23]. The above performance benchmarking shows that CNTFET gates are better than CMOS gates.

B. Common Mode Rejection Ratio (CMRR) and Differential Gain

The common-mode rejection ratio (CMRR) of a differential input indicates the capability of the input to reject input signals common to both input leads. A high CMRR is important when the signal of interest is a small voltage fluctuation superimposed on a (large) voltage offset [28]. Actually, this is a measurement of how well the device rejects a common-mode signal. In other words, it measures the quality of the amplifier. The CMRR is defined as the ratio of the differential gain Ad over the common-mode gain Acm [28]

(13)

Hence, to achieve high CMRR it is very important to design a circuit with better differential gain and very small common mode gain.

V. BASIC DIFFERENTIAL AMPLIFIER

A differential amplifier amplifies only the difference between two different potentials regardless of common mode value. It is characterized by its CMRR and its offset voltage [29]. In equation (13) the common mode gain, Acm should be zero and thus CMRR should be infinite. The Figure 7. shows the schematic diagram of a conventional CNTFET differential amplifier. In section IV it has been proved that the performance

of CNTFET is better than CMOS. Therefore, the same traditional CMOS differential amplifier is shown with CNTFET (Figure 7). Figure 7. shows the basic differential amplifier that uses two NCNTFETs (M1 and M2) to form a differential amplifier.

Both M1 and M2 are perfectly matched. So it will operate in

saturation region. Based on this concept, for the large signal analysis, given Vg1>>Vg2 with M1 and M2 the current behavior can be solved as

(14)

(15)

Solving equation (14) and (15) the drain currents can be given as

(16)

(17)

These relations are useful only when

(18)

The desired relation for the most dominant parameter of the differential amplifier trans-conductance can be given by

(19)

From equation (19) it can be observed that the amplifier trans-conductance, gm is directly proportional to Iss. DC analysis of a conventional CNTFET differential amplifier is shown in Figure 8. Here Vg1 increases from 0V to 1V while Vg2 is constantly kept to 0V resulting M2 always turned-OFF. Initially the output is in saturation; since Vg1 is 0V resulting M1 turned-OFF. But as Vg1 increases then it turns ON M1. Most differential amplifiers fit naturally into the trans-conductance amplifier category as they have large input resistance and fairly large output resistance. The DC analysis shows that nearly at Vg1 equals to Vth at 0.309V then the differential output, Vod is approximately 0.695V. The differential gain can be given by

(20)

The phase difference between the actual phase and -180 degrees is the phase margin. To measure better stability of the amplifiers minimum phase margin should be 45 degrees [31]. Figure 9. shows AC analysis where the output signal is at 180 degrees out of phase with the input signals. As the input frequency increases

Figure 6. DC analysis of CMOS inverter (22nm).

Figure 7. Schematic diagram of a conventional CNTFET differential amplifier

(22nm). TABLE II. ENERGY CONSUMPTION TABLE

Description Dynamic Power, Pdynamic (W)

Delay, td (Sec) PDP (J)

CNTFET 2.3912e-09 4.2542e-12 1.0172e-20

CMOS 1.3544e-07 8.3872e-12 1.1359e-18

GSTF Journal of Engineering Technology (JET) Vol.3 No.2, July 2015

©The Author(s) 2015. This article is published with open access by the GSTF

10

the voltage phase decreases. The average dissipated power is about 837.87nW and the output delay is 37.73 ps.

Figure 10 and 11 shows the transient analysis in common-mode and differential-mode inputs. In both cases the individual drain voltage is high when either M1 or M2 is turned-OFF due to the alternating inputs. The common-mode output voltage is nearly zero. In prefect matching case the bias current should be equally divided for M1 and M2 and the net current should be zero in common-mode operation. In case of differential-mode the load current should be exactly to Iss for better trans-conductance gain. The active load in this conventional differential amplifier acts as a current source. Therefore, to minimize the noise it must be biased such that their currents add up exactly to Iss. To be noted that increasing Iss can also increase the trans-conductance. Since this is quite difficult so a current mirror circuit is added in the proposed design to ensure this equality.

The Fast Fourier Transform (FFT) analysis of the

conventional differential amplifier is shown in Figure 12. The achieved DC output voltage components are 1.11mV or -59.09 dB and voltage phase angle is 180 degrees.

The highest FFT component can be found at 500MHz which

is 0dB with phase angle at 85.86 degrees. The calculated phase margin is approximately 265 degrees at 500MHz.

TABLE II. FOURIER ANALYSIS OF THE CONVENTIONAL DIFFERENTIAL AMPLIFIER

Frequency (Hz) Fourier Component 5.000e+08 1.222e+00

1.000e+09 1.989e-03

1.500e+09 3.135e-01

2.000e+09 2.012e-03

2.500e+09 9.908e-02

3.000e+09 1.865e-03

3.500e+09 2.529e-02

4.000e+09 1.848e-03

4.500e+09 4.473e-02

The above Table II. shows the Fourier components of transient response. The fundamental or first harmonic component is 1.22V at 500MHz. Up to 9th harmonic components are shown with their respective frequency in Table II. The Total harmonic Distortion (THD) is 27.23%. The data in Table II. is shown in the following bar diagram (Figure 13) for better understanding. The Low-Order Harmonics (LOH) is 0.314V which is the 3rd harmonic component.

Figure 8. DC analysis of the conventional differential amplifier.

Figure 10. Transient analysis of the conventional differential amplifier for

common-mode inputs.

Figure 11. Transient analysis of the conventional differential amplifier for

differential-mode Inputs

Figure 12. FFT analysis of the conventional differential amplifier.

Figure 9. AC analysis of the conventional differential amplifier.

GSTF Journal of Engineering Technology (JET) Vol.3 No.2, July 2015

©The Author(s) 2015. This article is published with open access by the GSTF

11

VI. PROPOSED DESIGN AND CIRCUIT DIAGRAM

The proposed CNTFET double stage differential amplifier is shown in Figure 14. The NCNTFETs M1 and M2 forms the input stage of differential amplifier; M6 and M7 are for the output stage. M4 and M5 are used for current sink. M3 is used for current mirror. A current mirror is a circuit designed to copy a current through one active device by controlling the current in another active device of a circuit, keeping the output current constant regardless of loading. The gates of M3, M4 and M5 are connected together. The reference current in M3 is copied to M4 and M5 resulting an equal current. The differential input is applied between the gate terminals of M1 and M2; the output can be taken across the drain of M6 and M7. The trans-conductance gain, gm is a function of DCNT, bias current (Id) and differential output voltage (Vod). The DC gain of the double stage differential amplifier can be given by

(21)

Here ith means double stage. Avi is DC gain of double stage of amplifier system independent from the frequency, Gmi is trans-conductance of the input network and RDi is the effective output resistance of output network.

All NCNTFETs are perfectly matched and the optimized Vth

is 0.309V. Simulation in differential-mode is carried out by taking two alternating signals (180 degrees phase shift to each other) as inputs to the gate terminal of M1 and M2. In order to analysis the common-mode again two alternating signals (both are in same phase) as inputs are given to the gate terminal of M1 and M2.

VII. SIMULATION, RESULTS AND ANALYSIS

The Figure 15. shows the DC analysis of the proposed CNTFET double stage differential amplifier. Here Vg1 increases from 0V to 1V while Vg2 is constantly kept to 0V resulting M2 always turned-OFF. Initially the output is in saturation; since Vg1 is 0V resulting M1 turned-OFF. But as Vg1 increases then it turns ON M1 and the drain voltage of M1 decreases. Now, the lower output of M1 turns OFF M6 resulting a higher drain voltage. Similarly, the higher drain voltage of M2 turns ON M7. Thus the output of M7 decreases. The DC analysis shows when Vg1 equals to Vth at 0.309V then the differential output, Vod is approximately 0.495V which is a reasonable adjustment for noise immunity.

Figure 16. shows AC analysis where the output signal after

the 1st stage is at 180 degrees out of phase with the input signals. As the input frequency increases the voltage phase decreases. The output voltage phase of 2nd stage tends to be zero as the frequency increases. The average dissipated power is about 1.948μW which is higher than the conventional design but because of current mirroring the faster operation can be achieved with an output delay of 23.69 ps.

Figure 17 and 18 shows the transient analysis in common-mode and differential-mode inputs. In common-mode analysis the individual drain output (average voltage) of M6 and M7 is very close to zero whereas the individual drain output (average voltage) in case of the conventional differential amplifier is a non-zero value. As a result, a low THD is possible in case of the proposed double stage differential amplifier. Also the transient analysis output is a more sinusoidal-like wave than the conventional one. Further, FFT and Fourier analysis of the

Figure 13. Bar diagram (Fourier analysis) of the conventional differential

amplifier.

Figure 14. Schematic diagram of the proposed CNTFET double stage

differential amplifier (22nm).

Figure 15. DC analysis of the proposed CNTFET double stage differential

amplifier.

Figure 16. AC analysis of the proposed CNTFET double stage differential

amplifier.

GSTF Journal of Engineering Technology (JET) Vol.3 No.2, July 2015

©The Author(s) 2015. This article is published with open access by the GSTF

12

proposed design reveals better performance parameter than the conventional design.

The Fast Fourier Transform (FFT) analysis of the proposed CNTFET double stage differential amplifier is shown in Figure 19. The achieved DC output voltage components are 1.29mV or -57.74 dB and voltage phase angle is zero degree.

The highest FFT component can be found at 500MHz which is 0dB with phase angle at -93.01 degrees. The calculated phase margin is approximately 86.99 degrees at 500MHz. Table III. shows the Fourier components of transient response. The fundamental or first harmonic component is 0.833V at 500MHz. Same as the Table II. here also up to 9th harmonic components are shown with their respective frequency. The Total harmonic Distortion (THD) is 22.61% which is approximately 17 percent lower than the conventional circuit. The data in Table II. is shown in the following bar diagram (Figure 20).

TABLE III. FOURIER ANALYSIS OF THE PROPOSED CNTFET DOUBLE STAGE DIFFERENTIAL AMPLIFIER

Frequency (Hz) Fourier Component 5.00e+08 8.331e-01 1.000e+09 5.076e-03 1.500e+09 1.589e-01 2.000e+09 4.843e-03 2.500e+09 1.134e-02 3.000e+09 4.677e-03 3.500e+09 6.473e-02 4.000e+09 4.616e-03 4.500e+09 7.640e-02

The Low-Order Harmonics (LOH) is 0.159V which is the 3rd harmonic component. The highest distortion on the fundamental component is produced by LOH. In the proposed design the LOH has been reduced by 49.36%. The proposed CNTFET double stage differential amplifier circuit works properly up to 500MHz frequency. After this frequency the performance of circuit gradually declines. The input voltage can be as low as -1.00 volts to +1.00 volts. So the proposed design can be regarded as low power application. The CMRR is very also very high due to the closely zero individual output average voltage. From the analysis it is seen that double stage differential amplifier using CNTFET is much better than the conventional differential amplifier.

VIII. CONCLUSION

This paper is aimed at designing of CNTFET based double

stage differential amplifier and observing various performances compared to a conventional one. Moreover, priority is given to develop a circuit model by integrating current mirror for better noise immunity by reducing the Total Harmonic Distortion (THD) and Low-Order Harmonics (LOH). The simulations are done by HSPICE and the proposed design is compared to the conventional differential amplifier to check if the developed design could meet the expectations. It is then observed that the THD and LOH are pointedly lower in case of the proposed design which makes the circuit more efficient. A significant amount of delay is reduced and also due the nano-scale gate length of CNTFETs, it minimizes the circuit in terms of chip area. The proposed design also consumes very low power.

Figure 17. Transient analysis of the proposed CNTFET double stage

differential amplifier for common-mode inputs.

Figure 18. Transient analysis of the proposed CNTFET double stage

differential amplifier for differential-mode inputs.

Figure 19. FFT analysis of the proposed CNTFET double stage differential

amplifier.

Figure 20. Bar diagram (Fourier analysis) of the proposed CNTFET double

stage differential amplifier.

GSTF Journal of Engineering Technology (JET) Vol.3 No.2, July 2015

©The Author(s) 2015. This article is published with open access by the GSTF

13

Therefore, the proposed CNTFET double stage differential amplifier can be used in designing of low voltage high CMRR operational amplifier.

ACKNOWLEDGMENT

The authors acknowledge the department of Electrical and Electronic Engineering, American International University – Bangladesh for giving permission to access certified software in VLSI laboratory.

REFERENCES [1] A. E. Sackinger and W. Guggenbuhl, “Design of Fully Differential

CMOS Amplifier for Clipping Control Circuit,” World Applied Science Journal, Vol. 3(1), pp. 110-113, 2008.

[2] C. Popa, “Linearity Evaluation Technique for CMOS Differential Amplifier,” Proc. of 26th International Conference on Microelectronics (MIEL 2008), Serbia, pp. 11-14, May 2008.

[3] H. S. C. Baoyong and W. Zhihua, “A Novel Offset Cancellation Technique for Low Voltage CMOS Differential Amplifiers,” Journal of Semiconductors, Vol. 27, No. 5, pp. 778-782, 2006.

[4] A. D. Grasso and S. Pennisi, “High-Performance CMOS Pseudo-Differential Amplifier”, IEEE International Symposium on Circuits and Systems, pp. 1569 – 1572, pp. 23-26, May 2005.

[5] Z. Liu, C. Bian and Z. Wang, “Full Custom Design of a Two-Stage Fully Differential CMOS Amplifier with High Unity-Gain Bandwidth and Large Dynamic Range at Output,” 48th IEEE International Midwest Symposium on Circuits and Systems, Cincinnati, Ohio, U.S.A., pp. 7-10, Aug. 2005.

[6] Z. Butkovic and A. Szabo, “Analysis of the CMOS Differential Amplifier with Active Load and Single-Ended Output,” IEEE MELECON, 2004, pp. 417-420, May 12-15, 2004.

[7] F. Corsi and C. Marzocca, “An Approach to the Analysis of the CMOS Differential Stage with Active Load and Single-Ended Output,” IEEE Trans. Educ., vol. 46, pp. 325-328, Aug. 2003.

[8] S. A. Tawfik, Z. Liu, and V. Kursun, “Independent-gate and tied gate FinFET SRAM circuits: Design guidelines for reduced area and enhanced stability,” in Proc. Int. Conf. Microelectron. (ICM), pp. 171– 174, Dec. 2007.

[9] M. S. Dresselhaus, G. Dresselhaus, and P. C. Eklund, “Science of Fullerenes and Carbon Nanotubes,” Academic press, vol. XVIII, pp. 965, San Diego, CA 1996. [Online]. Available:

http://onlinelibrary.wiley.com/doi/10.1002/adma.19970091518/abstract [Accessed: Jan. 18, 2015].

[10] J. Deng and H.-S. P.Wong, “A compact SPICE model for carbonnanotube field-effect transistors including nonidealities and its application—Part I: Model of the intrinsic channel region,” IEEE Trans. Electron Devices, vol. 54, no. 12, pp. 3186–3194, Dec. 2007.

[11] D. Duarte, N. Vijaykrishnan, M. J. Irwin, and M. Kandemir, “Formulation and validation of an energy dissipation model for the lock generation circuitry and distribution networks,” in Procs. of VLSI Design, pp. 248 – 253, 2001.

[12] J. Kao, S. Narendra, and A. Chandrakasan, “Subthreshold Leakage modeling and reduction techniques,” in Procs. of ICCAD, pp. 141 – 149, 2002.

[13] S. Iijima, “Helical microtubules of graphitic carbon,” Nature 354.6348 (1991): 56-58.

[14] P. L. McEuen, M. Fuhrer, and H. Park, “Single-Walled Carbon Nanotube Electronics,” IEEE Transactions on Nanotechnology, Vol. 1, No. 1, March 2002.

[15] N. Wang, Z.K. Tang, G.D. Li, and J.S. Chen, “Single Walled 4A carbon nanotube arrays,” Nature, vol 408, pp 50-51, Nov 2000.

[16] J. W. Wilder, L. C. Venema, A. G. Rinzler, R. E. Smalley, and C. Dekker, “Electronic structure of atomically resolved carbon nanotubes,” Nature, 391 (6662), 59-62, 1998.

[17] P. Avouris, T. Hertel, R. Martel,T. H. R. H. S. Schmidt, H. R. Shea, and R. E. Walkup, “Carbon nanotubes: nanomechanics, manipulation, and electronic devices,” Applied Surface Science, 141(3), 201-209, 1999.

[18] M. Dresselhaus, G. Dresselhaus, and P. Avouris, Eds., “Carbon Nanotubes: Synthesis, Structure, Properties, andApplications,” Springer-Verlag, New York, 2001.

[19] J. Deng and H. -S. P. Wong, “A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part I: Model of the Intrinsic Channel Region,” IEEE Trnsactions on Electron Devices, Vol. 54, No. 12, pp. 3186-3194, December 2007.

[20] J. Wildoer, L. Venema, A. Rinzler, R. Smalley, and C. Dekker, “Electronic Structure of Atomically Resolved Carbon Nanotubes,” Nature 391, 59 – 64 (1998).

[21] M. Dresselhaus, G. Dresselhaus, Saito, Riichiro, “Carbon fibers based on C60 and their symmetry,” The American Physical Society, Physical review B, Vol. 45, No. 11, 1992.

[22] H.-S. P. Wong, “Beyond the Conventional Transistor,” IBM J. Research & Development, March/May, pp. 133-168, 2002.

[23] (2008) Stanford University CNFET Model, Stanford University, Stanford, CA. [Online]. Available: https://nano.stanford.edu/stanford-cnfet-model [Accessed: Nov. 7, 2014].

[24] J. Appenzeller, “Carbon nanotubes for high-performance electronics- Progress and prospect,” Proc. IEEE, vol. 96, no. 2, pp. 201–211, Feb. 2008.

[25] J. Deng and H.-S. P.Wong, “A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—Part II: Full device model and circuit performance benchmarking,” IEEE Trans. Electron Device, vol. 54, no. 12, pp. 3195–3205, Dec. 2007.

[26] (2008) Predictive Technology Model (PTM), Arizona State University, Tempe, AZ. [Online].

Available: http://ptm.asu.edu/modelcard/HP/22nm_HP.pm [Accessed: Nov. 1, 2014].

[27] M. H. B. Jamaa, K. Mohanram, G. D. Micheli, “Power consumption of logic circuits in ambipolar carbon nanotube technology,” Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010 , pp.303-306, 8-12 Mar. 2010.

[28] Common-mode Rejection Ratio, TiePie engineering, Netherlands. [Online]. Available:

http://www.tiepie.com/en/classroom/Frequently_Used_Terms/CMRR [Accessed: Nov. 10, 2014].

[29] B. J. Hosticka, “Improvement of the Gain of CMOS Amplifiers,” IEEE Journal of Solid-State Circuits, vol.14, no.6, pp. 1111,1114, Dec. 1979.

[30] M. G. Degrauwe, J. Rijmenants, E. A. Vittoz, and H. J. De Man. “Adaptive biasing CMOS amplifiers,” IEEE J. Solid-Stute Circuits, vol. SC-17, pp. 522-528, June 1982.

[31] Gain Margin and Phase Margin, University of Minnesota Duluth, Minnesota, USA. [Online]. Available:

http://www.d.umn.edu/~htang/ece3235_doc_F10/slide6(LastTwo).ppt

[Accessed: Mar. 14, 2015].

GSTF Journal of Engineering Technology (JET) Vol.3 No.2, July 2015

©The Author(s) 2015. This article is published with open access by the GSTF

14

AUTHORS’PROFILE

Subrata Biswas received the B.Sc. degree in electrical and electronic engineering from American International University-Bangladesh, Bangladesh in 2010 with academic awards Summa Cum Laude Distinction. He is currently a Faculty Member in the Department of Electrical and Electronic Engineering at American International University-Bangladesh, Bangladesh. He is the author/co-author of 2 journal articles and 4 conference papers. He also presented 1 paper in International workshop on Nanotechnology, Bangladesh. He is a professional member of IEEE and IEB. He is a frequent technical reviewer of many distinguished IEEE and various conference papers. His current research interests are in the field of MEMS modules and embedded systems.

Poly Kundu received the B.Sc. degree in Physics from National

University, Bangladesh in 2010, and the M.S. degree in Computer Science from American International University-Bangladesh, Bangladesh in 2014 with an excellent academic background. She is currently a Faculty Member in the Department of Computer Science and Engineering at Royal University of Dhaka, Bangladesh. She is the author/co-author of 3 journal articles. Her current research interests are in the field of computer network and architecture and low-power devices.

Md. Hasnat Kabir received the B.Sc. degree in electrical and electronic

engineering from American International University-Bangladesh, Bangladesh in 2014 with an excellent academic background. He is a member of IEEE and ESAB. He has successfully completed various type of Automation Robotics project with NRF at Dhaka, Bangladesh. His current research interests are in the field of low-noise amplifiers and automotive intelligence.

Md. Moidul Islam received the B.Sc. degree in electrical and electronic engineering from American International University-Bangladesh, Bangladesh in 2014 with an excellent academic background. He completed his graduating thesis on Ultrathin Lightweight Amorphous Silicon based Solar cell in COMSOL Multiphysics. He is working on designing and performance analysis of capacitive pressure sensor, cantilever biosensor, mircrostrip antenna and many more. His current research interests are in the field of RF module, biosensors and embedded systems.

Sagir Ahmed received the B.Sc. degree in electrical and electronic engineering from American International University-Bangladesh, Bangladesh in 2014. He completed his graduating research on Electromechanics Modeling of Capacitive Pressure Sensor with Variation of MEMS Insulators in COMSOL Multiphysics. His current research concentrations are in the field of MEMS modules, CNTFET devices, electromagnetic field characteristic.

Nadia Islam Aditi received the B.Sc. degree in electrical and electronics engineering from American International University-Bangladesh, Bangladesh in 2015. She has completed her graduating thesis on COMSOL Multiphysics based Solar Cell Design. Her current research interests are in the field of low noise amplifiers and solar cells.

GSTF Journal of Engineering Technology (JET) Vol.3 No.2, July 2015

©The Author(s) 2015. This article is published with open access by the GSTF

15

This article is distributed under the terms of the Creative Commons Attribution License whichpermits any use, distribution, and reproduction in any medium, provided the original author(s) and the source are credited.