CAD SoftwareVerilog HDL

Figure 2.35. A typical CAD system.

Design conception

VerilogSchematic capture DESIGN ENTRY

Design correct?

Functional simulation

NoYes

No

Synthesis

Physical design

Chip configuration

Timing requirements met?

Timing simulation

Design Entry

• The starting point in the process of designing a logic circuit is the conception of what the circuit is supposed to do and the formulation of its general structure.

• Two design methods:– Schematic capture– Writing source code in HDL

Logic Synthesis

• Synthesis is the process of generating a logic circuit from an initial specification

• Synthesis CAD tools generate efficient implementations of circuits from such specifications

Functional Simulation

• A circuit represented in the form of logic expressions can be simulated to verify that it will function as expected

• The simulator requires the user to specify valuations of the circuit’s inputs that should be applied during simulation

Physical Design

• To determine exactly how to implement the circuit on a given chip

• The physical design tools map a circuit specified in the form of logic expressions into a realization that makes use of the resources available on the target chip

Timing Simulation

• Electronic circuits cannot perform their function in zero delay

• propagation delay – takes a certain amount of time before a

corresponding change occurs– delay caused by signals that must propagate

along wires that connect various logic elements• A timing simulator evaluates the expected

delays of a designed logic circuit

Circuit Implementation

• The circuit is implemented on an actual chip

• Two ways:– Custom-manufactured chip (ASIC) – chip

fabrication– Programmable hardware device – chip

configuration or chip programming

Verilog HDL

• Hardware Description Language (HDL)• 1980s, developed by Gateway Design

Automation, which was later acquired by Cadence Design Systems

• 1990, Verilog was put into the public domain

• 1995, IEEE Standard called 1364-1995• 2001, IEEE Standard called 1364-2001

2 ways to describe circuits

• Structural specification– a set of gate-level primitives that correspond to

commonly-used logic gates• Behavioral specification

– Using gate-level primitives can be tedious when large circuits have to be designed

– An alternative is to use more abstract expressions and programming constructs to describe the behavior of a logic circuit

Figure 2.36. The logic circuit for a multiplexer.

Example 1

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Figure 2.37. Verilog code for the circuit in Figure 2.36.

Structural

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Figure 2.40. Using the continuous assignment to specify the circuit in Figure 2.36.

Behavioral

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Figure 2.42. Behavioral specification of the circuit in Figure 2.36.

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Figure 2.43. A more compact version of the code in Figure 2.42.

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Figure 2.39. Logic circuit for the code in Figure 2.38.

Example 2

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Figure 2.38. Verilog code for a four-input circuit.

module example2 (x1, x2, x3, x4, f, g, h);input x1, x2, x3, x4;output f, g, h;

 and (z1, x1, x3);and (z2, x2, x4);or (g, z1, z2);or (z3, x1, ~x3);or (z4, ~x2, x4);and (h, z3, z4);or (f, g, h);

 endmodule 

Structural

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Figure 2.41. Using the continuous assignment to specify the circuit in Figure 2.39.

module example4 (x1, x2, x3, x4, f, g, h);input x1, x2, x3, x4;output f, g, h;

assign g = (x1 & x3) | (x2 & x4);assign h = (x1 | ~x3) & (~x2 | x4);assign f = g | h;

endmodule

Behavioral

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Figure 2.44. A logic circuit with two modules.

Hierarchical Verilog Code

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Figure 2.45. Verilog specification of the circuit in Figure 2.12.

Adder Module

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Figure 2.46. Verilog specification of the circuit in Figure 2.34.

Display Module

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Figure 2.47. Hierarchical Verilog code for the circuit in Figure 2.44.

Top-level Module

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