Cache Performance Evaluation under Multi-parameters Using SMPCache simulator
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Transcript of Cache Performance Evaluation under Multi-parameters Using SMPCache simulator
![Page 1: Cache Performance Evaluation under Multi-parameters Using SMPCache simulator](https://reader031.fdocuments.net/reader031/viewer/2022012313/55a8d63c1a28abd7778b476c/html5/thumbnails/1.jpg)
Jordan University Computer Engineering Department
Computer Performance Evaluation Project
Supervisor: Dr. Ghieth AbandahStudent: Aieshah F. Almaslam
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![Page 2: Cache Performance Evaluation under Multi-parameters Using SMPCache simulator](https://reader031.fdocuments.net/reader031/viewer/2022012313/55a8d63c1a28abd7778b476c/html5/thumbnails/2.jpg)
Outline Introduction Simulator Workload Metrics Design alternatives Implementation Results Analysis Conclusion & Future work
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![Page 3: Cache Performance Evaluation under Multi-parameters Using SMPCache simulator](https://reader031.fdocuments.net/reader031/viewer/2022012313/55a8d63c1a28abd7778b476c/html5/thumbnails/3.jpg)
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Why cache ?
High cache performance leads to high total system performance
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Cache performance parameters
Cache size Cache block size Cache levels Cache mapping Replacement policy Unified cache or splittedVery big range of combinations, so we need to
parameter performance evaluation.
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Outline Introduction Simulator Workload Metrics Design alternatives Implementation Results Analysis Conclusion & Future work
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![Page 6: Cache Performance Evaluation under Multi-parameters Using SMPCache simulator](https://reader031.fdocuments.net/reader031/viewer/2022012313/55a8d63c1a28abd7778b476c/html5/thumbnails/6.jpg)
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SMPCache simulator Trace driven simulatorWindows compatibleUser friendly interfaceWide range of configurationUniprocessor build in memory tracesMultiprocessor downloaded memory tracesCreating your own memory tracesText and graph results
Simulator
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SMPCache User-friendly interface
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Organization of memory SMP or DSM
Number of processors 1, 2, 4, 8, 16, 32, 64 or 128
Snoopy Protocol MSI, MESI or DRAGON
Bus arbitration random, LFU or LRU
Directory protocol SGI or offWord Width (bits( 8, 16, 32 or 64Words in a block 1, 2, 4, 8, 16, 32, 64, 128, up to 1024
Memory Blocks 1, 2, 4, 8, 16, 32, 64, up to 4194304.
Cache Levels 1, 2, 3 or 4Unified or splitted unified or data and instructions
Cache Blocks 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 or 2048
Mapping Direct, set-associative or fully associative
Cache sets in case of set-associative mapping
Replacement policy Random, LRU, LFU or FIFOWriting strategy Writeback
Architectural characteristics supported by SMPCache
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Outline Introduction SMPCache Simulator Workload Metrics Design alternatives Implementation Results Analysis Conclusion & Future work
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Memory traces from SPEC’92 Benchmarks
Uni-processor tracesReal applicationsBuild in simulator softwareDifferent types of applicationsInteger and floating pointExamples: Hydro, Nasa7, Cexp, Mdljd, Ear,
Comp, Wave, Swm and UComp
Workload
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Outline Introduction SMPCache Simulator Workload Metrics Design alternatives Implementation Results Analysis Conclusion & Future work
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Miss rate
Less miss rate less main memory access indication on execution delay less ink in the final graph
Metric performance
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Outline Introduction SMPCache Simulator Workload Metrics Design alternatives Implementation Results Analysis Conclusion & Future work
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Design alternatives for Cache size factor
Main memory size 64 Gbytes
Block size 16 Kbytes
Cache mapping fully associative
cache replacement Policy LRU
Cache levels 1
Cache levels size 16 / 32 / 64 / 128 / 256 / 1000 Kbytes
Memory traces Comp/Nasa7/hydro
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Design alternatives
for Cache multi-level factor
Main memory size 64 Gbytes
Block size 16 Kbytes
cache mapping fully associative
cache replacement Policy LRU
Cache levels 1/2/3/4
Cache levels size 16 / 32 / 64 / 128 Kbytes in order
Memory traces Comp/Nasa7/hydro
16 / 32 / 64 / 128 Kbytes
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Design alternatives
for Cache maping factor
Main memory size 64 Gbytes
Block size 16 Kbytes
cache mapping direct , 2,4,8,16,32 set associatiev and fully associative
cache replacement Policy LRU
Cache levels 1
Cache levels size 16 Kbytes
Memory traces Comp/Nasa7/hydro
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Outline Introduction SMPCache Simulator Workload Metrics Design alternatives Implementation Results Analysis Conclusion & Future work
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ImplementationIn each simulation experiment
Determine Main memory cache configuration Select the desired option from list menu Run the simulation Record the result
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Outline Introduction SMPCache Simulator Workload Metrics Design alternatives Implementation Results Analysis Conclusion & Future work
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![Page 20: Cache Performance Evaluation under Multi-parameters Using SMPCache simulator](https://reader031.fdocuments.net/reader031/viewer/2022012313/55a8d63c1a28abd7778b476c/html5/thumbnails/20.jpg)
An Example of one experiment result
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Cache Performance whencache size is changed
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Cache Performance whencache levels is changed
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Cache Performance when cache mapping is changed
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Outline Introduction SMPCache Simulator Workload Metrics Design alternatives Implementation Results Analysis Conclusion & Future work
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Higher cache performance Higher cache size Higher cache levels Higher associativity - But there is a ”Tradeoff”
Conclusion
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Evaluate cache performance by studying More factors
Factor interaction
Future Work
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Any Question?
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Eng. Aiesha F. Al-maslam