Cache Memory and Bus Interface...
Transcript of Cache Memory and Bus Interface...
32-bit Embedded Core Peripheral
Cache Memory and Bus Interface Unit
Rev. 1355A–03/01
Features• 8 KB Memory Size (Optional 2 KB, 4 KB, 16 KB and 32 KB)• Four-way Parallel Associative Cache Memory and Four-word Burst
External Access on Miss• Write-back Algorithm• Enhanced External Bus Access• ARM740-compatible Configuration and MPU Structure• Memory Protection Unit (MPU) with Eight Programmable Areas
DescriptionThe cache memory and bus interface unit extends the capabilities of the ARM7TDMI™
processor by adding to it an 8 KB, four-way, parallel associative cache memory, amemory protection unit and an AMBA™ ASB bus interface unit. The ARM7TDMI pro-cessor, together with the cache memory unit, is software- and hardware-compatiblewith the ARM740T™ processor. The cache memory unit, which does not require theuse of tri-state buses, decodes the ARM7TDMI co-processor interface and extendsthe instruction set of the original ARM7TDMI. The cache memory unit is designedspecifically for ASIC development.
Figure 1. Block Diagram
ARMInterface
Co-processor Interface
Control
Address
Data
ASB Control
ASB BA
ASB D
AMBA ASBInterface
ARM7TDMICPU
Cache Memoryand
Bus Interface Unit To
System
R
1
Signal Description Table 1. ARM Interface
Name Type Description
A<31:0> I ARM7TDMI address bus. Addresses must become valid during phase 2 of the cycle preceding that to which they refer (APE = 1).
ABORT O Abort signal for the ARM7TDMI. It signals that the requested access is not allowed.
CPA O ARM7TDMI co-processor interface (co-processor absent)
CPB O ARM7TDMI co-processor interface (co-processor busy)
DO<31:0> O Data bus to ARM7TDMI
DI<31:0> I Data bus from ARM7TDMI
LOCK I Lock signal from ARM7TDMI. The processor is performing a “locked” memory access.
MAS<1:0> I Memory access size
MCLK O Clock signal for the ARM7TDMI
nCPI I ARM7TDMI co-processor interface
nMREQ I Valid memory access
nOPC I ARM7TDMI co-processor interface (opcode fetch)
nRESET O Reset signal for the ARM7TDMI
nRW I Not read/write access cycle
nTRANS I Not memory translate. When low, the processor is in user mode, and no co-processor instructions are supported.
nWAIT I Wait cycle for the ARM7TDMI
TBIT I ARM7TDMI is executing in Thumb® mode. No co-processor instructions are supported.
Table 2. AMBA ASB Interface
Name Type Description
AREQ O ASB bus request
AGNT I ASB bus grant
BA<31:0> O ASB address bus
BCLK I/O ASB clock
BDO<31:0> O ASB data bus output
BDI<31:0> I ASB data bus input
BERROR I Error response. A transfer error is indicated by a selected bus slave.
BLAST I Last response. This signal is driven by the selected bus slave to indicate that the current transfer should be the last of a burst request.
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Cache Memory
AMBA ASB Interface
The ASB bus interface is defined by ARM Ltd. in its AMBA Specification (Rev. 2.0). The cachememory unit IP follows this specification apart from one restriction: No retract or last responsecycles are supported.
The cache memory unit provides an interface that is uni-directional and fully synchronous withthe falling edge of BCLK. The conversion to a full ASB interface with tri-state buses is easy,requiring only a few additional tri-state buffers at the outputs. For a description of the differ-ences between multiplexer bus and tri-state bus implementation, refer to the application noteon AMBA interconnection schemes provided by ARM.
No test support is provided through the ASB, so the cache must be tested by using conven-tional scan paths and memory BIST.
Configuration Configuration and operation of the cache memory unit is controlled via co-processor 15(CP15). Co-processor instructions are used to manipulate a number of on-chip registers,which control the configuration of the following:
• the cache
• the protection unit
• a number of other configuration options
To ensure backwards compatibility of future CPUs, all reserved or unused bits in registers andco-processor instructions should be programmed to 0.
Invalid registers must not be read/written.
Note that the areas filled in with “–” in the register diagrams are reserved and should be pro-grammed 0 for future compatibility.
BLOK O Locked transfer. This signal indicates that the current transfer and the next transfer are to be indivisible and no other bus master should be given access to the bus.
BnRES I Bus reset signal
BPROT<1:0> O Protection control (opcode-data fetch, user-privileged mode)
BSIZE<1:0> O Bus size. Indicates the size of the transfer (byte, half-word, word).
BTRAN<1:0> O Transfer type. Address-only, non-sequential, sequential.
BWAIT I Wait response. The bus slave indicates if the current transfer may complete.
BWRITE O Write/read transfer
Table 2. AMBA ASB Interface (Continued)
Name Type Description
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Internal Co-processor Instructions
On-chip configuration registers may be read using MRC instructions and written using MCRinstructions. However, these operations are only allowed in non-user modes, and the unde-fined instruction trap is taken if access is attempted in user mode.
Format of Internal Co-processor Instructions MRC and MCR
• Bits 31..28 – COND: ARM condition codes
• Bit 20 – n
1 = MRC register read
0 = MCR register write
• Bits 19..16 – CRn: CP15 Source/Destination Register
This field is normally used to determine which configuration register is being accessed.
• Bits 15..12 – Rd: ARM Register
• Bits 3..0 – CRm: CP15 Operand Register
31 30 29 28 27 26 25 24
COND 1 1 1 0
23 22 21 20 19 18 17 16
– – – n CRn
15 14 13 12 11 10 9 8
Rd 1 1 1 1
7 6 5 4 3 2 1 0
– – – 1 CRm
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Cache Memory
Registers The configuration registers are accessed by CPRT instructions to CP15, with the processor inprivileged mode.
Only some of the CRn registers, however, are valid:
• An attempt to access an invalid register results in neither the access nor an undefined instruction trap being obtained and therefore should never be made.
• An attempt to access any of the registers [8:15] results in the undefined instruction trap.
Register 0: ID RegisterRegister Name: ID Register
Access Type: Read-only
Register 0 is a read-only identity register that returns the ID code for this IP.
Note: The variable x represents the version number.
Table 3. System Control Registers
Register Register Reads Register Writes
0 ID Register Reserved
1 Control Control
2 Cacheable Cacheable
3 Reserved Reserved
4 Reserved Reserved
5 Protection Protection
6 Memory area definition Memory area definition
7 Reserved Flush unlocked cache banks
8 - 15 Reserved Reserved
Table 4.
Cache Variant ID Code
2 Kb 0xFF1C740x
4 Kb 0xFF2C740x
8 Kb 0xFF3C740x
16 Kb 0xFF4C740x
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Register 1: Control RegisterRegister Name: Control Register
Access Type: Read/write
Register 1 contains the control bits. All bits in this register are forced low by reset.
• Bits 29..28 – Bank: Cache Bank Select Register
This field controls the cache. See “Partially Locked Operation” on page 11.
• Bit 27 – F: Load Mode
This bit controls the cache. See “Partially Locked Operation” on page 11.
• Bits 26..25 – Lock: Lock Cache Lockdown Control Register
This field controls the cache. See “Partially Locked Operation” on page 11.
• Bit 24 – S: Split Instruction Data Mode
This bit controls the operating mode of the cache. See “Split-instruction Data Operation” on page 12.
• Bit 7 – B: Big-/Little-endian
0 = Little-endian operation
1 = Big-endian operation
• Bit 3 – W: Reserved
• Bit 2 – C: Cache Enable/Disable
0 = Cache disabled
1 = Cache enabled
• Bit 0 – M: Protection Unit Enable/Disable
0 = On-chip protection unit disabled
1 = On-chip protection unit enabled
31 30 29 28 27 26 25 24
– – Bank F Lock S
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
B – – – W C – M
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Register 2: Cacheable RegisterRegister Name: Cacheable Register
Access Type: Read/write
Register 2 contains the current values of the cacheable bit. See “Protection Unit Registers” on page 14 for a description ofthe operation of the Protection Unit.
Register 3: ReservedThis register is reserved.
Register 4: ReservedThis register is reserved.
Register 5: Protection RegisterRegister Name: Protection Register
Access Type: Read/write
Register 5 contains the access permissions for the eight areas of memory. The access permission bits are defined in the“Protection Register” on page 15.
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
7 6 5 4
7 6 5 4 3 2 1 0
3 2 1 0
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Register 6: Memory Area Definition RegisterRegister Name: Memory Area Definition Register
Access Type: Read/write
Register 6 is actually eight physical registers that are referenced by the CRm field of a CPRT instruction. Each registerdefines a memory area. A complete description of these registers is given in “Area Registers” on page 16.
When programming the Memory Area Register, the appropriate region is selected using the CRm parameter in the MCR orMRC instruction.
Register 7: IDC Flush RegisterRegister Name: IDC Flush Register
Access Type: Write-only
Register 7 is a write-only register. The data written to this register is discarded and all unlocked banks of the cache areflushed.
Registers (8:15): ReservedAccessing any of these registers causes the undefined instruction trap to be taken.
31 30 29 28 27 26 25 24
Base[31:12]
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
– – – –
7 6 5 4 3 2 1 0
7 6 Size[4:0] E
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Cache Memory
Cache Memory Unit
The cache memory unit incorporates either an 8K or 4K general-purpose cache. Both variantsare functionally equivalent.
The cache memory:
• is physically addressed
• is four-way parallel associative
• is write-back
• has four words and a valid flag per line
• uses a random replacement algorithm
• is filled line by line
Three operating modes are provided so that the cache can be adapted to the application:
• Mixed-instruction data mode
• Partially locked mode
• Split-instruction data mode
The cache memory unit control register is used to enable/disable and configure the cache.Cache operation can also be controlled by the cacheable function of the protection unit. Theprotection unit must always be enabled if the cache is enabled. Otherwise, behavior is unde-fined. Both functions may be enabled simultaneously with a single write to the control register.
The cache memory uses a random replacement algorithm. The various operating modes alluse random allocation. In every case, the options only affect cache replacements. The com-plete cache is always searched for an address, and if the address is found, the data is used orupdated. This ensures that the cache is internally consistent and coherent with externalmemory.
Read-lock-write The read-lock-write instruction is treated by the IDC as a special case. Externally the twophases are flagged as indivisible by asserting the BLOK signal. The read phase always forcesa read of external memory, regardless of whether the data is contained in the cache. The writephase is treated as a normal write operation and if the data is already in the cache, the cachewill be updated.
Reset The IDC is automatically disabled and flushed on BnRES. Once enabled, cacheable readaccesses place lines in the cache.
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Figure 2. Cache Memory Block Diagram
Data pathASB
Interface
Access Control
TagMemory
DataMemory
MPU
ARM Interface
ASBAddress
ASBControl
ASBData
AMBA ASB Interface
Address
Data
Control
Miss
Cacheable
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Control Registers The cache is controlled by the following bits in the control register.
Operating Modes The following operating modes are provided so that the cache can be adapted to theapplication:
• Mixed-instruction data
• Partially locked
• Split-instruction data
Mixed-instruction Data Operation
This is the standard operating mode for the cache. In this mode, the cache functions as a stan-dard mixed-instruction and data cache. Lines fetched into the cache are placed at random intoone of the cache banks.
Partially Locked Operation
In this mode, critical code and data can be locked into the cache to ensure high performance.
To lock code or data into the cache:
1. Select the bank to be loaded using the Bank[1:0] register and set the F bit to 1. Cache banks are always locked starting from bank 0, hence should be loaded and locked in the order 0, 1, 2.
2. Perform a cache flush operation. This is necessary to ensure that the required instruc-tions and data are loaded into the selected cache bank. If this is not performed, they may be elsewhere in the cache and therefore not loaded into the selected bank.
3. Load the instructions or data to be locked into the cache using either LDM or LDR instructions, one per line. While in load mode, all instruction fetches are uncacheable.
Table 5. Control Register Bit Description
Bit Name Description
Bank[1:0] These bits select the bank to be loaded when the F bit is set.
Note: The cache banks are always locked starting from bank 0, so the order of loading should be 0, 1, 2.Although bank 3 can be loaded, there is no mechanism for locking all four cache banks.
C Cache Enable Bit. The cache is filled when a cacheable (instruction or data) fetch is performed. The cache is loaded by a line fetch of four words.
F This bit forces all line fetches to apply to the bank selected by Bank[1:0]. When this bit is set, all instruction fetches are forced to be “uncacheable” data fetches and are still subject to the cacheable mapping in the protection unit.
Lock[1:0] These bits are used to set the number of banks locked. When in split-instruction data mode, they are also used to program the split. Table 5 shows the effect of using the Lock[1:0] bit to lock cache banks.
S This is the split-instruction data bit. When this bit is set, the cache is configured according to the value of the Lock[1:0] bits. It is illegal to have F and S set simultaneously. The effects of the Lock[1:0] bits when in split- instruction data mode is shown in Table 7. For a full description of the configuration register, see See “Register 1: Control Register” on page 6.
Table 6. Cache Banks Locked by Lock[1:0]
Lock[1:0] Bank 3 Bank 2 Bank 1 Bank 0 Description
00 Cache Cache Cache Cache No Banks Locked
01 Cache Cache Cache Locked 1 Bank Locked
10 Cache Cache Locked Locked 2 Banks Locked
11 Cache Locked Locked Locked 3 Banks Locked
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4. Set the F bit to zero.
5. Set the number of banks to be locked into the Lock[1:0] register.
6. Once the lock register is set, the replacement algorithm is prevented from making replacements in the locked banks. This results in reducing the associativity of the cache to the number of banks remaining as cache.
Split-instruction Data Operation
Another option allows the cache memory unit to be operated in split-instruction data mode.This forces instructions and data to be cached in separate banks of the cache and is used toimprove performance where a small code set is processing a large data set. The split nature ofthe cache means that data does not replace the cached instructions. The allocation of thebanks of the cache is shown in Table 7.
It is not necessary to flush the cache before enabling the split-instruction data mode since thecomplete cache is searched, regardless of the split selected.
1. Set the S bit.
2. Select the required split using the Lock[1:0] register.
If required, this mechanism can be used to make a snapshot of the contents of the instructionbanks and to lock them into the cache. The required sequence of operations is as follows:
1. Set the S bit to 1 and select the required split using the Lock[1:0] register.
2. Flush the cache to ensure that the code is loaded into the instruction banks.
3. Execute the required code fragment.
4. Set the S bit to 0, leaving the same value in the Lock[1:0] register.
In all cases, when operating in split-instruction data mode, the associativity of each section ofthe cache is equal to the number of banks allocated to it.
Notes: 1. It is illegal to simultaneously have the S bit and the F bit set.2. It is illegal to have the S bit set with a value of 00 in the Lock[1:0] register.
Table 7. Bank Allocation in Split-instruction Data Mode
Lock[1:0] Bank 3 Bank 2 Bank 1 Bank 0 Description
00 – – – – Reserved
01 Data Data Data Instruction 1 Bank Instruction, 3 Banks Data
10 Data Data Instruction Instruction 2 Banks Instruction, 2 Banks Data
11 Data Instruction Instruction Instruction 3 Banks Instruction, 1 Bank Data
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Cache Operation The cache is always searched regardless of whether it is enabled. If an address hits, then thedata will be read or written. So when the cache is disabled it should also be flushed. A sum-mary of cache operations is found in Table 8.
Cacheable Bit The appropriate cacheable bit in the cacheable register is used by the protection unit to deter-mine whether data being read may be placed in the IDC and used for subsequent readoperations.
To improve system performance, main memory is generally marked as cacheable and I/Ospace as non-cacheable to stop the data from being stored in the cache memory unit. Forexample, if the processor is polling a hardware flag in the I/O space, it is important that theprocessor is forced to read data from the external peripheral and not a copy of the initial dataheld in the cache. See “Memory Protection Unit” on page 14 for more details.
Software IDC Flush All unlocked banks of the cache may be marked as invalid by writing to the cache memoryunit’s IDC Flush Register (Register 7). See “Register 7: IDC Flush Register” on page 8. Thecache is flushed immediately as the register is written, but note that the following two instruc-tion fetches may come from the cache before the register is written.
Table 8. Cache Operations
Cacheable Reads A line fetch of four words is performed when a “cache-miss” occurs in a cacheable area of memory. This is placed in the cache according to the current mode of operation.
Uncacheable Reads An external memory access is performed and the cache is not written.
Writes All writes update the data in the cache if present and are written through to the main memory.
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Memory Protection Unit
By maintaining a description of the properties of memory areas in the memory map, the mem-ory protection unit has two primary functions:
• Control of the cache and write buffer
• Control of memory access permissions
The MPU provides individual control for eight areas of memory numbered 0 to 7. For eacharea, the following registers can be programmed:
• Cacheable
• Basic Protection
• Size
• Base Address
In this way, the memory architecture of the system can be described in an easily programma-ble but flexible manner.
Protection Unit Registers
Several registers are provided by the cache memory unit to control the operation of the protec-tion unit. The format of these registers is shown in Table 3, “System Control Registers,” onpage 5.
For a complete description of the control co-processor, see “Configuration” on page 3.
Control RegisterRegister Name: Control Register
Access Type: Read/write
The configuration register contains the protection enable bit M. On reset, this bit is set to zero, disabling the protectionmechanisms and allowing full access to all of the memory. All accesses are then uncacheable and unbufferable.
Note that other bits in the configuration register are also used for other functions. For a full description of the configurationregister, see “Register 1: Control Register” on page 6.
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
– – – – – – – M
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Cacheable RegisterThis register is used to set the cacheable bit for each of the eight areas of memory.
The cacheable bit determines if a line fetch should be performed for an access to a given area of memory. The cache isalways searched regardless of the state of this bit, and if the required address is found, the copy of the data in the cache willbe used.
On reset, all areas are marked as uncacheable. Main memory is typically marked as cacheable to provide maximum perfor-mance, while peripherals are marked as uncacheable.
Protection RegisterThis register controls the access permissions for the eight areas of memory.
Access permissions for each area of memory are controlled by the value in the protection register. The control accessesare shown in Table 9.
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
7 6 5 4
7 6 5 4 3 2 1 0
3 2 1 0
Table 9. Access Permission
Value Supervisor User
00 No access No access
01 Read/write No access
10 Read/write Read-only
11 Read/write Read/write
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Area Registers The area registers are used to control the parameters of the memory areas controlled by theprotection unit. These registers differ from the other CP15 registers with respect to the waymemory areas are addressed. Instead of separate bit-fields being used for each region ofmemory, one register is used for each area indexed by the co-processor operand parameter inthe instruction.
The number of the memory area to be accessed should be placed in the CP15 operand field ofthe instruction. See “Internal Co-processor Instructions” on page 4.
where:
• Bits 31..28 – COND: ARM Condition Code
• Bit 20 – n:
1 = MRC register read
0 = MCR register write
• Bits 19..16 – CRn: CP15 Source/Destination Register
This field is equal to six for the area register.
• Bits 15..12 – Rd: ARM Register
• Bits 3..0 – CRm: CP15 Operand Register
This field is set to the area to be accessed.
31 30 29 28 27 26 25 24
COND 1 1 1 0
23 22 21 20 19 18 17 16
– – – n CRn
15 14 13 12 11 10 9 8
Rd 1 1 1 1
7 6 5 4 3 2 1 0
– – – 1 CRm
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Each area register uses three fields to describe the location of the area of memory:
• enable bit E
• size of the area
• base address of the area
The enable bit E determines if a given area is active. If this bit is set to zero, the area isdisabled.
The value in Size[4:0] determines the size of a given area of memory, as shown in Table 10.
Base Address The base address of each area must be aligned with respect to the size of that area. Forexample, if a region size is set to 16K, then 0x8000 is a legal address for the region to start,but 0x5000 is not legal.
The finest resolution that can be used to set the location of a section is 4K, as determined bythe setting for the smallest region. If this requirement is not met, the behavior of the protectionunit is undefined.
31 30 29 28 27 26 25 24
Base[31:12]
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
– – – –
7 6 5 4 3 2 1 0
7 6 Size[4:0] E
Table 10. Area Sizes
Size[4:0] Area Size[4:0] Area
0b01011 4 Kb 0b10110 8 Mb
0b01100 8 Kb 0b10111 16 Mb
0b01101 16 Kb 0b11000 32 Mb
0b01110 32 Kb 0b11001 64 Mb
0b01111 64 Kb 0b11010 128 Mb
0b10000 128 Kb 0b11011 256 Mb
0b10001 256 Kb 0b11100 512 Mb
0b10010 512 Kb 0b11101 1 Gb
0b10011 1 Mb 0b11110 2 Gb
0b10100 2 Mb 0b11111 4 Gb
0b10101 4 Mb
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Accessing the Area Register
This register is accessed using MCR and MRC instructions as follows:
• To write the descriptor for an area of memory:MCR p15, 0, Rd, c6, CRm, 0
where:
- CRm is the area of memory to be defined
- Rd is the ARM register containing the value to be written into the area register
• To read back the descriptor:MRC p15, 0, Rd, c6, CRm, 0
where:
- CRm is the area of memory to be read
- Rd is the ARM register where the descriptor is placed
Protection Unit Operation
The protection unit compares the address generated by the ARM with the parameters of theeight memory areas. This produces one of three results as shown in Table 11.
The protection unit operation is illustrated in Figure 3.
Figure 3. Protection Unit Operation
Table 11. Protection Unit Operation
No area hits The access is aborted
One area hit The properties of this area are applied to the access
Multiple areas hit The properties of the highest priority area are applied to the access.
Access to Area 5
Access to Area 0(Background Permissions)
Access to ,Area 4(Highest Priority Area)
Are
a 0
Are
a 1
Are
a 2
Are
a 3
Are
a 4
Are
a 5
Are
a 6
Are
a 7
4GB
Add
ress
Spa
ce
0
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Memory Area Properties
Each area of memory is defined in terms of the following properties:
• base address
• size
• access permissions
• bufferable bit
• cacheable bit
An area’s base address must be a multiple of its size. When an address matches multipleareas of memory, the properties of the highest priority area of memory are used. Area priori-ties are fixed as follows:
• area 7 has the highest priority
• area 0 has the lowest priority
The bufferable and cacheable bits for the selected area of memory are used to determine ifthe cache and write buffer should be used (if enabled).
Access Permissions Access permission bits are checked against access type. Details of decoding are found inTable 9, “Access Permission,” on page 15.
• If access is permitted, the ARM continues.
• If access is prohibited, the ARM is aborted and there is no access on the external bus.
Protection Failures and External Accesses
If an access violation is detected by the protection unit, access is then inhibited to the externalmemory. External aborts, however, do not necessarily inhibit the external access, asdescribed in “External Aborts” on page 20.
An internally aborting access may cause the address on the external address bus to change,even though the external bus cycle has been cancelled. No memory access is performed tothis address.
Reset The protection unit is disabled on BnRES. Before it is enabled, all the protection unit registersmust be programmed. If this is not respected, unpredictable behavior will result.
Overlapping Memory Regions
When mapping logical memory regions into physical memory devices, overlapping regionscan be used to allow greater flexibility. For example, consider the case where the system has4K of supervisor code and 28K of user code, both of which must be mapped into a 32K RAM.
If overlapping memory is not supported, four regions would have to be used to achieve this:
• one 4K region for the supervisor code
• one 32K region
• one 16K region
• one 4K region for the user code
Table 12. Cacheable and Bufferable Properties
Property Effect if Set
Bufferable If the access is a write, the write buffer will be used.
Cacheable If the access is a read, a cache line fill will be performed if the required word is not in the cache.
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If the supervisor and user code regions can be overlapped, this can be achieved using onlytwo regions:
• one 4K region for the supervisor code
• one 32K region for the user code
Thus in Figure 4, by way of example, the supervisor code could be placed in Region 2, and theuser code in Region 1. This would ensure that the supervisor mapping takes precedence overthe less strict user mapping.
Figure 4. Use of Overlapping Memory Regions
Undefined Address Space
The default protection for otherwise unmapped memory can be programmed by using themechanism for overlapping segments. If the memory regions do not completely fill the 4 GB ofaddress space of the ARM7TDMI, there are “holes” in the address map. By configuring Region0 (the lowest priority region) to be 4 GB in size, the user can program what happens if anaccess becomes a “hole”.
For example, the attributes could be set to full access or no access. Alternatively, the usermay choose to ignore the holes, and any access to an area of memory not described by theprotection unit results in an abort.
External Aborts In addition to the aborts generated by the protection unit, the cache memory unit has an exter-nal abort input BERROR that may be used to flag an error on an external memory access.However, not all accesses can be aborted in this way, so this input must be used with greatcare.
Restrictions The following accesses may be aborted and restarted safely:
• reads
• unbuffered writes
• read-lock-write sequence
If any of these are aborted, the external access ceases on the next cycle. In the case of aread-lock-write sequence in which the read aborts, the write does not occur.
Cacheable Reads (Line Fetches)
A line fetch may be safely aborted on any word in the transfer:• If an abort occurs during the line fetch, the cache is purged, so it does not contain invalid
data.
• If the abort happens on a word that has been requested by the cache memory unit, it is aborted. Otherwise, the cache line is purged but program flow is not interrupted.
The line is therefore purged under all circumstances.
1
2
4
1
23
Four RegionsRequired
Two Regions Required
Supervisor Only
Full Access
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Cache Memory
Performance and Waveforms
Performance Performance is expressed in terms of the number of clock cycles per hit access or missaccess.
Number of clock cycles per hit access:
• Read access: 1 cycle (0 wait states)
• Write access: 2 cycles (1 wait state)
Number of clock cycles per miss access:
• Miss-on-read access without line replacement: 5 cycles + (access time for 4-word read burst from external memory)
• Miss-on-write access without line replacement: 6 cycles + (access time for 4-word read burst from external memory)
• Miss (read or write) and line replacement: 6 cycles + (access time for 4-word read burst from external memory) + (access time for 4-word write burst to external memory)
For non-cacheable accesses, there is no penalty due to cache insertion. It is possible to workat zero wait states in read and write. This depends only on required external wait states.
Waveforms In order to improve visibility on waveforms, a zero-wait-states external memory is used in theexamples that follow.
Waveform Signals
Table 13. External Memory Bus (AMBA ASB)
xxx.cpu1.MCLK Main clock CPU bus and BCLK
xxx.cache.BA Address bus to external memory
xxx.cache.BDI Data bus from external memory
xxx.cache.BDO Data bus to external memory
xxx.cache.BTRAN Transfer type
xxx.cache.BWRITE Write signal
Table 14. ARM Side Bus
xxx.cpu1.A Address bus to cache
xxx.cpu1.D Data bus to/from cache
xxx.cpu1.nRW Write to cache
xxx.cpu1.nWAIT Wait from cache
xxx.cpu1.nMREQ Memory request to cache
xxx.cpu1.SEQ Sequential address to cache
211355A–03/01
Table 15. Internal Cache Memories
xxx.core.tagmem.miss Miss signal (active high)
xxx.core.datmem.ADD Internal data memory address
xxx.core.datem.DIN Data-to-data memory
xxx.core datem.DOUT Data-from-data memory
xxx.core datmem.WE Write enables to data memories (4 ways)
xxx.core.control.cacheable Cacheable signal (active high)
22 Cache Memory1355A–03/01
Cach
e Mem
ory
1355A–0
Fig
ure 5. M
iss-on-read Access
00000210 00000074
00002800
0
00000074
00002800
074210
00000005
00002800
66400000.00.0
233/0100000070 00000210 00000214 00000218 0000021c
00002800 00003000 00003800 00004000
e59f51a0
0 3
00000070 00000210
e59f51a0
MISS ON READ ACCESS
070 210 214 218 21c
00000005 00002800 00003000 00003800 00004000
e59f51a0
66150000.0 66200000.0 66250000.0 66300000.0 6635000
TEST_CACHE.cpu1.MCLK
TEST_CACHE.cache.BA
TEST_CACHE.cache.BDI
TEST_CACHE.cache.BDO
TEST_CACHE.cache.BTRAN
TEST_CACHE.cache.BWRITE
TEST_CACHE.cpu1.A
TEST_CACHE.cpu1.D
TEST_CACHE.cpu1.nRW
TEST_CACHE.cpu1.nWAIT
TEST_CACHE.cpu1.nMREQ
TEST_CACHE.cpu1.SEQ
cache.core.tagmem.miss
cache.core.datmem.ADD
cache.core.datem.DIN
cache.core.datem.DOUT
cache.core.datmemWE[3]
cache.core.datmemWE[2]
cache.core.datmemWE[1]
cache.core.datmemWE[0]
cache.core.control.cacheable
time (ps)
24
Fig
ure 6. M
iss-on-read Access and D
irty Line Replacem
ent (Write-back)
0
004008 0000400c 00004000
00
55555555
55555555
004 008 00c 000
00000000
55555555
73350000.0
Cach
e Mem
ory
1355A–03/01
00004000 00004000
55555555 aaaaaaaa 55555555 aaaaaaaa
0 3
MISS ON READ ACCESS AND DIRTY LINE REPLACEMENT (WRITE BACK)
aaaaaaaa 55555555 aaaaaaaa 55555555 aaaaaaaa
73050270.0 73100000.0 73150000.0 73200000.0 73300000.073250000.0
00003800 00003804 00003808 0000380c 00004004 00
000000
e088800aaaaaaaaa 55555555 aaaaaaaa55555555
00004000e088800a
aaaaaaaa 55555555 aaaaaaaa55555555
000 004 008 00c 000
e088800aaaaaaaaa 55555555 aaaaaaaa55555555
TEST_CACHE.cpu1.MCLK
TEST_CACHE.cache.BA
TEST_CACHE.cache.BDI
TEST_CACHE.cache.BDO
TEST_CACHE.cache.BTRAN
TEST_CACHE.cache.BWRITE
TEST_CACHE.cpu1.A
TEST_CACHE.cpu1.D
TEST_CACHE.cpu1.nRW
TEST_CACHE.cpu1.nWAIT
TEST_CACHE.cpu1.nMREQ
TEST_CACHE.cpu1.SEQ
cache.core.tagmem.miss
cache.core.datmem.ADD
cache.core.datem.DIN
cache.core.datem.DOUT
cache.core.datmemWE[3]
cache.core.datmemWE[2]
cache.core.datmemWE[1]
cache.core.datmemWE[0]
cache.core.control.cacheable
time (ps)
Cach
e Mem
ory
1355A–0
Fig
ure 7. W
rite-and-read Hit C
acheable Accesses
00004008 00000150
00000000
00004008 00000150
aaaaaaaa
aaaaaaaa
008 150
00000000
74100000.0
253/01
0
00004004 0000014c00000140
e3a08000 00000000 e797900800000000e7969008
2
00004004 0000400800000148 0000014c0000014400000140
e3a08000 00000000 e7979008e786c00855555555e7969008
e786c008
00000144 00000148 00004008
TEST_CACHE.cpu1.MCLK
TEST_CACHE.cache.BA
TEST_CACHE.cache.BDI
TEST_CACHE.cache.BDO
TEST_CACHE.cache.BTRAN
TEST_CACHE.cache.BWRITE
TEST_CACHE.cpu1.A
TEST_CACHE.cpu1.D
TEST_CACHE.cpu1.nRW
TEST_CACHE.cpu1.nWAIT
aaaaaaaa 55555555
004 008148 14c144140
e3a08000 00000000 e7979008e786c00800000000e7969008
73950000.073955014.0 73950000.0 74000000.0 74050000.0
WRITE AND READ HIT CACHEABLE ACCESSES
TEST_CACHE.cpu1.nMREQ
TEST_CACHE.cpu1.SEQ
cache.core.tagmem.miss
cache.core.datmem.ADD
cache.core.datem.DIN
cache.core.datem.DOUT
cache.core.datmemWE[3]
cache.core.datmemWE[2]
cache.core.datmemWE[1]
cache.core.datmemWE[0]
cache.core.control.cacheable
time (ps)
26
Fig
ure 8. M
iss-on-write A
ccess
03800
0
200000
13131313
00000200
00000200
50000.0 325100000.0
Cach
e Mem
ory
1355A–03/01
000001fc 00003800 00003804 00003808 0000380c 000
55555555 aaaaaaaa
01002000
0 3
00003800
1fc 000 004 008 00c
55555555 aaaaaaaa
55555555 aaaaaaaa
55555555
0 2
000001fc
01002000 13131313
06000005 1313313 aaaaaaaa55555555
01002000 55555555
MISS ON WRITE ACCESS
324850000.0 324900000.0 324950000.0 325000000.0 3250
TEST_CACHE.cpu1.MCLK
TEST_CACHE.cache.BA
TEST_CACHE.cache.BDI
TEST_CACHE.cache.BDO
TEST_CACHE.cache.BTRAN
TEST_CACHE.cache.BWRITE
TEST_CACHE.cpu1.A
TEST_CACHE.cpu1.D
TEST_CACHE.cpu1.nRW
TEST_CACHE.cpu1.nWAIT
TEST_CACHE.cpu1.nMREQ
TEST_CACHE.cpu1.SEQ
cache.core.tagmem.miss
cache.core.datmem.ADD
cache.core.datem.DIN
cache.core.datem.DOUT
cache.core.datmemWE[3]
cache.core.datmemWE[2]
cache.core.datmemWE[1]
cache.core.datmemWE[0]
cache.core.control.cacheable
time (ps)
Cach
e Mem
ory
1355A–0
Fig
ure 9. N
on-cacheable Accesses w
ith External Z
ero-wait-states M
emory
310650000.0.0
000001d4 00003640
e158000688800a
2
000001d4 00003640
e158000688800a
1d4 640
273/01
3 2
NON CACHEABLE ACCESSES WITH EXTERNAL 0 WAIT STATES MEMORY
310525000.0 310550000.0 310575000.0 310600000.0 310625000
000001d8 000001dc 000001e0 000001cc 000001d0
bafffffb e59f9054 ee019f11 e7949008 e0
28000005
3
000001d8 000001dc 000001e0 000001cc 000001d0
bafffffb e59f9054 ee019f11 e7949008 e000000000
1d8 1dc 1e0 1cc 1d0
28000005
00000000
TEST_CACHE.cpu1.MCLK
TEST_CACHE.cache.BA
TEST_CACHE.cache.BDI
TEST_CACHE.cache.BDO
TEST_CACHE.cache.BTRAN
TEST_CACHE.cache.BWRITE
TEST_CACHE.cpu1.A
TEST_CACHE.cpu1.D
TEST_CACHE.cpu1.nRW
TEST_CACHE.cpu1.nWAIT
TEST_CACHE.cpu1.nMREQ
TEST_CACHE.cpu1.SEQ
cache.core.tagmem.miss
cache.core.datmem.ADD
cache.core.datem.DIN
cache.core.datem.DOUT
cache.core.datmemWE[3]
cache.core.datmemWE[2]
cache.core.datmemWE[1]
cache.core.datmemWE[0]
cache.core.control.cacheable
time (ps)
© Atmel Corporation 2001.Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warrantywhich is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errorswhich may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and doesnot make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are grantedby the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as criticalcomponents in life support devices or systems.
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