C161 C166 C163 C164 C165 C167 HL MC AT, lehmann 16x_all.ppt 30.08.2015, 08:46 - 1 Microcontrollers...

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167

HL MC AT, lehmann16x_all.ppt19.04.23, 11:08

- 1Microcontrollers

C166 Family-High Performance 16-Bit Microcontrollers

SAB 8xC166SAB 8xC166 C167xC167x C165C165 C163C163 C164xC164x C161xC161x

SAB-C167CRSAB-C167CR

XRAMXRAM1KByte1KByte

XRAMXRAM1KByte1KByteRAMRAM

1KByte1KByte

RAMRAM1KByte1KByte

PWMPWM

ADCADC

CANCAN

BUS-BUS-CONTROLCONTROL

INTERRUPTINTERRUPTUNITUNIT

CAPCOMCAPCOM1+21+2

SSCSSC

USARTUSARTGPTGPT1+21+2

IR+PEC-IR+PEC-CONTROLCONTROL

ROMROM

WDTWDT

CORECORE

The Reference ClassThe Reference Class1

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167


- 2Microcontrollers

WDTOSC.PEC

CPUROM /

RAM

PORTS

CAPCOM

ADCBus

Ext..

Processor -System

Interrupt-System

USART GPTs

Peripheral-System

Flash

Control

X-Bus

Sync Communication PWMPeripheral.

C166 Family The Three Subsystems


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167


- 3Microcontrollers

WDTOSC.PEC

CPUROM /

RAM

PORTS

CAPCOM

ADCBus

Ext..

Processor -System

Interrupt-System

USART GPTs

Peripheral-System

Flash

Control

X-Bus

Sync Communication PWMPeriphrl.

Microcontrollers:

Control oriented instruction setoptimized event handling

“System on Silicon”

Microprocessors:

High computational powerhigh data throughput

good addressing capabilitiesHLL-supporting architecture

C166 Family The Best of Both Worlds


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167


- 4Microcontrollers

+ CAN

+ PWMMore I/OMore AD-Ch.

Different Mix

ProcessorCore

n x 4 KBROM

n x 512 BRAM

DowngradedCore

n x 8 KBFlash-EPROM

InternalROM

OSC.

Internal

RAM

PECInterrupt Controller WDT

PORTS

CAPCOM10-bitADCBus

Control

Ext..USARTs GPTs

CPU

The Modular Concept


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167


- 5Microcontrollers

Four Bus Modular SystemX Bus ModulesX Bus Modules

RAM1k

RAM1k

NewModules

Timers USART SSC

Ports NewModules

WDT

ADC

CAPCOM

XRAMSSP

NewModules

CAN

I²C

NewModules

ROM 8K

ROM 32K

Flash32K

Flash128K

NewModules

OTP 64K

Flash64K

CoreCore32

bit

32 b

it

16 - b i t16 - b i t

2x1

6 b

it2x

16

bit

16 - b i t16 - b i t

Basic Library ModulesBasic Library Modules


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167


- 6Microcontrollers

Low CostLow CostProcessor OrientedProcessor Oriented

* different RAM Size* up to 16 M Addr. Range* up to 5 Timers* Serial Interfaces SSP, SSC

C165C165* 2KB RAM* 3V* P-TQFP-100

* 1KB RAM* SSP* 3V* reduced Peripherals* P-TQFP-100

C163C163* less Chip Selects* full Bus Support/ MUX Bus only* 3 V Options* 25 MHz Option

* 16MHz CPU* 4 M address* 1-2KB RAM* Pwr. Man. / RTC* P-MQFP-80/100

C161xC161x

* CAPCOM* PWM* Serial Interfaces* Timer* 10-bit / 8bit ADC* full Bus Support/ MUX Bus only

8xC1668xC166* 1KB RAM* 32KB ROM* 32KB Flash* P-MQFP-100

Balanced Peripheralset for a broadApplication Ranges:Price differentiation:

* 1K / 2 KB RAM* ROM / Flash / OTP

General PurposeGeneral Purpose

C164C164* 2KB RAM* 64KB OTP/ROM/Flash* Full-CAN 2.0B active* Power Management / RTC* CAPCOM6* P-MQFP-80

* 16 M Address Range* 2/4 KByte RAM* 32 CAPCOM* 4 PWM* 2 Serial Interface* 5 Timer* Chip Selects Benefits in System Integration* Extensive I/O

C167CRC167CR* CAN* 4K RAM* PLL

C167SRC167SR* 2KB RAM* PLL

* 2KB RAM

C167C167C167SC167S

* 32K ROM* 2KB RAM* PLL

Highly IntegratedHighly Integrated

RoadmapRoadmap2

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167


- 7Microcontrollers

Numbering Scheme8xC166 Products

SABSAB

8080

8383

8888

C166C166

C166WC166W

C166C166

C166WC166W

C166C166

C166WC166W

(-)(-)

(-)(-)

55

55

55

55

MM

MM

MM

MM

MM

MM

(-)(-)T3T3

(-)(-)T3T3T4T4

(-)(-)T3T3T4T4

(-)(-)T3T3

(-)(-)

(-)(-)

Prefix Memory Type Memory Package Temp.Range

Type Code Designation Size Code Code Code

W = without prescaler M = Metric Quad Flatpack

ROMLess

Flash EEPROM

Metal Mask ROM

32KBytes

(-) no suffix

-40° / 110°

-40° / 85° 0° / 70°

-40° / 85° 0° / 70°

-40° / 110°-40° / 85° 0° / 70°-40° / 85° 0° / 70°

0° / 70°

0° / 70°

OverviewOverview3

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167


- 8Microcontrollers

**difference later onin this Foilset

PrefixPrefix Temp. Range Temp. Range Type Type Memory Code Memory Code CPU CPU PackagePackage CodeCode Designation Designation Size Size Type Type Freq. Freq. Code Code

B = 0/ 70 °CF = -40/ 85 °C

M = Metric Quad FlatpackF = Thin Quad Flatpack

L = ROMlessR = MASK ROMF = FLASH

(-) = 0kB16 = 128kB

BB C161V / K / O*C161V / K / O* LL 1616 MM(-)(-)

SASA

B,FB,F C165C165 RRLL

(-)(-)

2525(-)(-)

M,FM,FM,FM,F

C163C163 LLLL

2525(-)(-)

FF FF

B,FB,F BB

(-)(-) (-)(-)

Numbering SchemeC161/C163/165 Products

OverviewOverview3

FF FF B,FB,F 1616

128kB FLASH

4KB Metal Mask ROM

2525

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167


- 9Microcontrollers

Numbering SchemeC164 Products

PrefixPrefix Temp. RangeTemp. Range Type Type Memory Code Memory Code CPU CPU Package PackageCodeCode Designation Designation Size Size Type Type Freq. Freq. Code Code

SASA

64KB OTP

B,F,H,K B,F,H,K C164CIC164CI EERR

LL 88 88

(-)(-)(-)(-)(-)(-)

(-)(-)M,FM,FM,FM,F

M,FM,F

B = 0/ 70 °CF = -40/ 85 °CH = -40/ 110°CK = -40/ 125°C

M = Metric Quad FlatpackF = Thin Quad Flatpack

L = ROMlessR = MASK ROME = EPROM

(-) = 0kB 8 = 64kB

OverviewOverview3

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167


- 10Microcontrollers

Prefix Temp. Range Type Memory Code Package

Code Designation Size Type Code

SASA

B,FB,F C167C167 (-)(-) LL MM

BB C167CRC167CR 16*16* FF MM

B, F, K B, F, K C167CRC167CR(-)(-) LL MM4*4* R*R* MM

B,F,KB,F,K C167SRC167SR (-)(-) LL MM

B, F,KB, F,K C167CRC167CR 16*16* R*R* MM

B= 0/ 70 °CF= -40/ 85 °CK= -40/110 °C

C= CAN InterfaceR= 2KBytes XRAM

M= Metric Quad Flatpack

32KBytes

ROMLess

Flash

Mask ROMBB C167SC167S 44 MMRR

128KBytes

Numbering SchemeC167 Products

OverviewOverview3

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167


- 11MicrocontrollersOverview -Overview - C161V Block Diagram

6

4

16

161V

Por

t 6P

ort 0

Por

t 4

Port 1 Port 5 Port 3

CPU

Dua

l Por

t

RAM

1 KByte

Interrupt ControllerWatchdog

Peripheral Data

External Instr./Data

Instr./Data

USART

ASC

BRG

GPT1

16 2 12

16

16

16

1632

PEC

no

ROM

Interrupt Bus

Data

Data

Port 2

7

BRG

SSC

Sync. Channel(SPI)

OSCinput: 16MHz;

prescaleror direct drive

XB

US

(16

-bit

NO

N M

UX

Dat

a / A

ddre

sses

)

External Bus,MUX only

XBUS Control,no CS Logic,

T2

T4

T3

5 ext. IR

noX

-Bus

Per

iphe

ral

C166-C166-CoreCore

XTAL

3

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167


- 12MicrocontrollersOverview -Overview - C161K Block Diagram

161K

C166-CoreC166-Core


CPU

Dua

l Por

t

RAM

1 KByte


Peripheral Data


Instr./Data

USART

ASC

BRG

GPT1

16 2 12

16

6

4

16

16

16

1632

PEC

no

ROM

Interrupt Bus

Data

Data

Port 2

7

BRG

SSC

Sync. Channel(SPI)

OSC(input: 16MHz;

prescaleror direct drive)

XB

US

(16

-bit

NO

N M

UX

Dat

a / A

ddre

sses

)

External Bus,XBUS Control,2 x CS Logic

T2

T4

T3

5 ext. IR

noX

-Bus

Per

iphe

ral

XTAL

3

Por

t 6P

ort 0

Por

t 4

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



161O

C166-CoreC166-Core


CPU

Dua

l Por

t

RAM

2 KByte


Peripheral Data


Instr./Data

USART

ASC

BRG

GPT1 GPT2

16 2 12

16

6

4

16

16

16

1632

PEC

no

ROM

Interrupt Bus

Data

Data

Port 2

7

BRG

SSC

Sync. Channel(SPI)

OSC(input: 16MHz;


XB

US

(16

-bit

NO

N M

UX

Dat

a / A

ddre

sses

)


T2

T4

T3

11 ext. IR

noX

-Bus

Per

iphe

ral

T6

T5

XTAL

3Overview -Overview - C161O Block Diagram

Por

t 6P

ort 0

Por

t 4

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



7

8

16

161RI

C166-C166-CoreCore


CPU Dua

l Por

t

RAM

1 KByte

Interrupt Controller

Watchdog

Peripheral Data


Instr./Data

USART

ASC

BRG

GPT1 GPT2

16 6 15

16

16

16

1632

PEC

no

ROM

Interrupt Bus

Data

Data

Port 2

8

BRG

SSC

Sync. Channel(SPI)

OSC(input: 16MHz;


XB

US

(16

-bit

NO

N M

UX

Dat

a / A

ddre

sses

)


T2

T4

T3

11 ext. IR

T6

T5

I2C-Bus

XRAM2 KByte

RTC

8-bitADC

4 Channels

XTAL

3Overview -Overview - C161RI Block Diagram

Por

t 6P

ort 0

Por

t 4

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



RAM

1 KByte

163

PLLprogr. multiplier

(W/0.5/1.5/2/../5)

SSPModule

12.5 Mbit/s

Por

t 6P

ort 0

Por

t 4


CPU Dua

l Por

t


Peripheral Data


USART

ASC

BRG

GPT1

T3

T4

GPT2

T2

T5

T6

16 6 16

16

8

8

16

16

16

1632

PEC

up to

128 KByte

Flash

EPROM

Interrupt Bus

Data

Data

Port 2

8

Instr./Data

XB

US

(16

-bit

NO

N M

UX

Dat

a / A

ddre

sses

)

External Bus,XBUS Control,5 * CS Logic

11 ext. IR

C166-CoreC166-Core

XTAL

RAM

1 KByte

3Overview -Overview - C163 Block Diagram

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



164CL

XTAL

C166-C166-CoreCore

Por

t 0

Port 5 Port 3

CPU Dua

l Por

t

RAM

2 KByte


Watchdog

Peripheral Data


Instr./Data

USART

ASCBRG

GPT1

1616

16

1632

PEC

64 K ROM

(C164 Cl-8-RM)

or OTPC164-8EM)

Interrupt Bus

Data

Data

Port 8

BRGSSC

Sync. Channel

(SPI)

PLL-Oscillatorprog. Multiplier:

0.5; 1; 1.5; 2;2.5; 3; 4; 5

XB

US

(16

-bit

NO

N M

UX

Dat

a / A

ddre

sses

)

T2

T4

T3

13 ext. IRFull-CANInterface

V2.0Bactive

RTC

10-BitADC

Tim

er 7

Tim

er 8

Port 1

Tim

er 1

3

1 Comp.Channel

3/6 CAPCOMChannels

CAPCOM6 Unit forPWM Generation

8 9 4 16

6

16

Port 4

P4.5/ CAN RxD

P 4.6/ CAN TxD

8-Channels

External Bus,(8/16 bit;MUX only

&XBUSControl

CAPCOM 2

8-Channel

3Overview -Overview - C164CI Block Diagram

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



C166-CoreC166-Core

165

OSC CPU clock:20 / 25 MHz

Por

t 6P

ort 0

Por

t 4

Port 1

Port 5

Port 3

Port 2

CPU

Dua

l Po

rt RAM

2 KByte


Watchdog

Peripheral Data


Instr./Data

USART

ASCBRG

BRG

SSC

Sync.Channel(SPI)

GPT1

T3

T4

GPT2

T2

T5

T6

16 6 16 8

16

8

8

16

16

16

1632

PEC

Interrupt Bus

Data

Data

XB

US

(16

-bit

NO

N M

UX

Dat

a / A

ddre

sses

)


no

ROM

X-B

us

Per

iph

era

l

12 ext. IR

XTAL


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



up to

ROM/Flash-

EPROM

32 KByte

OSC

Por

t 0P

ort 4

Port 1 Port 5 Port 3 Port 2

SAB 8xC166SAB 8xC166CPU CORE CPU CORE D

ual P

ort

RAM

1 KByte


Peripheral Data


Instr./Data

External

Bus

Controller

10-BitADC

USART

ASCBRG BRG

ASC

GPT1

T3

T4

GPT2

T2

T5

T6

CAPCOM

Tim

er 1

Tim

er 0

16 10 16 16

16

2

16

16

16

1632

PEC

Interrupt Bus

Data

Data

USART

XTAL

16 Channels

19 ext. IR

3Overview -Overview - SAB 80C166 Block Diagram

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



C166-CoreC166-Core

167

PLL(input: 5

MHz)OSC(output: 20MHz)

2KBXRAM

Por

t 6P

ort 0

Por

t 4

Port 1

Port 5

Port 3

Port 2 Port 8

Port 7

CPU

Dua

l Po

rt

RAM

2 KByte


Watchdog

Peripheral Data


Instr./Data

USART

ASCBRG

BRG

SSC

Sync.Channel

(SPI)

GPT1

T3

T4

GPT2T2

T5

T6

CAPCOM1, 2

32 Channels

Tim

er 7

Tim

er 1

Tim

er 0

Tim

er 8

PWM Module

PT 1PT 2

PT 3

PT 4

16 16 16 16 8 8

16

8

8

16

16

16

1632

PEC

Interrupt Bus

Data

Data

EPROM

ROM/Flash

up to128

KByte

XB

US

(16

-bit

NO

N M

UX

Dat

a / A

ddre

sses

)


Multi Funktional

10-BitADC

16 Channels

36 ext. IR

XTAL


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



C166-CoreC166-Core

167CR

PLL(input: 5 MHz)OSC(output: 20MHz)

2KB XRAM

Por

t 6P

ort 0

Por

t 4

Port 1

Port 5

Port 3

Port 2 Port 8

Port 7

CPU

Dua

l Po

rt

RAM

2 KByte


Watchdog

Peripheral Data


Instr./Data

MultiFunktional

10-BitADC

USART

ASCBRG

BRG

SSC

Sync.Channel

(SPI)

GPT1

T3

T4

GPT2

T2

T5

T6

CAPCOM1, 2

32 Channels

Tim

er 7

Tim

er 1

Tim

er 0

Tim

er 8

PWM ModulePT 1PT 2

PT 3

PT 4

16 16 15 16 8 8

16

8

8

16

16

16

1632

PEC

Interrupt Bus

Data

Data

128 KByteROM/

EPRONFLASH

XB

US

(16

-bit

NO

N M

UX

Dat

a / A

ddre

sses

)


CAN2.0 B active

16 Channels

36 ext. IR

XTAL

3Overview -Overview - C167CR Block Diagram

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167


- 21MicrocontrollersCPUCPU

Overview (16 MHz)

Complete 16-bit architecture with 32-bit bus to the internal Complete 16-bit architecture with 32-bit bus to the internal ROM to process 8-bit, 16-bit and even 32-bit (MUL/DIV) ROM to process 8-bit, 16-bit and even 32-bit (MUL/DIV) operandsoperands

16 MHz CPU clock results in an instruction cycle time of 16 MHz CPU clock results in an instruction cycle time of 125ns which guarantees highest CPU performance125ns which guarantees highest CPU performance

To avoid an accumulator bottleneck To avoid an accumulator bottleneck 16 General Purpose Register (GPR) are implemented16 General Purpose Register (GPR) are implemented- Up to 16 GPRs from a register bankUp to 16 GPRs from a register bank- Any register bank is freely locatable in internal RAMAny register bank is freely locatable in internal RAM

Easy and efficient programming is supported by powerful Easy and efficient programming is supported by powerful instructions combined with complex addressing modesinstructions combined with complex addressing modes

Transparent programming of the on-chip peripherals via Transparent programming of the on-chip peripherals via an universal Special Function Register (SFR) interfacean universal Special Function Register (SFR) interface

4

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Overview (20 MHz)






4

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Overview (25 MHz)






4

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



On-ChipOn-Chip(EP)ROM(EP)ROM

SP

STK OV

STK UV

Block DiagramROM / RAM interaction

CPUCPU

PSW

SYSCON

MDL

MDH

Mul./Div.-HW

Bit-Mask Gen.

ALUALU

16-bit

Barrel-Shifter

Code Seg.Ptr

Data Page Pointer

On-ChipOn-ChipStaticStaticRAMRAM

R15

R0

STK OV

STK UV

General

R15

R0

Purpose

Registers

Context Ptr.

4-StagePipeline

Exec. Unit

Instr. Ptr.

Instr. Reg.32

16

16

BUSCON 1

ADDRSEL 1

4CPUCPU

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



On-ChipOn-Chip(EP)ROM(EP)ROM

SP

STK OV

STK UV

Block DiagramROM / RAM interaction

CPUCPU

MDL

MDH

Mul./Div.-HW

Bit-Mask Gen.

ALUALU

16-bit

Barrel-Shifter

Code Seg.Ptr

Data Page Pointer

On-ChipOn-ChipStaticStaticRAMRAM

R15

R0

STK OV

STK UV

General

R15

R0

Purpose

Registers

Context Ptr.

4-StagePipeline

Exec. Unit

Instr. Ptr.

Instr. Reg.

ADDRSEL 1

ADDRSEL 2

ADDRSEL 3

ADDRSEL 4

PSWSYSCON

BUSCON 0

32

16

16

BUSCON 1

BUSCON 2

BUSCON 3

BUSCON 4

4CPUCPU

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Up to 16 GPRs = 1 Register bankUp to 16 GPRs = 1 Register bankConsisting of max.Consisting of max.- 8 Word-Registers8 Word-Registers- 8 Word-Registers with lower and higher Byte access8 Word-Registers with lower and higher Byte access

The GPRs are bit-addressableThe GPRs are bit-addressable Any Register bank can be freely allocated in internal RAMAny Register bank can be freely allocated in internal RAM The location of the active Register bank is determined by The location of the active Register bank is determined by

Context Pointer (CP)Context Pointer (CP) CP can be easily switched, to select another Register bankCP can be easily switched, to select another Register bank SWTC (one instruction cycle)SWTC (one instruction cycle)

General Purpose Register(GPR)

4CPUCPU

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



0FA00

R8R8R9R9R10R10R11R11R12R12R13R13R14R14R15R15

RH0RH1RH2RH3RH4RH5RH6RH7

RL0RL1RL2RL3RL4RL5RL6RL7

Context pointerContext pointer

0FDFE

1KBytesinternal RAM


Block DiagramROM / RAM interaction with 1K RAM

STKOV

STKUV

R15R15

R0R0

0FC00

Stackpointer UnderflowStackpointer

Stackpointer Overflow

STKUV

STKOV

4CPUCPU

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



0F600


RH0RH1RH2RH3RH4RH5RH6RH7

RL0RL1RL2RL3RL4RL5RL6RL7

Context pointerContext pointer

0FDFE

2KBytesinternal RAM


STKOV

STKUV

R15R15

R0R0

0FC00

Stackpointer UnderflowStackpointer

Stackpointer Overflow

STKUV

STKOV

Block DiagramROM / RAM interaction with 2K RAM

4CPUCPU

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Effective execution time of most instruction in 125 nsEffective execution time of most instruction in 125 ns Three word prefetch queue (buscontroller) to support Three word prefetch queue (buscontroller) to support

pipelinepipeline Optimized branch processingOptimized branch processing

- For branch instruction (Jump, Cond. Jump, Call, Return,...) For branch instruction (Jump, Cond. Jump, Call, Return,...) only one additional machine cycle is normally required to only one additional machine cycle is normally required to fetch target instructionfetch target instruction

Jump CacheJump Cache- For loop processing no additional machine cycle is requiredFor loop processing no additional machine cycle is required

Four Stage Instruction Pipeline at 16 MHz

4CPUCPU

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Processing of each instruction is partitioned in 4 stages

Fetch

Decode

Execute

Write Back

1. Instr.

2. Instr.

3. Instr.

4. Instr.

Time 1 Machine Cycle = 125 ns at 16 MHz CPU clock


4CPUCPU

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167




4CPUCPU





C161C161

C166C166

C163C163

C164C164

C165C165

C167C167




Fetch

Decode

Execute

Write Back

1. Instr.

2. Instr.

3. Instr.

4. Instr.



4CPUCPU

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167








4CPUCPU

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167




Fetch

Decode

Execute

Write Back

1. Instr.

2. Instr.

3. Instr.

4. Instr.



4CPUCPU

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Data manipulationData manipulation- Arithmetic and boolean instruction incl. fast multiply/divide Arithmetic and boolean instruction incl. fast multiply/divide

in 0.6/1.2µsin 0.6/1.2µs- Multiple (up to 15) bit shift and rotate in 125 ns Multiple (up to 15) bit shift and rotate in 125 ns - Bit to bit manipulation in internal RAM and SFR’sBit to bit manipulation in internal RAM and SFR’s

Data movementData movement- MOV instructions with all important addressing modesMOV instructions with all important addressing modes- Byte to word conversionByte to word conversion- System stack (PUSH, POP) with over- and underflow System stack (PUSH, POP) with over- and underflow

controlcontrol- User stack (MOV with auto increment and decrement)User stack (MOV with auto increment and decrement)

... ...

Instruction Set at 16 MHz

4CPUCPU

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Program manipulationProgram manipulation- Jumps and calls / conditional jumps under 16 different Jumps and calls / conditional jumps under 16 different

conditionsconditions- Software- and hardware-TrapsSoftware- and hardware-Traps- Fast context switching in 125 nsFast context switching in 125 ns

Special instructions forSpecial instructions for- Power consumption reduction and system ControlPower consumption reduction and system Control- Non-interruptable instruction sequences Non-interruptable instruction sequences - Extended addressing access Extended addressing access

...Instruction Set at 16 MHz

4CPUCPU

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167





in 0.5/1.0us in 0.5/1.0us - Multiple (up to 15) bit shift and rotate in 100 ns Multiple (up to 15) bit shift and rotate in 100 ns - Bit to bit manipulation in internal RAM and SFR’sBit to bit manipulation in internal RAM and SFR’s



......

4CPUCPU

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167





Special instructions forSpecial instructions for- Power consumption reduction and system ControlPower consumption reduction and system Control- Non-interruptable instruction sequences Non-interruptable instruction sequences - Extended addressing accessExtended addressing access


4CPUCPU

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167





Special instructions forSpecial instructions for- Power consumption reduction and system ControlPower consumption reduction and system Control

...Instruction Setat 20 MHz on the 8xC166

4CPUCPU

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167




in 0.4/0.80µsin 0.4/0.80µs- Multiple (up to 15) bit shift and rotate in 80 ns Multiple (up to 15) bit shift and rotate in 80 ns - Bit to bit manipulation in internal RAM and SFR’sBit to bit manipulation in internal RAM and SFR’s



... ...


4CPUCPU

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167





Special instructions forSpecial instructions for- Power consumption reduction and system ControlPower consumption reduction and system Control- Non-interruptable instruction sequences Non-interruptable instruction sequences - Extended addressing accessExtended addressing access


4CPUCPU

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Address Space...

Complete address spaceComplete address space- ““von Neumann” architecture with multiple internal bus von Neumann” architecture with multiple internal bus

structure to avoid bus bottlenecksstructure to avoid bus bottlenecks- up to 8 MBytes address spaceup to 8 MBytes address space- segmented address space: 64KB code segments and 16K segmented address space: 64KB code segments and 16K

data pagesdata pages

Internal address spaceInternal address space- no ROMno ROM- 1 KByte SFR's1 KByte SFR's

C161C161VVC161C161VV C161C161RIRIC161C161RIRIC161C161OOC161C161OOC161C161KKC161C161KK

1 KByte1 KByte1 KByte1 KByte 3 KByte3 KByte3 KByte3 KByte2 KByte2 KByte2 KByte2 KByte1 KByte1 KByte1 KByte1 KByteRAMRAMRAMRAM

MemoryMemory5

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Flexible ext. bus configurations to simplify system Flexible ext. bus configurations to simplify system integrationintegration- up to 22-bit Address / 8-bit Data MUXup to 22-bit Address / 8-bit Data MUX- up to 22-bit Address / 16-bit Data MUX up to 22-bit Address / 16-bit Data MUX - Five completely independent configuration registersFive completely independent configuration registers- 0-5 programmable chip selects and programmable bus 0-5 programmable chip selects and programmable bus

control signal to save external glue-logiccontrol signal to save external glue-logic

...Address Space

MemoryMemory5

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Address Space...




Internal address spaceInternal address spaceup to 128 KBytes ROM / Flash-EPROMup to 128 KBytes ROM / Flash-EPROM- 1 KByte SFR's1 KByte SFR's

MemoryMemory5

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



C164RIAddress Space...




Internal address spaceInternal address space- 1 KByte SFR's1 KByte SFR's- 2 KByte RAM2 KByte RAM- 64 KByte of OTP ROM64 KByte of OTP ROM

MemoryMemory5

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



C164RI ...Address Space

Flexible ext. bus configurations to simplify system Flexible ext. bus configurations to simplify system integrationintegration- up to 22-bit Address / 8-bit Data (MUX)up to 22-bit Address / 8-bit Data (MUX)- up to 22-bit Address / 16-bit Data (MUX)up to 22-bit Address / 16-bit Data (MUX)- Five completely independent configuration registersFive completely independent configuration registers- Programmable bus control signal to save external glue-Programmable bus control signal to save external glue-

logiclogic

MemoryMemory5

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Address Space...




Internal address spaceInternal address space- no ROMno ROM- 1 KByte SFR's1 KByte SFR's- 2 KByte RAM2 KByte RAM

MemoryMemory5

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Address Space...


structure to avoid bus bottlenecksstructure to avoid bus bottlenecks- 64KByte non-segmented address space64KByte non-segmented address spaceup to 16 MBytesup to 16 MBytes- segmented address space: 64KB code segments and 16K segmented address space: 64KB code segments and 16K


Internal address spaceInternal address spaceup to 32 KBytes ROM / Flash-EPROMup to 32 KBytes ROM / Flash-EPROM- 1 KByte SFR's1 KByte SFR's

MemoryMemory

883 3 C166C166883 3 C166C166 888 8 C166C166888 8 C166C166

1 KByte1 KByte1 KByte1 KByte 1 KByte1 KByte1 KByte1 KByteRAMRAMRAMRAM

32 KByte32 KByte32 KByte32 KByte 32 KByte 32 KByte FlashFlash32 KByte 32 KByte FlashFlashROMROMROMROM

5

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Flexible ext. bus configurations to simplify system Flexible ext. bus configurations to simplify system integrationintegration- up to 18-bit Address / 8-bit Data (MUX and NMUX)up to 18-bit Address / 8-bit Data (MUX and NMUX)- up to 18-bit Address / 16-bit Data (MUX and NMUX)up to 18-bit Address / 16-bit Data (MUX and NMUX)- Two on 80C166 completely independent configuration Two on 80C166 completely independent configuration

registersregisters- Programmable HOLD/HOLDA/BREQ bus arbitration Programmable HOLD/HOLDA/BREQ bus arbitration

function for multi-master operations function for multi-master operations

...Address Space

MemoryMemory5

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Address Space...


structure to avoid bus bottlenecksstructure to avoid bus bottlenecks- 64KByte non-segmented address space64KByte non-segmented address spaceup to 16 MBytesup to 16 MBytes- segmented address space: 64KB code segments and 16K segmented address space: 64KB code segments and 16K


Internal address spaceInternal address spaceup to 128 KBytes ROM / Flash-EPROMup to 128 KBytes ROM / Flash-EPROM- max 4 KByte SFR'smax 4 KByte SFR's

MemoryMemory

RAMRAMRAMRAM

ROMROMROMROM

C167C167C167C167 C167C167CRCRC167C167CRCR

4 KByte4 KByte4 KByte4 KByte 4 KByte4 KByte4 KByte4 KByte

128 KByte 128 KByte FlashFlash128 KByte 128 KByte FlashFlash 128 KByte 128 KByte FlashFlash

5

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Flexible ext. bus configurations to simplify system Flexible ext. bus configurations to simplify system integrationintegration- up to 24-bit Address / 8-bit Data (MUX and NMUX)up to 24-bit Address / 8-bit Data (MUX and NMUX)- up to 24-bit Address / 16-bit Data (MUX and NMUX)up to 24-bit Address / 16-bit Data (MUX and NMUX)- Five completely independent configuration registersFive completely independent configuration registers- Five programmable chip selects and programmable bus Five programmable chip selects and programmable bus

control signal to save external glue-logiccontrol signal to save external glue-logic- Programmable HOLD/HOLDA/BREQ bus arbitration Programmable HOLD/HOLDA/BREQ bus arbitration

function for multi-master operationsfunction for multi-master operations

...Address Space

MemoryMemory5

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Bit Addressable Space

Segment 0 includes Internal MemorySegment 0 includes Internal Memory

512 BytesExt. SFR’s

Internal RAM

1K

0.5K

ExternalMemory

00000

0FE00

0FA00

0F000

100007 0

0.5K

4 M4 M Bytes externalBytes external16 MByte internal16 MByte internal

Code Segments Data Pages

0

1

2

3

3

2

1

0

7

6

5

4

11

10

9

8

15

14

13

12

10000

20000

30000

3FFFF

Internal and externalMemory Map

MemoryMemory

C161RI:

C161O:0F600

Internal RAM

512 BytesSFR’s

1K

2KOn-Chip XRAM

0E800

0E000

Reserved

0F200Reserved

I²CI²C

C161V, C161K, C161O, C161RI:

C161RI:

X-Bus Peripheral

5

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167





512 BytesSFR’s

Internal RAM

1K

ExternalMemory


00000

0F000

08000

0FE00

0FA00

0F200

100007 0

128K

0.5K

0.5K

up to 16 Mup to 16 M BytesBytesCode Segments Data Pages

0

1

2

3

3

2

1

0

7

6

5

4

11

10

9

8

15

14

13

12

InternalROM/

FLASH

10000

20000

30000

3FFFF


MemoryMemory

InternalROM /

Flash E²PROM(mappable to Seg. 1)

0F200

Reserved

SSP ModuleSSP Module0F000

0E800Reserved

X-Bus Peripheral

5

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167




X-Bus Peripheral


512 BytesSFR’s

Internal RAM

1K

1KInternal RAM

ExternalMemory

InternalROM /

Flash E²PROM(mappable to Seg. 1)


00000

08000

0FE00

0FA00

0F600

0F200

100007 0

64K

0.5K

0.5K

Reserved


0

1

2

3

3

2

1

0

7

6

5

4

11

10

9

8

15

14

13

12

InternalROM/

FLASH

10000

20000

30000

3FFFF


MemoryMemory

Full -CANFull -CAN0F000

0E800Reserved

5

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167




512 BytesSFR’s

Internal RAM

1K

1KInternal RAM

ExternalMemory


00000

0F000

0FE00

0FA00

0F600

0F200

100007 0

0.5K

0.5K

Reserved


0

1

2

3

3

2

1

0

7

6

5

4

11

10

9

8

15

14

13

12

10000

20000

30000

3FFFF


MemoryMemory


5

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167




512 BytesSFR’s

Internal RAM

1K

ExternalMemory

InternalROM /

Flash E²PROM(mappable to Seg. 1) 00000

08000

0FE00

100007 0

32K

0.5K 256 KBytes256 KBytes

Code Segments Data Pages

0

1

2

3

3

2

1

0

7

6

5

4

11

10

9

8

15

14

13

12

InternalROM/

FLASH

10000

20000

30000

3FFFF


MemoryMemory

0FA00


5

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167





512 BytesSFR’s

Internal RAM

1K

1KInternal RAM

ExternalMemory

Internal ROM /Flash E²PROM

(mappable to Seg. 1)


00000

0E800

08000

0FE00

0FA00

0F200

100007 0

128K

0.5K

0.5K

Reserved


0

1

2

3

3

2

1

0

7

6

5

4

11

10

9

8

15

14

13

12

InternalROM/

FLASH

10000

20000

30000

3FFFF

Internal and externalMemory Map - C167CR

MemoryMemory

0F000

X-Bus Peripheral

Full - CANFull - CAN

0F600Reserved

5

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



15

Data addressing with Data Page Pointer (DPP) Code addressing with Code Segment Pointer

Selection of oneData Page Pointer 6-bit Segment

Number16-bit

14-bit

8-bitPageNumber

Physical 22-bit Code address

Physical 22-bit Data address

DPP3DPP2DPP1DPP0

Code and Data Addressing via Segmentation and Paging on 8 Mbyte address range

MemoryMemory

Code Seg. Pointer013 16-bit Adress 015 16-bit Instr. Pointer51415 0

5

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Code and Data Addressing via Segmentation and Paging on 16 Mbyte address range

MemoryMemory

15



Number16-bit

14-bit

10-bitPageNumber



DPP3DPP2DPP1DPP0


5

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Code and Data Addressing via Segmentation and Paging on 256 KByte address range

15



Number16-bit

14-bit

4-bitPageNumber



DPP3DPP2DPP1DPP0


MemoryMemory5

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



MByte KByte

8 4 2 1M 512 256 128 64 32 16 8 4 2 1K 512 256 128 64 32 16 8 4 2 0

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

16K

DPP0 = 0 0DPP1 = 0 1DPP2 = 1 0DPP3 = 1 1

Data Addressing via Data Page Pointer (DPPx)

MemoryMemory5

DPP

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Data Addressing via Extended Mode

Examples: Override Segment Number

EXTS RN,#data2 ;data2:No. of instructionsMOV [RM],Ri ;to be used for Ext.Addr.Mode

EXTP RN, #data2MOV [RM], Ri

RN RM RN RM

Physical address, where the contents of Ri is moved to Physical address, where the contents of Ri is moved to

15 0 0 0 015 1515

0 0 0 013

A13 A0A14A23A0A15A16A23

9157

Override Page Number

Overrides standard DPP addressing scheme to ease large Overrides standard DPP addressing scheme to ease large (up to 32-bit) address calculation(up to 32-bit) address calculation- Segment or Page override by an immediate valueSegment or Page override by an immediate value- Segment and Page override by a Register contentsSegment and Page override by a Register contents

MemoryMemory5

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Comparison of Bus Speed at Different Bus Configurations at 16 MHz CPU Clock

External bus speed optimization by prefetching into the instruction queue !

n.a.n.a.

11 1.51.5 2.52.5 4.54.53.03.0

nonenone nonenone 16 Bit16 Bit 8 Bit8 Bitnonenone

nonenone Port 0, 1, 4Port 0, 1, 4 Port 1, 4Port 1, 4 Port 1, 4Port 1, 4Port 0, 1, 4Port 0, 1, 4

125ns /../..125ns /../..

125ns /../..125ns /../.. 375/500/625 ns375/500/625 ns 500/750ns/1µs500/750ns/1µs

88/150/213 ns88/150/213 ns 88/150/213 ns88/150/213 ns

250/375/500 ns250/375/500 ns

125/188/250 ns125/188/250 ns 188/250/313 ns188/250/313 ns

125ns /../..125ns /../.. 125/188/250 ns125/188/250 ns 188/250/313 ns188/250/313 ns125/188/250 ns125/188/250 ns 188/250/313 ns188/250/313 ns

375/500/625 ns375/500/625 ns250/375/500 ns250/375/500 ns

88/150/213 ns88/150/213 ns 88/150/213 ns88/150/213 ns

750/1µs/1.25µ750/1µs/1.25µInstr. Fetch TimeInstr. Fetch Time2 Word2 Word

Bus Cycle TimeBus Cycle Time0 / 1 / 2 Wait States0 / 1 / 2 Wait States

single Chipsingle ChipModeMode

16 Bit Data16 Bit Data16/24 bit Address16/24 bit Address

NON MUXNON MUX


MUXMUX


NON MUXNON MUX


MUXMUX

Address LatchAddress Latch

Instr. Fetch TimeInstr. Fetch Time1 Word1 Word

used Portsused Ports

(50% 2 word instructions) (50% 2 word instructions)

EPROM Access EPROM Access Time t17Time t17

rel. speed for rel. speed for typ. code typ. code

MemoryMemory5

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167






n.a.n.a.





NON MUXNON MUX


MUXMUX


NON MUXNON MUX


MUXMUX




100/150/200 ns100/150/200 ns


100ns /../..100ns /../..

100ns /../..100ns /../..

100/50/200 ns100/50/200 ns 300/400/500 ns300/400/500 ns

600/800ns/1µs600/800ns/1µs

70/120/170 ns70/120/170 ns 70/120/170 ns70/120/170 ns 70/120/170 ns70/120/170 ns

200/300/400 ns200/300/400 ns 300/400/500 ns300/400/500 ns

150/200/250 ns150/200/250 ns

70/120/170 ns70/120/170 ns

400/600/800 ns400/600/800 ns

200/300/400 ns200/300/400 ns

100/150/200 ns100/150/200 ns 150/200/250 ns150/200/250 ns 150/200/250 ns150/200/250 ns100ns /../..100ns /../..


11 1.51.5 2.52.5 4.54.53.03.0(50% 2 word instructions) (50% 2 word instructions)


MemoryMemory5

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167




n.a.n.a.



80/120/160 ns80/120/160 ns


240/320/400 ns240/320/400 ns

480/640/800ns480/640/800ns

55/105/155 ns55/105/155 ns 55/105/155 ns55/105/155 ns 55/105/155 ns55/105/155 ns

160/240/320 ns160/240/320 ns 240/320/400 ns240/320/400 ns

120/160/200 ns120/160/200 ns

55/105/155 ns55/105/155 ns

320/480/640 ns320/480/640 ns

160/240/320 ns160/240/320 ns 80/120/160 ns80/120/160 ns

120/160/200 ns120/160/200 ns 120/160/200 ns120/160/200 ns

80ns /../..80ns /../..

80ns /../..80ns /../..

80ns /../..80ns /../.. 80/120/160 ns80/120/160 ns





NON MUXNON MUX


MUXMUX


NON MUXNON MUX


MUXMUX





11 1.51.5 2.52.5 4.54.53.03.0(50% 2 word instructions) (50% 2 word instructions)


MemoryMemory5

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Relative Performance vs. CPU Frequency

graph by Patrick Pettibon

0/1/2 Waitstates based on 0% mix of 1-wordand 2-word Fetches with Data in the internal DP-RAM

0/1/2 Waitstates based on 0% mix of 1-wordand 2-word Fetches with Data in the internal DP-RAM

MemoryMemory5

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Flash technology from Siemens!

C163 Flash Module! C163 Flash Module! 6

SAB C163-16F25FSAB C163-16F25F

128KByte FLASH

CPU

1k RAM

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



C163 FlashComparsion with C167CR Flash

C163 Flash Module C163 Flash Module

C163 Flash ModuleNew Technology

C167 Flash Module

128 KByte capacity128 KByte capacityAny use for instruction code or dataAny use for instruction code or data

Programming and eraseProgramming and erase- 12 V on separate VPP pin- 12 V on separate VPP pin- SW controlled- SW controlled- Complex SW to avoid over/under-- Complex SW to avoid over/under- programming or eraseprogramming or eraseProgramming controlProgramming control+ Fast: 200 msec per 8 KB block+ Fast: 200 msec per 8 KB blockErase controlErase control- Preprogramming (all zeros) necessary- Preprogramming (all zeros) necessary- Slow: 1 sec per sector- Slow: 1 sec per sector

128 KByte capacity128 KByte capacityAny use for instruction code or dataAny use for instruction code or data

Programming and eraseProgramming and erase+ Progr. voltage 5V on standard VCC pins+ Progr. voltage 5V on standard VCC pins+ Integrated state machine+ Integrated state machine+ Directly controlled by commands+ Directly controlled by commands

Programming controlProgramming control+ Fast: 125 msec per 8 KB block+ Fast: 125 msec per 8 KB blockErase controlErase control+ Simple erase command per sector+ Simple erase command per sector+ Fast: 10 msec per sector+ Fast: 10 msec per sector

6

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Embedded Flash ModuleBasic Overview

CPU

Bus

ExternalHostBus

128 KByteFlash Module

2 Interfaces for Flash Programming

C163 Flash

C163 Core

6C163 Flash Module C163 Flash Module

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Basic StructureProgramming Interface

Ext

erna

l Hos

tIn

terf

ace

CPU

Inte

rfac

eCommand

& ArrayState

Machine

32K

Sec

tor

32K

Sec

tor

32K

Sec

tor

32K

Sec

tor

64 x

8 A

ssem

bly

Buf

fer

Voltage Pumps

32 Bit Data Bus16 Bit Address Bus

ExternalHost

Prog

ram

min

g In

terf

aces

C163Core


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Programming and Erase Controlon CPU Interface...

Commands for Flash Control written to Flash by CPU:Commands for Flash Control written to Flash by CPU:- Reset to ReadReset to Read Resets the internal state machine; Resets the internal state machine;

returns to read mode returns to read mode- Enter Burst ModeEnter Burst Mode Enter programming mode and Enter programming mode and

write first write first word of burst into word of burst into assembly burst assembly burst register register

- Load Burst DataLoad Burst Data Write subsequent word into Write subsequent word into assembly assembly burst register burst register

- Store BurstStore Burst Write last word into burst register and Write last word into burst register and store whole burst into Flash array store whole burst into Flash array

- Erase SectorErase Sector Erase addressed 32KByte sector Erase addressed 32KByte sector- Read Flash Status Read status registerRead Flash Status Read status register- Clear StatusClear Status Clear error flags in status register Clear error flags in status register

......


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



...Programming and Erase Controlon CPU Interface

Commands are transferred to Flash with command Commands are transferred to Flash with command sequences for protectionsequences for protection

Cycles of command sequences are based on JEDEC Cycles of command sequences are based on JEDEC standard (USA)standard (USA)

Command sequences can only be written by instructions Command sequences can only be written by instructions not fetched from Flash itselfnot fetched from Flash itself


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Operation Control by Command Sequences

R = Register Address RA = Read Data Address RD = Read Data WA = Write AddressWD = Write Data SA = Sector Address (hex)

Reset to Read AAAA xxF0Reset to Read AAAA xxF0

Clear Status AAAA xxF5Clear Status AAAA xxF5

RA RDRA RD

AAAA xxA0 WA 32WD

Enter Burst Load AAAA xx50 WA 1.WD

Load Burst Data A0F2 WD

Store Burst AAAA xxAA 5554 xx55

AAAA xx55 SA xx30Erase Sector AAAA xxAA AAAA xx80 5554 xxAA 5554 xx55

1. Cycle 2.Cycle 3.Cycle 4.Cycle 5.Cycle 6.Cycle1. Cycle 2.Cycle 3.Cycle 4.Cycle 5.Cycle 6.CycleCommand Sequence of bus cycles to FlashCommand Sequence of bus cycles to Flash

Flash Command Sequences

Addr DataAddr Data Addr DataAddr Data Addr DataAddr Data Addr DataAddr Data Addr DataAddr Data Addr DataAddr Data


Read Status AAAA xxFA SA, R statusRead Status AAAA xxFA SA, R status

All commands cycles are write cycles (exception status read cycle) !

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



64 Byte Block

Flash Memory

Programming a Burst of 32 Words

Programming is performed by a load / store procedure with the assembly buffer:Programming is performed by a load / store procedure with the assembly buffer:

1. Word

Last WordStore Burst into Flash

Programming Commands Assembly Buffer Flash Array

- Enter BurstEnter Burst Load / Load 1. Word

- Load 3. Word

and so on

- Load 31. Word

- Load 32. Word and Store BurstStore Burst

- Load 2. Word


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



SA 2 SA 2 32 KB 32 KB 0 1 - 0 - 0 1 - 0 -

Erasing a Sector of Flash Memory

Flash MemoryFlash Memory

Erasing a sector is performed in a single step:Erasing a sector is performed in a single step:

Programming Command Flash Array

Only one command (sequence):Erase Sector

Sector addressing:

SA 4 SA 4 32 KB 32 KB 1 1 - 0 - 1 1 - 0 -

SA 3 SA 3 32 KB 32 KB 1 0 - 0 - 1 0 - 0 -

SA 1 SA 1 32 KB 32 KB 0 0 - 0 - 0 0 - 0 -

SectorSectorNumberNumber

Sector SizeSector Size Sector AddressSector Address A16 A15 A14...A01A16 A15 A14...A01

32 KByte Sector32 KByte Sector


Sector addresses are physical addresses !

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



The Flash Status Register FSR provides information of the actual The Flash Status Register FSR provides information of the actual operating state and of error conditions to the user.operating state and of error conditions to the user.

Status bits in FSR:Status bits in FSR:

- BUSY BUSY Flash BusyFlash Busy Busy with programming or erase; Busy with programming or erase; not in read modenot in read mode

- PROG PROG Programming State Programming State Flash busy with store burstFlash busy with store burst- ERASE ERASE Erase StateErase State Flash busy with erase stateFlash busy with erase state- SESE Sector ErasedSector Erased Addressed sector correctly Addressed sector correctly

erasederased- BRSTBRST Burst Mode Burst Mode Assembly buffer being filledAssembly buffer being filled

Error bits in FSR:Error bits in FSR:- OPEROPER Operation ErrorOperation Error Error during programming or Error during programming or

erase erase operationoperation- VPERVPER Voltage Error Voltage Error Voltage problem during Flash Voltage problem during Flash

operationoperation- SQERSQER Sequence Error Sequence Error Improper command or address in Improper command or address in

command sequencecommand sequence- BUERBUER Burst ErrorBurst Error Overflow or underload condition Overflow or underload condition

in in burst modeburst mode

Flash Status Information


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



A Flash operation shall be controlled by following SW A Flash operation shall be controlled by following SW procedure:procedure:

11 Write command sequence to FlashWrite command sequence to Flash22 Check SQER error bit for fault condition in command Check SQER error bit for fault condition in command

sequence sequence 33 Check BUSY status bit if command is (still) in operationCheck BUSY status bit if command is (still) in operation44 When finished: check OPER and VPER error bits; in case When finished: check OPER and VPER error bits; in case

of a store burst operation also the BUER error bitof a store burst operation also the BUER error bit55 In case of fault condition: clear error flag with a clear statusIn case of fault condition: clear error flag with a clear status

command; start corrective actioncommand; start corrective action All addresses to Flash have to be mapped to Flash spaceAll addresses to Flash have to be mapped to Flash space

- Command, sector and data addresseshave to be located Command, sector and data addresseshave to be located within active Flash memory spacewithin active Flash memory space

- The active Flash space is that address range which is The active Flash space is that address range which is covered by the Flashcovered by the Flash

SW control of a flash operation


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Features Programming Modes

OTP module OTP module

64 K byte embedded OTP memory64 K byte embedded OTP memory Two different programming possibilitiesTwo different programming possibilities

- Parallel programming modeParallel programming mode- Controlled by external standard programming Controlled by external standard programming

systemsystem- Serial programming mode Serial programming mode - Controlled by int. CPU with boot routine out of boot Controlled by int. CPU with boot routine out of boot

ROMROM- Using e.g. a laptop as programming deviceUsing e.g. a laptop as programming device

External 11,5 V programming voltageExternal 11,5 V programming voltage Fast programming cycles: 1 word (16 bit) in 100 µsFast programming cycles: 1 word (16 bit) in 100 µs Optional read protectionOptional read protection Interface optimized for CPU performance Interface optimized for CPU performance

with 32-bit instruction fetch in one cyclewith 32-bit instruction fetch in one cycle Any use for instruction code or constant dataAny use for instruction code or constant data

7

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Serial ProgrammingCPU Host Mode

Parallel ProgrammingExternal Host Mode

Comparsion of Programming Modes

Host programming deviceHost programming device• Internal CPUInternal CPU

Programming InterfaceProgramming Interface• Standard serial interface (USART)Standard serial interface (USART)• Automatical adjustment on baud rateAutomatical adjustment on baud rate• Optimized for com-link of PC or laptopOptimized for com-link of PC or laptop

Programming controlProgramming control• User SW fetched by boot ROM routineUser SW fetched by boot ROM routine

VPP controlVPP control• By SW: control signal on port pinBy SW: control signal on port pin

Host programming deviceHost programming device• External programmer or testerExternal programmer or tester

Programming InterfaceProgramming Interface• External 16-bit system bus (XBUS)External 16-bit system bus (XBUS)• Fully asynchronFully asynchron• OTP is slave; CPU disabledOTP is slave; CPU disabled

Programming controlProgramming control• External control with bus cyclesExternal control with bus cycles

VPP controlVPP control• Controlled by programming deviceControlled by programming device

7OTP OTP

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Pro

gram

min

g In

terf

ace

CPU

Inte

rfac

e

ProgrammingControl

64K

OT

P A

rray

A

rray

Con

trol32 Bit

Data Bus

16 Bit Address Bus

External Hostor CPU Host

C164Core

Basic StructureProgramming Interface

7OTP module OTP module

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Interrupt ControllerInterrupt Controller- Extremely short interrupt response time of minimal 312ns Extremely short interrupt response time of minimal 312ns

typical: 500ns typical: 500ns - Interrupt execution in small time segmentsInterrupt execution in small time segments- Ensures highest real-time performanceEnsures highest real-time performance- Comprehensive prioritization schemeComprehensive prioritization scheme

- Easy scheduling of complex real-time systems by Easy scheduling of complex real-time systems by using up to 64 priority levels (4 groups within 16 using up to 64 priority levels (4 groups within 16 levels)levels)

- Non-maskable interrupt input (NMI)Non-maskable interrupt input (NMI)- Hardware-Traps on runtime errors and Software-TrapsHardware-Traps on runtime errors and Software-Traps

......

Interrupt SystemInterrupt System

Overview at 16MHz...

8

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



CPU independent interrupt-service via CPU independent interrupt-service via Peripheral Events Controller (PEC)Peripheral Events Controller (PEC)- Off-loads the CPU from simple but frequent interrupt-Off-loads the CPU from simple but frequent interrupt-

servicesservices- Interrupt-driven “DMA-like” data transfer to any location in Interrupt-driven “DMA-like” data transfer to any location in

segment 0, without task switch of the CPUsegment 0, without task switch of the CPU- Makes peripheral data transfers Independent of running Makes peripheral data transfers Independent of running

CPU routineCPU routine- Response-time is minimal 187ns, typical 375ns Response-time is minimal 187ns, typical 375ns

with a CPU load of 125nswith a CPU load of 125ns

...Overview at 16MHz

8Interrupt SystemInterrupt System

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167







......

Interrupt SystemInterrupt System


8

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167








...Overview at 20MHz


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167







......



C161C161

C166C166

C163C163

C164C164

C165C165

C167C167








Overview at 25MHz


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



3 2 1 0151413121110

9876543210

group

L e

v e

l

1

64

Level 15group 1

group 0

group 2group 3

Level 14group 1

group 0

group 2group 3 PEC 0

PEC 6 PEC 5PEC 4

PEC 3PEC 2 PEC 1

PEC 7

Level 13 group 1group 0

group 2group 3

Level 1-12group 1

group 0

group 2group 3

Level 0group 1

group 0

group 2group 3

Priority System, PEC


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



INTR Flag is Set

Peripheral Interrupt




External Interrupt*

External Interrupt*

Priority Check

Comparison ofInterrupt Priority

with CPURuntime Priority

16 Priority Levels

ifhigherPriority

Interrupt Control Register of the appropriate peripheral INTR Service:

Save PSW, CSP, IP

Set new priorityin PSW.

Set CSP, IPaccording toperipheral vector or Trap no.

PECService

* External Interrupts are possible, e.g. instead of the Capture Input

Interrupt Processing

4 Groups

Group Check

ClearINTR Flag


Ext. Interrupts + NMIExt. Interrupts + NMI

Peripheral InterruptsPeripheral Interrupts

sampled every 63 nssampled every 63 ns

C161C161VV C161C161KK C161C161OO C161C161RIRI

1515 2121 2121 2121

55 55 1111 1111

44 44 77 88

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167




INTR Flag is Set





External Interrupt*

External Interrupt*

Priority Check



16 Priority Levels

ifhigherPriority

Interrupt Control Register of the appropriate peripheralINTR Service:

Save PSW, CSP, IP



PECService


12 ext. Interrupts(+ NMI) including 8 which are sampled every 40 ns12 Peripheral Interrupts

4 Groups

Group Check

ClearINTR Flag


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167




INTR Flag is Set





External Interrupt*

External Interrupt*

Priority Check



16 Priority Levels

ifhigherPriority


Save PSW, CSP, IP



PECService



4 Groups

Group Check

ClearINTR Flag


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167




INTR Flag is Set





External Interrupt*

External Interrupt*

Priority Check



16 Priority Levels

ifhigherPriority


Save PSW, CSP, IP



PECService


19 ext. Interrupts(+ NMI)32 Peripheral Interrupts on the 80C166

4 Groups

Group Check

ClearINTR Flag


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167




INTR Flag is Set





External Interrupt*

External Interrupt*

Priority Check



16 Priority Levels

ifhigherPriority


Save PSW, CSP, IP



PECService



4 Groups

Group Check

ClearINTR Flag


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Interrupt has passed priority and group check

Interrupt priority < 14 Interrupt priority 14 or 15and Data Counter > 0Interrupt priority 14 or 15and Data Counter > 0

Interrupt service PEC service

PEC

8 PECChannel

Data Counter

SRC PointerDEST Pointer

Contr. Reg.

IR request if Data Counter = 0

Memory Segment 0Memory Segment 0

0FFFF

00000

Byte orWordTransfer

INTR Service:

Save PSW, CSP, IP


Set CSP, IPaccording toPeripheral vector or Trap No.

IR request if Data Counter = 0priority & groupcheck

Peripheral Event Controller (PEC)


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



2 General Purpose Timer units (GPT1 & GPT2)2 General Purpose Timer units (GPT1 & GPT2)- 5 Timers (250/500ns) with multiple Input/Output, Reload 5 Timers (250/500ns) with multiple Input/Output, Reload

and Capture functions and complex concatenation and Capture functions and complex concatenation capabilitiescapabilities

Capture/Compare unit (CAPCOM)Capture/Compare unit (CAPCOM)- 2 timers (500ns) each with Reload register and 16 2 timers (500ns) each with Reload register and 16

independent independent 16-bit Capture/Compare channels programmable to 6 16-bit Capture/Compare channels programmable to 6 modes of operationmodes of operation

2 independent identical USARTs2 independent identical USARTs- max 500KBaud asynchronousmax 500KBaud asynchronousmax 2.0 Mbit/sec synchronous data transfermax 2.0 Mbit/sec synchronous data transfer

I/O PortsI/O Ports- 6 Ports provide 76 I/O lines (V/K/O only)6 Ports provide 76 I/O lines (V/K/O only)

Watchdog: 16-bit Reload-timer causes reset on overflowWatchdog: 16-bit Reload-timer causes reset on overflow

Peripherals Set of theC161x

9PeripheralsPeripherals

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Peripherals Set of theC161RI

I/O PortsI/O Ports- 7 Ports provide 77 I/O Lines7 Ports provide 77 I/O Lines

Realtime clockRealtime clock Fast and accurate A/D ConverterFast and accurate A/D Converter

- 8-bit resolution, 4 input channels, 7.5µs conversion time, 8-bit resolution, 4 input channels, 7.5µs conversion time, continuous modescontinuous modes

II22C BusC Bus- 7 and 10-bit addressing, 400KHz7 and 10-bit addressing, 400KHz- 2 channels (multiplexed)2 channels (multiplexed)


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Varieties of the C161


C161C161VV C161C161KK C161C161OOFeatureFeature

1 KByte 1 KByte 2 KByteInternal RAM Size (IRAM)

2 4Chip Select Signals

MUX (DE)MUX (DE)MUXBus Modes

yes yesPower Saving Modes

yes yes yesGeneral Purpose Timer 1 (GPT1)

yes yesInput / Output Functionality GPT1

General Purpose Timer 2 (GPT2)with Capture Input (CAPIN) Funct.

yes

Extension RAM Size (XRAM)

4 4 7Fast external Interrupts

I²C - BUS

Real Time Clock (RTC)

C161C161RIRI

1 KByte

5

(DE)MUX

yes

yes

yes

yes

2 KByte

8

yes

yes

8-Bit ADC yes

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



2 General Purpose Timer units (GPT1 & GPT2)2 General Purpose Timer units (GPT1 & GPT2)- 5 Timers 160/320ns with enhanced Input/Output, 5 Timers 160/320ns with enhanced Input/Output,

Reload and Capture functions andReload and Capture functions andcomplex concatenation capabilitiescomplex concatenation capabilities

Independent USARTIndependent USART- max. 780 KBaud asynchronous max. 780 KBaud asynchronous

and max 3.1 Mbit/sec synchronous data transferand max 3.1 Mbit/sec synchronous data transfer Fast Synchronous Serial Port (SSP)Fast Synchronous Serial Port (SSP)

- max. 12.5 Mbit/sec to connect to slave devices likemax. 12.5 Mbit/sec to connect to slave devices likeEEPROMs with sending up to 3 Bytes (24bits)EEPROMs with sending up to 3 Bytes (24bits)

I/O PortsI/O Ports- 7 Ports provide 77 I/O Lines7 Ports provide 77 I/O Lines

Watchdog: 16-Bit Reload -timer causes reset on overflowWatchdog: 16-Bit Reload -timer causes reset on overflow

Peripherals Set of theC163


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



General Purpose Timer unit (GPT1)General Purpose Timer unit (GPT1)- 3 Timers (200/400ns) with enhanced Input/Output, Reload 3 Timers (200/400ns) with enhanced Input/Output, Reload


Capture/Compare unit (CAPCOM2)Capture/Compare unit (CAPCOM2)- 2 Timers (400ns) with Reload register and 8 independent 2 Timers (400ns) with Reload register and 8 independent

16-bit Capture/Compare channels programmable to 6 16-bit Capture/Compare channels programmable to 6 modes of operationmodes of operation

Capture/Compare unit (CAPCOM6) Capture/Compare unit (CAPCOM6) for flexible PWM Signal Generationfor flexible PWM Signal Generation- 2 Timers (100ns) with Period register, 1 Offset register, 3/6 2 Timers (100ns) with Period register, 1 Offset register, 3/6

16-bit Capture/Compare channels and one 10-bit compare 16-bit Capture/Compare channels and one 10-bit compare channelchannel

- Optimized for Drive Control ApplicationsOptimized for Drive Control Applications ......

Peripherals Set of theC164...


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Independent USARTIndependent USART- max 625 KBaud asynchronous and max 2.5 Mbit/sec max 625 KBaud asynchronous and max 2.5 Mbit/sec

synchronous data transfersynchronous data transfer Fast Serial Synchronous Communication interface (SSC)Fast Serial Synchronous Communication interface (SSC)

- max 5 Mbit/sec full duplex transfer rate, SPI compatiblemax 5 Mbit/sec full duplex transfer rate, SPI compatible Fast and accurate A/D ConverterFast and accurate A/D Converter

- 10-Bit resolution, 8 input channels, 9.7µs conversion time, 10-Bit resolution, 8 input channels, 9.7µs conversion time, enhanced continuous and scan modes with channel-enhanced continuous and scan modes with channel-injection capability, automatic calibration.injection capability, automatic calibration.

I/O PortsI/O Ports- 6 Ports provide 59 I/O lines6 Ports provide 59 I/O lines

Watchdog: 16-Bit Reload-timer causes reset on overflowWatchdog: 16-Bit Reload-timer causes reset on overflow Reset DetectionReset Detection

...Peripherals Set of theC164


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



2 General Purpose Timer units (GPT1 & GPT2)2 General Purpose Timer units (GPT1 & GPT2)- 5 Timers (160/320)ns with enhanced5 Timers (160/320)ns with enhanced

Input/Output, Reload and Capture functions andInput/Output, Reload and Capture functions andcomplex concatenation capabilitiescomplex concatenation capabilities

Independent USARTIndependent USART- max. 780 KBaud asynchronous max. 780 KBaud asynchronous

and max 3.1 Mbit/sec synchronous data transferand max 3.1 Mbit/sec synchronous data transfer Fast Serial Synchronous Communication interface (SSC)Fast Serial Synchronous Communication interface (SSC)

- max. 6.25 Mbit/sec full duplex transfer rate, SPI compatiblemax. 6.25 Mbit/sec full duplex transfer rate, SPI compatible I/O PortsI/O Ports

- 7 Ports provide 77 I/O Lines7 Ports provide 77 I/O Lines Watchdog: 16-Bit Reload-timer causes reset on overflowWatchdog: 16-Bit Reload-timer causes reset on overflow

Peripherals Set of theC165


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



2 General Purpose Timer units (GPT1 & GPT2)2 General Purpose Timer units (GPT1 & GPT2)- 5 Timers (200/400ns) with multiple Input/Output, Reload 5 Timers (200/400ns) with multiple Input/Output, Reload


Capture/Compare unit (CAPCOM)Capture/Compare unit (CAPCOM)- 2 timers (400ns) each with Reload register and 16 2 timers (400ns) each with Reload register and 16

independent independent 16-bit Capture/Compare channels programmable to 6 16-bit Capture/Compare channels programmable to 6 modes of operationmodes of operation

2 independent identical USARTs2 independent identical USARTs- max 625KBaud asynchronousmax 625KBaud asynchronousmax 2.5 Mbit/sec synchronous data transfermax 2.5 Mbit/sec synchronous data transfer

......

Peripherals Set of theSAB 80C166...


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Fast and accurate A/D ConverterFast and accurate A/D Converter- 10-bit resolution, 10 input channels, 9.7µs conversion time, 10-bit resolution, 10 input channels, 9.7µs conversion time,

continuous and scan modescontinuous and scan modes I/O PortsI/O Ports

- 6 Ports provide 76 I/O lines6 Ports provide 76 I/O lines Watchdog: 16-bit Reload-timer causes reset on overflowWatchdog: 16-bit Reload-timer causes reset on overflow

...Peripherals Set of theSAB 80C166


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



2 General Purpose Timer units (GPT1 & GPT2)2 General Purpose Timer units (GPT1 & GPT2)- 5 Timers (200/400ns) with enhanced Input/Output, Reload 5 Timers (200/400ns) with enhanced Input/Output, Reload


2 Capture/Compare units (CAPCOM1 & 2)2 Capture/Compare units (CAPCOM1 & 2)- 4 Timers (400ns) with Reload register and 32 independent 4 Timers (400ns) with Reload register and 32 independent

16-bit Capture/Compare channels programmable to 6 16-bit Capture/Compare channels programmable to 6 modes of operationmodes of operation

4 high resolution PWM channels4 high resolution PWM channels- each with independent time-base of up to 50ns resolution each with independent time-base of up to 50ns resolution

and programmable operation modes (edge-aligned, center-and programmable operation modes (edge-aligned, center-aligned, burst and single-shot mode)aligned, burst and single-shot mode)

......

Peripherals Set of theC167...


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Independent USARTIndependent USART- max 625 KBaud asynchronous and max 2.5 Mbit/sec max 625 KBaud asynchronous and max 2.5 Mbit/sec

synchronous data transfersynchronous data transfer Fast Serial Synchronous Communication interface (SSC)Fast Serial Synchronous Communication interface (SSC)

- max 5 Mbit/sec full duplex transfer rate, SPI compatiblemax 5 Mbit/sec full duplex transfer rate, SPI compatible Fast and accurate A/D ConverterFast and accurate A/D Converter

- 10-Bit resolution, 16 input channels, 9.7µs conversion time, 10-Bit resolution, 16 input channels, 9.7µs conversion time, enhanced continuous and scan modes with enhanced continuous and scan modes with channel-injection capability.channel-injection capability.

I/O PortsI/O Ports- 8 Ports provide 111 I/O lines8 Ports provide 111 I/O lines

Watchdog: 16-Bit Reload-timer causes reset on overflowWatchdog: 16-Bit Reload-timer causes reset on overflow

...Peripherals Set of theC167


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Three 16-bit up/down timers: Three 16-bit up/down timers: 2 auxiliary timers(T2,T4) and 1 core timer(T3) 2 auxiliary timers(T2,T4) and 1 core timer(T3)

Input modeInput mode- Timer mode: Internal clock input with prescaler up to Timer mode: Internal clock input with prescaler up to

2.0 MHz / 500ns; 2.0 MHz / 500ns; Clock can be gated with external signal Clock can be gated with external signal

- Counter Mode: external clock up to 1.00 MHzCounter Mode: external clock up to 1.00 MHz- Cascading of core timer and any aux. timer (33-Bit timer)Cascading of core timer and any aux. timer (33-Bit timer)

Count direction (C166 T3 only) can be changed externally Count direction (C166 T3 only) can be changed externally ......

General Purpose Timer 1 (GPT1)at 16 MHz

GPT 1GPT 110

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



General Purpose Timer 1at 16 MHz

Output modeOutput mode- Interrupt possibility and toggle function at the core timer T3Interrupt possibility and toggle function at the core timer T3- Interrupt possibility at auxiliary timers T2 and T4Interrupt possibility at auxiliary timers T2 and T4

Reload: Reload: Core timer can be reloaded with the contents of any Core timer can be reloaded with the contents of any aux. timeraux. timer

Capture:Capture: Contents of the core timer can be latched into any Contents of the core timer can be latched into any aux. timeraux. timer

10GPT 1GPT 1

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



GPT 1 Function Diagramat 16 MHz

Clk max2.0 MHzClk max2.0 MHz

GateGate

InputMode

Control Core Timer T3 Core Timer T3

ToggleLatch

INTRINTR Flag Flag INTRINTR Flag Flag


GateGate

InputMode

ControlAux Timer T2 / T4Aux Timer T2 / T4

Capture

RunEnable

RunEnable


Outp.enablesOutp.

enables

GateGate

InputMode


up / down

RunEnable

RunEnable


Reload

RunEnable

RunEnable Clk max

2.0 MHzClk max2.0 MHz

33-bit cascaded path

max.

1.0 MHz

max.

1.0 MHz

max.

1.0 MHz

up / down

up / down

10GPT 1GPT 1

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167





2.5 MHz / 400 ns; Clock can be gated with external signal2.5 MHz / 400 ns; Clock can be gated with external signal- Counter Mode: external clock up to 1.25 MHzCounter Mode: external clock up to 1.25 MHz- Cascading of core timer and any aux. timer (33-Bit timer)Cascading of core timer and any aux. timer (33-Bit timer)

Count direction (only T3 ) can be changed externally Count direction (only T3 ) can be changed externally Output modeOutput mode

- Interrupt possibility and toggle function at the core timer T3Interrupt possibility and toggle function at the core timer T3- Interrupt possibility at auxiliary timers T2 and T4Interrupt possibility at auxiliary timers T2 and T4

Reload: Core timer can be reloaded with the contents of Reload: Core timer can be reloaded with the contents of any aux. timerany aux. timer

Capture: Contents of the core timer can be latched into Capture: Contents of the core timer can be latched into any aux. timerany aux. timer

General Purpose Timer 1(GPT 1) at 20 MHz

10GPT 1GPT 1

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167





GateGate

InputMode


ToggleLatch


Clk max2.5 MHzClk max2.5 MHz Input

ModeControl

Aux Timer T2 / T4Aux Timer T2 / T4

Capture

RunEnable

RunEnable


Outp.enablesOutp.

enables

InputMode


up / down

RunEnable

RunEnable


Reload

RunEnable

RunEnable Clk max



max.

1.25 MHz

up / down

up / down

10GPT 1GPT 1

to CAPCOM2Timer T7, T8

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167





GateGate

InputMode


ToggleLatch



GateGate

InputMode


Capture

RunEnable

RunEnable


Outp.enablesOutp.

enables

GateGate

InputMode


up / down

RunEnable

RunEnable


Reload

RunEnable

RunEnable Clk max



max.

1.25 MHz

max.

1.25 MHz

max.

1.25 MHz

up / down

up / down

10GPT 1GPT 1

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167





3.1 MHz / 320 ns; Clock can be gated with external signal3.1 MHz / 320 ns; Clock can be gated with external signal- Counter Mode: external clock up to ~1.6 MHzCounter Mode: external clock up to ~1.6 MHz- Cascading of core timer and any aux. timer (33-Bit timer)Cascading of core timer and any aux. timer (33-Bit timer)

Count direction can be changed externally Count direction can be changed externally Output modeOutput mode

- Interrupt possibility and toggle function at the core timer T3Interrupt possibility and toggle function at the core timer T3- Interrupt possibility at auxiliary timers T2 and T4Interrupt possibility at auxiliary timers T2 and T4

Reload: Core timer can be reloaded with the contents of Reload: Core timer can be reloaded with the contents of any aux. timerany aux. timer

Capture: Contents of the core timer can be latched into Capture: Contents of the core timer can be latched into any aux. timerany aux. timer

General Purpose Timer 1(GPT 1) at 25 MHz

10GPT 1GPT 1

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167





GateGate

InputMode


ToggleLatch



GateGate

InputMode


Capture

RunEnable

RunEnable


Outp.enablesOutp.

enables

GateGate

InputMode


up / down

RunEnable

RunEnable


Reload

RunEnable

RunEnable Clk max



max.

1.6 MHz

max.

1.6 MHz

max.

1.6 MHz

up / down

up / down

10GPT 1GPT 1

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Two 16-Bit up/down timers (T5, T6)Two 16-Bit up/down timers (T5, T6) Input modeInput mode

- Timer mode: Internal clock input with prescalerTimer mode: Internal clock input with prescalerup to 4MHz (250ns)up to 4MHz (250ns)

- Counter mode: External clock up to 2.0 MHz Counter mode: External clock up to 2.0 MHz - T5 can also be clocked with the toggle bit of T6T5 can also be clocked with the toggle bit of T6

Output modeOutput mode- Interrupt possibility and toggle function of a Interrupt possibility and toggle function of a

port line (via a toggle bit)port line (via a toggle bit)- Output of T6 can be used to clock CAPCOM timersOutput of T6 can be used to clock CAPCOM timers

Count direction of all timers can be dynamically changed Count direction of all timers can be dynamically changed (C167) (C167)

Cascading of timer T6 with timer T5Cascading of timer T6 with timer T5 One 16-Bit Capture(for T5) / Reload(for T6) register One 16-Bit Capture(for T5) / Reload(for T6) register

- Reload register for T6, Capture register for T5Reload register for T6, Capture register for T5

General Purpose Timer 2 (GPT 2) at 16 MHz

11GPT 2GPT 2

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167




Capture / ReloadCapture / Reload


ModeControl


RunEnable

RunEnable

EnableEnable

InputMode

Control Timer T5 Timer T5

RunEnable

RunEnable Clk max


ReloadEnableReloadEnable

Clear

Outp.enablesOutp.

enables

ToggleLatch

EnableEnable




INTRINTR Flag Flag INTRINTR Flag Flag max.

2 MHz

max.

2 MHz

up / down

up / down

11GPT 2GPT 2

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



GPT 2 Function Diagramat 16 MHz - C161RI only



ModeControl


RunEnable

RunEnable

EnableEnable

InputMode


RunEnable

RunEnable Clk max



Clear

ToggleLatch

EnableEnable





up / down

up / down

11GPT 2GPT 2

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167




- Timer mode: Internal clock input with prescaler up to 5MHz Timer mode: Internal clock input with prescaler up to 5MHz (200ns)(200ns)


Output modeOutput mode- Interrupt possibility and toggle function of a port line (via a Interrupt possibility and toggle function of a port line (via a

toggle bit)toggle bit)- Output of T6 can be used to clock CAPCOM timersOutput of T6 can be used to clock CAPCOM timers

Count direction of all timers can be dynamically changed Count direction of all timers can be dynamically changed (C167) (C167)

Cascading of timer T6 with timer T5Cascading of timer T6 with timer T5 One 16-Bit Capture(for T5) / Reload(for T6) register One 16-Bit Capture(for T5) / Reload(for T6) register



11GPT 2GPT 2

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167




11GPT 2GPT 2



ModeControl


RunEnable

RunEnable

EnableEnable

InputMode


RunEnable

RunEnable Clk max



Clear

Outp.enablesOutp.

enables

to CAPCOMTimer T0, T1

ToggleLatch

EnableEnable





up / down

up / down

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167




11GPT 2GPT 2



ModeControl


RunEnable

RunEnable

EnableEnable

InputMode


RunEnable

RunEnable Clk max



Clear

Outp.enablesOutp.

enables

to CAPCOMTimer T0, T1

ToggleLatch

EnableEnable





2.5 MHz

max.

2.5 MHz

up / down

up / down

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167




- Timer mode: Internal clock input with prescalerTimer mode: Internal clock input with prescalerup to 6.25MHz (160ns)up to 6.25MHz (160ns)


Output modeOutput mode- Interrupt possibility and toggle function of a port line (via a Interrupt possibility and toggle function of a port line (via a

toggle bit)toggle bit)- Output of T6 can be used to clock CAPCOM timersOutput of T6 can be used to clock CAPCOM timers

Count direction of all timers can be dynamically changedCount direction of all timers can be dynamically changed Cascading of timer T6 with timer T5Cascading of timer T6 with timer T5 One 16-Bit Capture(for T5) / Reload(for T6) register One 16-Bit Capture(for T5) / Reload(for T6) register



11GPT 2GPT 2

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167




11GPT 2GPT 2



ModeControl


RunEnable

RunEnable

EnableEnable

InputMode


RunEnable

RunEnable Clk max



Clear

Outp.enablesOutp.

enables

ToggleLatch

EnableEnable





3.1 MHz

max.

3.1 MHz

up / down

up / down

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Two 16-bit timers (T0, T1) each with 16-bit reload registerTwo 16-bit timers (T0, T1) each with 16-bit reload register- Timer mode: Internal clock input with prescaler up to 2.5 Timer mode: Internal clock input with prescaler up to 2.5

MHz (400ns)MHz (400ns)- Counter mode: External clock input to T0 up to 1.25 MHz, Counter mode: External clock input to T0 up to 1.25 MHz,

output from T6 (GPT2) can be used as clock inputoutput from T6 (GPT2) can be used as clock input Two units with sixteen 16-Bit Capture/Compare registersTwo units with sixteen 16-Bit Capture/Compare registers

- Individually programmable for Capture or any Compare Individually programmable for Capture or any Compare modemode

- Individually allocatable to timer T0/T1Individually allocatable to timer T0/T1 Various Compare modes for flex. Pulse Width Various Compare modes for flex. Pulse Width

Modulation(PWM)Modulation(PWM)- Output-Pin toggles if Compare is trueOutput-Pin toggles if Compare is true- 1 or 2 Compare registers can operate to one output-Pin1 or 2 Compare registers can operate to one output-Pin- 1 or more Compare events can be detected in 1 or more Compare events can be detected in

one timer periodone timer period- Interrupt only modeInterrupt only mode

Capture / Compare Unit(CAPCOM)

12PWM generation - CAPCOMPWM generation - CAPCOM

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Two 16-bit timers (T7,T8) each with 16-bit reload registerTwo 16-bit timers (T7,T8) each with 16-bit reload register- Timer mode: Internal clock input with prescaler up to 2.5 Timer mode: Internal clock input with prescaler up to 2.5

MHz (400ns)MHz (400ns)- Counter mode: Output from T3 can be used as clock inputCounter mode: Output from T3 can be used as clock input

One unit with eight 16-Bit Capture/Compare registersOne unit with eight 16-Bit Capture/Compare registers- Individually programmable for Capture or any Compare Individually programmable for Capture or any Compare

modemode- Individually allocatable to timer T7/T8Individually allocatable to timer T7/T8

Various Compare modes for flex. Pulse Width Various Compare modes for flex. Pulse Width Modulation(PWM)Modulation(PWM)- Output-Pin toggles if Compare is trueOutput-Pin toggles if Compare is true- 1 or 2 Compare registers can operate to one output-Pin1 or 2 Compare registers can operate to one output-Pin- 1 or more Compare events can be detected in one timer 1 or more Compare events can be detected in one timer

periodperiod- Interrupt only modeInterrupt only mode

Capture / Compare Unit 2(CAPCOM2)

12PWM generation - CAPCOM 2 PWM generation - CAPCOM 2

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Four 16-bit timers (T0/T1 & T7/T8), 16-bit reload reg. eachFour 16-bit timers (T0/T1 & T7/T8), 16-bit reload reg. each- Timer mode:Timer mode: Int. clock input with up to 2.5 MHz (400ns) Int. clock input with up to 2.5 MHz (400ns)- Counter mode:Counter mode: External clock input to T0/T7 up to 1.25 External clock input to T0/T7 up to 1.25

MHz, Output from T6 can be used as clock inputMHz, Output from T6 can be used as clock input- CAPCOM 2 can be synchronized via T0 to CAPCOM 1CAPCOM 2 can be synchronized via T0 to CAPCOM 1

Two units with sixteen 16-Bit Capture/Compare registersTwo units with sixteen 16-Bit Capture/Compare registers- Individually program. for Capture or any Compare modeIndividually program. for Capture or any Compare mode- Individually allocatable to timer T0/T1 or T7/T8Individually allocatable to timer T0/T1 or T7/T8

Various Compare modes for flexibleVarious Compare modes for flexiblePulse Width Modulation(PWM)Pulse Width Modulation(PWM)- Output-Pin toggles if Compare is trueOutput-Pin toggles if Compare is true- 1 or 2 Compare registers can operate to one Output-Pin1 or 2 Compare registers can operate to one Output-Pin- One or more Compare events can be detected in one timer One or more Compare events can be detected in one timer

periodperiod- Interrupt only modeInterrupt only mode

Capture / Compare Unit 1/2 (CAPCOM 1/2)...

12PWM generation - CAPCOM 1/2 PWM generation - CAPCOM 1/2

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



CAPCOM(1)Function Diagram

InputMode

Control

T0 Reload T0 Reload

RunEnable

RunEnable Clk max


T1 Reload T1 Reload

Timer T1 Timer T1

Timer T0 Timer T0

Mode ControlMode ControlSixteen 16 Bit

Capture/CompareRegister

CC0-CC15





from T6

InputMode

ControlRun

Enable Run

Enable


from T6

Edge Selectfor

Capture Input

- Capture Mode- Compare Mode 0- Compare Mode 1- Compare Mode 2- Compare Mode 3- Double Register Compare Mode 0

12PWM generation - CAPCOM (1) PWM generation - CAPCOM (1)

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



CAPCOM 2Function Diagram

Edge Selectfor

Capture Input

InputMode

Control

T7 Reload T7 Reload

RunEnable

RunEnable Clk max


T8 Reload T8 Reload

Timer T8 Timer T8

Timer T7 Timer T7

Mode ControlMode ControlSixteen 16 Bit


CC16-CC33





from T6

InputMode

ControlRun

Enable Run

Enable


from T6

Channel 24 to 27only CaptureInput possible

Channel 31 is able to triggeran ADC Channel Injection



C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



CAPCOM 2Function Diagram

Edge Selectfor

Capture Input

InputMode

Control

T7 Reload T7 Reload

RunEnable

RunEnable Clk max


T8 Reload T8 Reload

Timer T8 Timer T8

Timer T7 Timer T7

Mode ControlMode Controleight 16 Bit


CC16-CC19CC24-CC27





from T6

InputMode

ControlRun

Enable Run

Enable


from T6

Channel 24 to 27only CaptureInput possible

Channel 27 is able to triggeran ADC Channel Injection



C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



CAPCOM 1/2Compare Mode 0 and 1

Mode 0: only INTR Flag is set

Mode 1: INTR Flag is setand Port Pin is toggled

Compare Value 2

Compare Value 1

FFFF

Reload Value

New

Reload ValueCompare Register X: Value 1 Value 2

is changed toC

om

par

e IN

TR

Timer INTR

Co

mp

are

INT

R

Several Compare events are possible within a single Timer Several Compare events are possible within a single Timer periodperiod

12

Port Level P1.xP8.x (C164)

PWM generation - CAPCOM 1/2 PWM generation - CAPCOM 1/2

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Mode 2: only INTR Flag is set

Mode 3: INTR Flag is set.Port Pin is set at the first Compare Event and reset at Timer overflow

CAPCOM 1/2 Compare Mode 2 and 3

Compare Value 2

Compare Value 1

FFFF

Reload Value

New

Reload ValueCompare Register X: Value 1 Value 2

is changed toC

om

par

e IN

TR

Tim

er IN

TR

Only one Compare events is possible within a single Timer Only one Compare events is possible within a single Timer periodperiod

12



C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Bank1 Compare Register X:(programmed to mode 1)

the associated

Bank2 Compare Register Y:(programmed to mode 0)

CAPCOM 1/2 Double Register Compare Mode

Compare Value 2

Compare Value 1

FFFF

Reload Value

New

Reload Value Value X

Value Y

Co

mp

are

INT

R

Reg

. YTimer INTR

Co

mp

are

INT

R

Reg

. X

Two Compare Register work together to control one Port Two Compare Register work together to control one Port PinPin

This mode is selected by a special combination of the This mode is selected by a special combination of the mode 0 and 1mode 0 and 1

12



C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Pulse Width Modulation Unit (PWM)

4 completely indep. PWM channels each with its own time-4 completely indep. PWM channels each with its own time-basebase- 50ns or 12.8µs timer-resolution provides a very wide 50ns or 12.8µs timer-resolution provides a very wide

frequency range to generate PWM signals frequency range to generate PWM signals - Programmable output polarityProgrammable output polarity- Up to 78 KHz at 8-bit PWM resolutionUp to 78 KHz at 8-bit PWM resolution

Four operation modesFour operation modes- Standard, edge-aligned PWMStandard, edge-aligned PWM- Symmetrical, center-aligned PWM for asynchronous motor Symmetrical, center-aligned PWM for asynchronous motor

controlcontrol- Burst-mode for modulated PWM signalsBurst-mode for modulated PWM signals- Single-shot modeSingle-shot mode

FPWM =1

2 x 50ms 8-bit

12

=78 KHz

PWM generation - PWM unit PWM generation - PWM unit

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



PWM unitFrequencies and Resolution

PMW Unit Frequencies and Resolution in Mode 1 Operation (SYMMETRICAL)(SYMMETRICAL)

PMW Unit Frequencies and Resolution in Mode 0 Operation (EDGE-ALIGNED)(EDGE-ALIGNED)

Resolution Resolution

Input ClockInput Clock (CPU @ 20 MHz)

8 Bit 10 Bit 12 Bit 14 Bit 16 Bit

CPU Clock (50ns Resolution)

CPU Clock / 64 (3.2µs Res.)

39.1 KHz

610 Hz

9.77 KHz

152.6 Hz

2.44 KHz

38.15 Hz

610 Hz

9.54 Hz

152.6 Hz

2.4 Hz

Resolution Resolution

Input ClockInput Clock (CPU @ 20 MHz)

8 Bit 10 Bit 12 Bit 14 Bit 16 Bit

CPU Clock (50ns Resolution)

CPU Clock / 64 (3.2µs Res.)

78.1 KHz

1.22 KHz

19.5 KHz

305 Hz

4.88 KHz

76.3 Hz

1.22 KHz

13.1 Hz

305 Hz

4.77 Hz

12PWM generation - PWM unit PWM generation - PWM unit

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



RunEnable

RunEnable

Timer PT0-PT3

Comparator

Shadow Register


PWM unitFunction Diagramm

InputMode

Control

Pulse Width Reg. PW0-PW3

Shadow Register

4 identical PWM Channels with common Interrupt Control Register

Period Register PP0-PP3

Output PolarityEnable

Output PolarityEnable

20 MHz

78 KHz

at 20 MHz CPU Clock

PWMOutputs

Comparator

up/down,clear


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



PWM unitMode 0 and 1...

Contents of the PWx Register

Interrupt Request andLatch of the Shadow Register

Contents of the PWxRegister

IR and Latch of theShadow Register

Timer Period

Timer Perio

d Timer Period

Contents of the Period Register (PPx)

PWM Mode 0: Standard PWM’s or Edge-Aligned PWM’s

PWM Mode 1: Symmetrical or Center-Aligned PWM’s

PWM Signal

If all channels are programmed to mode 0,edge-aligned PWM signals will be generated.A duty cycle from 0 to 100% is programmable

If all channels are programmed to mode 1,center-aligned PWM signals will be generated.A duty cycle from 0 to 100% is programmable

PWM Signal

Possible PWM Signals from other channels programmed to the same mode:

PWMx

PWMy


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



... PWM unitModes

Burst Mode :Burst Sequence by combiningPWM channel 0 and 1

Single Shot : Only one PWM Pulse is generated Mode available for channel 2 and 3

Period Value Period Value

Pulse widthValue

PeriodValue

Internal Signalof Channel 0

Period ofTimer PT1

Int. Signalof Channel 1

Output Result: Channel 1 is modulated by Channel 0

OutputSignal

Timer isautomatically

stopped

Timer isreleased by

Software again

The Timer can be dynamically changed tolengthen (retrigger) or shorten the output pulse

Tim

er Perio

d

Timer Period PT0


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Capture Compare Unit for flexible PWM Signal GenerationCapture Compare Unit for flexible PWM Signal Generation Optimized for Drive Control ApplicationsOptimized for Drive Control Applications C164CI suitable forC164CI suitable for

- All kinds of inverters All kinds of inverters - Frequency convertersFrequency converters- Motor applications with current control (abc-frame, block Motor applications with current control (abc-frame, block

commutation) commutation) - Motor applications with speed control.Motor applications with speed control.

Same functionality as CCU of C504Same functionality as CCU of C504

Capture / Compare Unit 6(CAPCOM 6)

PWM generation - CAPCOM 6 PWM generation - CAPCOM 6 12

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



CAPCOM 6 - Block Diagram


ModeMode

Offset Reg. T12OFOffset Reg. T12OF

Compare Timer T12

Period Reg. T12PPeriod Reg. T12P CTRAP

CC60 COUT60

CC61 COUT61

CC62 COUT62

FCPU

InputControl

CC Channel 0 CC60CC Channel 0 CC60



deadtimeControl

deadtimeControl

Compare Timer T1310 bitFCPU

InputControl

Period Reg. T13PPeriod Reg. T13P

Comp Reg. CMP13Comp Reg. CMP13

Burst ModeBurst Mode

BlockCommutation

Control

BlockCommutation

Control

COUT63

CC6POS0

CC6POS1

CC6POS2 MM

Po

rt C

on

tro

l Lo

gic

Po

rt C

on

tro

l Lo

gic

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



3-channel 16-bit capture/compare unit (CAPCOM)3-channel 16-bit capture/compare unit (CAPCOM)- CAPCOM6 I/O lines : 2 outputs / channel in compare modeCAPCOM6 I/O lines : 2 outputs / channel in compare mode

1 input in capture mode 1 input in capture mode- Channels independently programmable for capture or Channels independently programmable for capture or

comparecompare

- Compare timer T12 input clock : fCompare timer T12 input clock : fCPUCPU up to f up to fCPUCPU/128/128

- Two operating modes of compare timer T12Two operating modes of compare timer T12

- Mode 0 : up-count and resetMode 0 : up-count and reset

- Mode 1 : up-count and down-countMode 1 : up-count and down-count- Programmable initial logic output level in compare modeProgrammable initial logic output level in compare mode

- 1 compare channel can generate 2 inverted signals1 compare channel can generate 2 inverted signals- Interrupt generation atInterrupt generation at

- compare timer reset / count direction changecompare timer reset / count direction change

- compare match / capture eventcompare match / capture event

CAPCOM 6Features...


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



- External trap input External trap input

- putting selectively compare outputs to low or high levelputting selectively compare outputs to low or high level- Offset register for automatic constant dead-time generationOffset register for automatic constant dead-time generation

1-channel 10-bit compare unit for PWM signal generation 1-channel 10-bit compare unit for PWM signal generation

- Compare timer T13 input clock : fCompare timer T13 input clock : fCPUCPU up to f up to fCPUCPU/128/128

- Edge aligned PWM (compare timer operating mode 0)Edge aligned PWM (compare timer operating mode 0)- PWM output at COUT3PWM output at COUT3

- enable/disable and output level controlenable/disable and output level control- Combination with CAPCOM unitCombination with CAPCOM unit

- Burst modeBurst mode

- Multi-channel PWM modesMulti-channel PWM modes

...CAPCOM 6Features


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Two count modesTwo count modes- Operating mode 0 : 0000H up to period registerOperating mode 0 : 0000H up to period register

value and reset value and reset- Operating mode 1 : up- and down-counting between Operating mode 1 : up- and down-counting between

0000H and period register value 0000H and period register value Compare operation - match eventCompare operation - match event

- CCx outputsCCx outputs toggle state when compare timer matches with toggle state when compare timer matches with compare register contentcompare register content

- COUTx outputsCOUTx outputs toggle state when compare timer matches toggle state when compare timer matches with compare register content plus the value in the T12OF with compare register content plus the value in the T12OF offset register ---> constant dead time generationoffset register ---> constant dead time generation

Capture operationCapture operation- Storing the compare timer T12 value in the Storing the compare timer T12 value in the

capture/compare register at a signal transition (rising/falling capture/compare register at a signal transition (rising/falling edge) at the CCx pinedge) at the CCx pin

CAPCOM 6Compare Timer T12 Operation


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



CAPCOM 6 Compare Timer Operating Mode 0

a) Standard PWM (Edge Aligned) b) Standard PWM (Single Edge Aligned) with constant Single Edge Delay

0000H

CompareValue

PeriodValue

CCX

COUTX

Offset

CompareValue

PeriodValue

CCX

COUTX

tOff

Both compare timers can use this operating modeBoth compare timers can use this operating mode


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



CAPCOM 6 Compare Timer Operating Mode 1

c) Symetrical PWM (Center Aligned) d) Symetrical PWM (Center Aligned) with constant Edge Delay

0000H

CompareValue

PeriodValue

CCX

COUTX

Offset

CompareValue

PeriodValue

CCX

COUTX

tOff

Only compare timer T12 can operate is this mode Only compare timer T12 can operate is this mode

tOff


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



CAPCOM 6Compare Timer Operating Mode 1

Count ValueCount Value

2

3

4

5

6

7

6

5

4

3

2

3

4

5

0

1

2

3

4

5

6

7

6

5

4

3

2

1

0

1

2

3

4

5

8

9

8

7

6

7

TimeTime

29%

57%

57%

tOfftOff Duty Cycles:

T12 + T12OFT12 + T12OF

T12T12

CCP=7Period Reg.

T12OF=2Offset Reg.

Start of T12Start of T12

CCx (CC=5)COINI Bit=0

COUTx (CC=5)COINI Bit=0

COUTx (CC=5)COINI Bit=0


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



CAPCOM 6 Multi-Channel PWM Modes...

Special operating mode of the CAPCOM6, in which Special operating mode of the CAPCOM6, in which CAPCOM and COMP unit are providing versatile PWM CAPCOM and COMP unit are providing versatile PWM compare output waveformscompare output waveforms

Four operating modes :Four operating modes :- Block commutation mode (e.g.for decoding of hall sensor Block commutation mode (e.g.for decoding of hall sensor

signals)signals)- 4-pole multi-channel PWM 4-pole multi-channel PWM - 5-pole multi-channel PWM 5-pole multi-channel PWM - 6-pole multi-channel PWM6-pole multi-channel PWM

......


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



CAPCOM 6 ...Multi-Channel PWM Modes

Block commutation mode :Block commutation mode :- Position input (CC6POS0# - CC6POS2#) controlled PWM Position input (CC6POS0# - CC6POS2#) controlled PWM

timing generationtiming generation- Implementation of a specific control table for hall sensor Implementation of a specific control table for hall sensor

input signals at the interrupt inputsinput signals at the interrupt inputs Multi-pole multi-channel PWM modes :Multi-pole multi-channel PWM modes :

- Compare timer T12 controlled, fixed basic PWM compare Compare timer T12 controlled, fixed basic PWM compare output timing pattern of active and inactive phase at 4, 5, or output timing pattern of active and inactive phase at 4, 5, or 6 CCx/COUTx outputs6 CCx/COUTx outputs

Special control registerSpecial control register


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



CAPCOM 6 Block Commutation Mode...

1 1 1 0 0 0

011100

1 0 0 0 1 1

CC6POS0#CC6POS0#

CC6POS1#CC6POS1#

CC6POS2#CC6POS2#

CC0

CC1

CC2

COUT0

COUT1

COUT2

InputSignals

OutputSignals


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



CAPCOM 6 Block Commutation Mode

Controlled by a fixed pattern table for interrupt input Controlled by a fixed pattern table for interrupt input signalssignals- Specific motor control modeSpecific motor control mode- Control table covers rotate-left/-right/idle/slow-down case Control table covers rotate-left/-right/idle/slow-down case

for motor hall sensor input signalsfor motor hall sensor input signals- CCx unmodulated / COUTx modulated with compare timer CCx unmodulated / COUTx modulated with compare timer

T13 outputT13 output


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



CAPCOM 6 5-Pole Multi-Channel PWM Mode...

Start

activephase

CompareTimer T12

CC0

COUT1

CC2

COUT0

COUT2

or

Active phase modulatedby Compare Timer T12

Active phase modulatedby Compare Timer T13


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



CAPCOM 6 ...5-Pole Multi-Channel PWM Mode

Active phase can be modulated byActive phase can be modulated by- Compare timer T12 :Compare timer T12 : modulation for two compare timer modulation for two compare timer

T12 periodsT12 periods- Compare timer T13 :Compare timer T13 : compare timer T13 output signal compare timer T13 output signal

is switched to CCxis switched to CCxor COUTx during active phaseor COUTx during active phase

Programmable polarity of active/inactive phaseProgrammable polarity of active/inactive phase


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



CAPCOM 6 ...Block Commutation Mode

BitNMCS

CC0

COUT1

CC2

COUT0

COUT2

Static level during active phase(at CCx and COUTx outputs)

Compare Timer T13 modulationduring active phase

10

1 2 3 4 5 1 2 3 4 5 1

activephase

Setting bit NMCS bysoftware

5-Pole Multi-Channel PWM Mode:Rotate Left Mode (BCM1,0 =1,0) with COINI XX111111B


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



CAPCOM 6 Drive Applications Area


AC Drives ("Drehstrommotoren") XX

- Synchronous motors, Brushless DC motors ("Synchronmotoren") XX

- Induction motors ("Asynchronmotoren") XX

- Reluctance motors ("Reluktanzmotoren") XX

Stepper Motors ("Schrittmotoren") -

- Unipolar stepper motors ("Unipolare Schrittmotoren") XX

- Bipolar stepper motors ("Bipolare Schrittmotoren") XX

DC Drives ("Gleichstrommotoren") XX

with C164CI

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Analog Digital Converter(ADC) - C161RI only

8-Bit ADC based on the successive approximation 8-Bit ADC based on the successive approximation principleprinciple- flexible conversion-time control with minimal flexible conversion-time control with minimal

7.5µs conversion-time7.5µs conversion-time- On-chip sample- & hold-circuit On-chip sample- & hold-circuit

(1.5 µs sample-time)(1.5 µs sample-time) 4 multiplexed input channels 4 multiplexed input channels

- Fixed channel single channel conversionFixed channel single channel conversion- Fixed channel single channel continuous conversion for Fixed channel single channel continuous conversion for

permanent data trackingpermanent data tracking 8-bit result can be left- or right- adjusted to a 8-bit result can be left- or right- adjusted to a

10-bit field10-bit field Interrupt onInterrupt on

- Overrun errorOverrun error- Conversion completeConversion complete

ADCADC13

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



8-Bit A/D ConverterBlock Diagram - C161RI only

AnalogInputs

Channel and Mode Control Conversion Control


ReferenceVoltage

4ChannelAnalogMUX

C-NETSwitch

Tree

Com-parator

Timing Controland Successive Approximation

Register



Result Register

13ADCADC

prescaler

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Analog Digital Converter(ADC)

10-Bit ADC based on the successive approximation 10-Bit ADC based on the successive approximation principleprinciple- 9.7µs conversion-time9.7µs conversion-time- On-chip sample- & hold-circuit (1.6 us sample-time)On-chip sample- & hold-circuit (1.6 us sample-time)

10 multiplexed input channels 10 multiplexed input channels - Flexible operation modeFlexible operation mode- Single-channel and single-channel-continuous for periodic Single-channel and single-channel-continuous for periodic

data acquisitiondata acquisition- Auto-scan and auto-scan-continuous for permanent data Auto-scan and auto-scan-continuous for permanent data

trackingtracking Easy error handling and channel identificationEasy error handling and channel identification

- 10-bit result and channel number in result register10-bit result and channel number in result register- Overrun error checkOverrun error check

ADCADC13

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



10-Bit A/D ConverterBlock Diagram

AnalogInputs



ReferenceVoltage

10 (16)ChannelAnalogMUX

C-NETSwitch

Tree

Com-parator



13ADCADC


Register

Channel

Information Result Register

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167




10-Bit ADC based on the successive approximation 10-Bit ADC based on the successive approximation principleprinciple- 9.7µs conversion-time9.7µs conversion-time- On-chip sample- & hold-circuit (1.6 us sample-time)On-chip sample- & hold-circuit (1.6 us sample-time)- 8 multiplexed input channels8 multiplexed input channels- Automatic self-calibration after conversion Automatic self-calibration after conversion

Flexible operation modeFlexible operation mode- Single-channel and single-channel-continuous for periodic Single-channel and single-channel-continuous for periodic


trackingtracking- Channel-injection mode with own result-register can be Channel-injection mode with own result-register can be

used to interrupt the scan modes used to interrupt the scan modes Easy error handling and channel identificationEasy error handling and channel identification


13ADCADC

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167




10-Bit ADC based on the successive approximation 10-Bit ADC based on the successive approximation principleprinciple- 9.7µs conversion-time9.7µs conversion-time- On-chip sample- & hold-circuit (1.6 us sample-time)On-chip sample- & hold-circuit (1.6 us sample-time)- 16 Multiplexed input channels16 Multiplexed input channels- Automatic self-calibration after conversion Automatic self-calibration after conversion

Flexible operation modeFlexible operation mode- Single-channel and single-channel-continuous for periodic Single-channel and single-channel-continuous for periodic


trackingtracking- Channel-injection mode with own result-register can be Channel-injection mode with own result-register can be

used to interrupt the scan modes used to interrupt the scan modes Easy error handling and channel identificationEasy error handling and channel identification


13ADCADC

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



AnalogInputs



ReferenceVoltage

8 (16)ChannelAnalogMUX

C-NETSwitch

Tree

Com-parator



10-Bit A/D ConverterBlock Diagram

13ADCADC


Register

Channel

Information Result Register

Channel

Selection Result Register for Channel Injection Mode

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Synchronous / asynchronous serial channel with its own Synchronous / asynchronous serial channel with its own baud-rate-generatorbaud-rate-generator

Asynchronous mode with max 500 KBaud transfer rate Asynchronous mode with max 500 KBaud transfer rate - Full duplex (receive and transmit at the same time)Full duplex (receive and transmit at the same time)- programmable features:programmable features:- 1 or 2 stop bits, 7, 8 or 9 data bits1 or 2 stop bits, 7, 8 or 9 data bits- Generation of parity- or wake-up bit at data transmissionGeneration of parity- or wake-up bit at data transmission- Odd or even parity Odd or even parity - Error detection (parity, overrun, framing)Error detection (parity, overrun, framing)- Wake-up check (receive int. flag is set if wake-up bit is true)Wake-up check (receive int. flag is set if wake-up bit is true)

Synchronous mode with max 2.0 Mbit/sec transfer rangeSynchronous mode with max 2.0 Mbit/sec transfer range- Half duplex operation (only transmit or receive possible)Half duplex operation (only transmit or receive possible)- Easy I/O expansion with external shift registerEasy I/O expansion with external shift register- Overrun error detectionOverrun error detection

USARTUSART

Asynchronous / SynchronousSerial Channel (USART) at 16MHz

14

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167






USARTUSART


14

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



INTRINTR FlagFlag

TransmitTransmit

INTRINTR FlagFlag

TransmitTransmit

INTRINTR FlagFlag

ReceiveReceive

INTRINTR FlagFlag

ReceiveReceive

INTRINTR FlagFlag

ERRORERROR

INTRINTR FlagFlag

ERRORERROR

to internal Bus

CPU CLK Baud Rate Generator

Control Reg.

ControlUnit

Transmit Shift Register

Receive Shift Register

Receive Buffer

from internal Bus

Shift CLK

Asynchronous/

Synchronous

Port Pin

Port Pin

Port Pin

Port Pin

USART Block Diagram

14USARTUSART

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Synchronous Serial Channel(SSC), SPI compatible at 16MHz

Full duplex Synchronous Serial Channel (SSC) with its Full duplex Synchronous Serial Channel (SSC) with its own baudrate generator for high speed communicationown baudrate generator for high speed communication

Up to 4 Mbit/sec transfer rateUp to 4 Mbit/sec transfer rate SPI compatibleSPI compatible Master (clock is output) or slave mode (clock is input)Master (clock is output) or slave mode (clock is input) Programmable features to satisfy various communication Programmable features to satisfy various communication

requirementsrequirements- MSB or LSB firstMSB or LSB first- Data frame from one to 16-bitData frame from one to 16-bit- Clock polarity and phaseClock polarity and phase

14USARTUSART

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Synchronous Serial Channel(SSC), SPI compatible at 20 MHz


Up to 5 Mbit/sec transfer rateUp to 5 Mbit/sec transfer rate SPI compatibleSPI compatible Master (clock is output) or slave mode (clock is input)Master (clock is output) or slave mode (clock is input) Programmable features to satisfy various communication Programmable features to satisfy various communication


14USARTUSART

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Synchronous Serial Channel(SSC), SPI compatible at 25MHz


Up to 6.25 Mbit/sec transfer rateUp to 6.25 Mbit/sec transfer rate SPI compatibleSPI compatible Master (clock is output) or slave mode (clock is input)Master (clock is output) or slave mode (clock is input) Programmable features to satisfy various communication Programmable features to satisfy various communication


14USARTUSART

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Synchronous Serial Channel - Block Diagram

Baud RateGenerator

ClockControl

Control Unitwith Controland StatusRegisters

Shift Registerprogrammable from 1 - 16-bit

MSB- / LSB-First Selection

Receive Buffer

Transmit Buffer

Internal Bus

InterruptRequest

Slave ModeMaster Mode SSCCLKCPU

Clock Master / Slave Selection

SSCDI

SSCDO

15SSPSSP

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Synchronous Serial Port(SSP)

Synchronous Serial Port was designed for communication Synchronous Serial Port was designed for communication with external slave devices such as EEPROMs with external slave devices such as EEPROMs

SSP can be programmed to...SSP can be programmed to...- send command, address or data information to a peripheralsend command, address or data information to a peripheralreceive data from a peripheralreceive data from a peripheral

Three-wire interface compatible to SPI-protocol Three-wire interface compatible to SPI-protocol - Bi-directional serial data lineBi-directional serial data line- Configurable clock control lineConfigurable clock control line- Two dedicated configurable chip enable linesTwo dedicated configurable chip enable lines- Baudrate up to 12.5 Mbit/s Baudrate up to 12.5 Mbit/s - Heading selectable (LSB / MSB first)Heading selectable (LSB / MSB first)

Busy flag (Check if SSP is busy or idle)Busy flag (Check if SSP is busy or idle) Interrupt (XP1INT) is generated at the end of a transferInterrupt (XP1INT) is generated at the end of a transfer

15SSPSSP

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Synchronous Serial PortBlock Diagram

In order to use the SSP,- Bit XPEREN (SYSCON.2) must be set during

initialization (before EINIT instruction)- Pins P4.4 to P4.7 must not be used as

segment address lines (max. 5 x 1 Mbyte external memory)

Input / OutputControl

SSPDAT(P4.6)

SSPCLK(P4.7)

SSPCE1(P4.4)

SSPCE0(P4.5)

BaudrateGenerator

OutputControl

OutputControl

SSPCON0SSPCON0

SSPCON1SSPCON1

Interrupt(XP1INT)

ControlControlLogicLogic

XBUS-Interface

ClockControl

ChipEnableControl

8 bit8 bit 8 bit8 bit 8 bit8 bit

SSPTB2 SSPTB1SSPTB0/SSPRB0

Shift Unit & Shift Control

15SSPSSP

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Synchronous Serial Port Detailed Block Diagram

SSPCON0

SSPCON1

Clock Generator

Shift / Load

1-Byte

2-Byte

3-Byte

CS1

CS0SS

PC

ON

TR

OL

LE

R

INTERNAL BUSXBCON XADRS

X-BUS CONTROLLER

8

SSPCE0 (P4.5)

SSPCE1(P4.4)

SDATA I/O(P4.6)

88

SSPTB0/SSPRB0

SSPTB1 SSPTB2SIN SOUT

0

1

SIN SOUT0

1

SIN SOUT

0

1

SCLK (P4.7)

15SSPSSP

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Synchronous Serial Port Configurations...

Configuration of the Chip Enable lines:Configuration of the Chip Enable lines:- Chip Enable lines may be selected separately:Chip Enable lines may be selected separately:

- no Chip Enable line selectedno Chip Enable line selected

- Chip Enable line 0 (SSPCE0) selectedChip Enable line 0 (SSPCE0) selected

- Chip Enable line 1 (SSPCE1) selectedChip Enable line 1 (SSPCE1) selected

- Both Chip Enable lines selected (take care with READ-Both Chip Enable lines selected (take care with READ-operations)operations)

- Polarity can be selected for each Chip Enable linePolarity can be selected for each Chip Enable line (active high / active low) (active high / active low)

15SSPSSP

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Configuration of the Clock line (like SSC on C167/C165)Configuration of the Clock line (like SSC on C167/C165)- Clock polarity can be selected:Clock polarity can be selected:

- Idle Clock line high (leading clock edge is high-to- Idle Clock line high (leading clock edge is high-to- low transition)low transition)

- Idle Clock line low (leading clock edge is low-to-high Idle Clock line low (leading clock edge is low-to-high transition)transition)

- Clock edge can be selected:Clock edge can be selected:

- Shift data on leading clock edge, latch on trailing edgeShift data on leading clock edge, latch on trailing edge

- Latch data on leading clock edge, shift on trailing edgeLatch data on leading clock edge, shift on trailing edge

...Synchronous Serial Port Configurations

15SSPSSP

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Differences between SSP and SSC

SSP (C163)

Up to 10 MBaud @ 20 MHz CPUclock

Only half duplex communicationpossible;

one bidirectional data lineShift clock can only be generated

(master only)Data width 1 byte

No error detection mechanismsTwo dedicated chip enable lines

Connected to XBUS1 interrupt source dedicated to SSP

Synchronous Serial PortSSCSSC

Up to 5 MBaud @ 20 MHz CPUUp to 5 MBaud @ 20 MHz CPUclockclock

Full duplex communicationFull duplex communicationpossible;possible;

two data lines (Transmit, Receive)two data lines (Transmit, Receive)

Shift clock can be generatedShift clock can be generated(master) or received (slave)(master) or received (slave)

Data width can be chosen from 2Data width can be chosen from 2bits to 16 bitsbits to 16 bits

Error detection mechanismsError detection mechanisms

No dedicated chip enable linesNo dedicated chip enable lines

Connected to Internal BusConnected to Internal Bus

3 interrupt sources dedicated to3 interrupt sources dedicated toSSCSSC

Synchronous Serial ChannelSynchronous Serial Channel

SSP vs. SSCSSP vs. SSC16

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Serial E2PROM connected to SSP

P4.4 / SSPCE1

P4.5 / SSPCE0

P4.6 / SSPDAT

P4.7 / SSPCLK

CS#(Chip Select)

SO(Serial DataOutput)

SI(Serial DataInput)

SCK(Clock)

C163 EEPROM(e.g. X25C02)

Application for the SSPApplication for the SSP17

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Single Write Operation toEEPROM (X25C02)

SSPCLK

SSPDAT

SSPCE0/1

WriteEnable

WriteCommand

Address(e.g. A5h)

Data(e.g. 99h)

>500 ns

SSPTB0 = 0x06;/* Write Enable */

SSPTB2 = 0x02; /* Write Command */SSPTB1 = 0xA5; /* Address */SSPTB0 = 0x99; /* Data */

Note: - After the data has been written, the EEPROM needs 10 ms to store the data.- SSPCON 0 and SSPCON 1 must be configured before the operation.

17Application for the SSPApplication for the SSP

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Single Read Operation toEEPROM (X25C02)

ReadCommand

Address(e.g. A5h)

Data(e.g. 99h)

sent by EEPROM

SSPTB1 = 0x03; /* Read Command */SSPTB0 = 0xA5; /* Address */

SSPCLK

SSPDAT

SSPCE0/1

Note: SSPCON 0 and SSPCON 1 must be configured before the operation.

one clock-cycle needed for EEPROM to respond

17Application for the SSPApplication for the SSP

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Siemens, The CAN Reference!

CAN Bus CAN Bus 18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



CAN is low costCAN is low cost- Serial bus with two wires: good price/performance ratioSerial bus with two wires: good price/performance ratio- Low cost protocol devices available driven by high volume Low cost protocol devices available driven by high volume

production in the automotive and industrial marketsproduction in the automotive and industrial markets- About 15.000.000 CAN nodes in use so farAbout 15.000.000 CAN nodes in use so far

CAN is reliableCAN is reliable- Sophisticated error detection and error handling Sophisticated error detection and error handling

mechanisms results in high reliability transmissionmechanisms results in high reliability transmission- Example: 500 kbit/s, 25% bus load, 2000 hours per year:Example: 500 kbit/s, 25% bus load, 2000 hours per year:

One undetected error every 1000 yearsOne undetected error every 1000 years- Erroneous messages are detected and repeatedErroneous messages are detected and repeated- Every bus node is informed about an errorEvery bus node is informed about an error- High immunity to Electromagnetic InterferenceHigh immunity to Electromagnetic Interference

......

User Benefits...

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



CAN means real-timeCAN means real-time- Short message length (0 to 8 data bytes / message)Short message length (0 to 8 data bytes / message)- Low latency between transmission request and actual start Low latency between transmission request and actual start

of transmissionof transmission- Inherent Arbitration on Message Priority (AMP) Inherent Arbitration on Message Priority (AMP) - Multi Master using CSMA/CD + AMP methodMulti Master using CSMA/CD + AMP method

CAN is flexibleCAN is flexible- CAN Nodes can be easily connected / disconnectedCAN Nodes can be easily connected / disconnected

(i.e. plug & play)(i.e. plug & play)- Number of nodes not limited by the protocolNumber of nodes not limited by the protocol

CAN is fastCAN is fast- maximum data rate is 1 MBit/s @ 40 m bus lengthmaximum data rate is 1 MBit/s @ 40 m bus length

(still about 40 kBit/s @ 1000 m bus length)(still about 40 kBit/s @ 1000 m bus length) ......

...User Benefits...

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



CAN allows Multi-Master OperationCAN allows Multi-Master Operation- Each CAN node is able to access the busEach CAN node is able to access the bus- Bus communication is not disturbed by faulty nodesBus communication is not disturbed by faulty nodes- Faulty nodes self swith-off from bus communicationFaulty nodes self swith-off from bus communication

CAN means Broadcast CapabilityCAN means Broadcast Capability- Messages can be sent to single/multiple nodesMessages can be sent to single/multiple nodes- All nodes simultaneously receive common data All nodes simultaneously receive common data

CAN is standardizedCAN is standardized- ISO-DIS 11898 (high speed applications)ISO-DIS 11898 (high speed applications)- ISO-DIS 11519-1 (low speed applications)ISO-DIS 11519-1 (low speed applications)

...User Benefits

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



CAN Application Layer (CAL)CAN Application Layer (CAL)- Layer-7-standard defined by CiA (CAN in Automation)Layer-7-standard defined by CiA (CAN in Automation)- Network management service provides initialisation, Network management service provides initialisation,

surveillance and configuration of nodes in a standardized surveillance and configuration of nodes in a standardized wayway

- Takes care of all aspects for the realisation of open Takes care of all aspects for the realisation of open communication via CAN (makes sure manufacturer-specific communication via CAN (makes sure manufacturer-specific systems work together)systems work together)

- Available implementations of CAL make it easy for the user Available implementations of CAL make it easy for the user to define sophisticated standardized Controller Area to define sophisticated standardized Controller Area NetworksNetworks

......

Higher Layer Protocols...

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



CANopen (CiA DS-301)CANopen (CiA DS-301)- Application profile based on CALApplication profile based on CAL- While CAL determines the While CAL determines the wayway of communicating, an of communicating, an

Application Profile determines the Application Profile determines the meaningmeaning of specific of specific messages for the respective application messages for the respective application

- Target: device interchangeability for certain applicationsTarget: device interchangeability for certain applications Further higher level protocols / standards:Further higher level protocols / standards:

- Automotive Sector: VOLCANO, OSEK (in development)Automotive Sector: VOLCANO, OSEK (in development)- Industrial Automation: DeviceNet (Allen Bradley),Industrial Automation: DeviceNet (Allen Bradley),

SDS (Honeywell)SDS (Honeywell)

...Higher Layer Protocols

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



CAN in motor vehicles (cars, trucks, buses)CAN in motor vehicles (cars, trucks, buses)- Enables communication between ECUs like engine Enables communication between ECUs like engine

management system, anti-skid braking, gear control, active management system, anti-skid braking, gear control, active suspension ... (power train)suspension ... (power train)

- Used to control units like dashboard, lighting, air Used to control units like dashboard, lighting, air conditioning, windows, central locking, airbag, seat belts conditioning, windows, central locking, airbag, seat belts etc. (body control)etc. (body control)

CAN in utility vehiclesCAN in utility vehicles- e.g. construction vehicles, forklifts, tractors etc.e.g. construction vehicles, forklifts, tractors etc.- CAN used for power train and hydraulic control CAN used for power train and hydraulic control

......

Application Examples...

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



CAN in trainsCAN in trains- High need of data exchange between the different High need of data exchange between the different

electronic subsystem control unitselectronic subsystem control units- Mainly data about acceleration, braking, door control, error Mainly data about acceleration, braking, door control, error

messages etc. but also for diagnosismessages etc. but also for diagnosis CAN in industrial automationCAN in industrial automation

- Excellent way of connecting all kinds of automation Excellent way of connecting all kinds of automation equipment (control units, sensors and actuators)equipment (control units, sensors and actuators)

- Used for initialization, program and parameter Used for initialization, program and parameter up-/download, exchange of rated values / actual values, up-/download, exchange of rated values / actual values, diagnosis etc.diagnosis etc.

- Machine control (printing machines, paper- and textile Machine control (printing machines, paper- and textile machines etc.): Connection of the different intelligent machines etc.): Connection of the different intelligent subsystemssubsystems

- Transport systemsTransport systems ......

...Application Examples...

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



CAN in medical equipmentCAN in medical equipment- Computer tomographs, X-ray machines, dentist chairs, Computer tomographs, X-ray machines, dentist chairs,

wheel chairswheel chairs CAN in building automationCAN in building automation

- Heating, air conditioning, lighting, surveillance etc.Heating, air conditioning, lighting, surveillance etc.- Elevator and escalator controlElevator and escalator control

CAN in household appliancesCAN in household appliances- Dishwashers, washing machines, even coffee machines...Dishwashers, washing machines, even coffee machines...

CAN in office automationCAN in office automation- photo copier, interface to document handler, paper feedingphoto copier, interface to document handler, paper feeding

systems, sortersystems, sorter- communicates status, allows in field connection or "hot communicates status, allows in field connection or "hot

swapping"swapping"- DocuText Systems, i.e. automatic print, sort and bind on DocuText Systems, i.e. automatic print, sort and bind on

demanddemand

...Application Examples

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Developed in the mid-eighties by BOSCHDeveloped in the mid-eighties by BOSCH Asynchronous serial bus with linear bus structure and Asynchronous serial bus with linear bus structure and

equal nodes (Multi Master bus)equal nodes (Multi Master bus) CAN does not address nodes (address information is CAN does not address nodes (address information is

inside the messages combined with message priority)inside the messages combined with message priority) Two bus states: dominant and recessiveTwo bus states: dominant and recessive Bus logic according to "Wired-AND" mechanism:Bus logic according to "Wired-AND" mechanism:

dominant bits (Zeros) override recessive bits (Ones)dominant bits (Zeros) override recessive bits (Ones) Bus Access via CSMA/CD with NDA (Carrier Sense Bus Access via CSMA/CD with NDA (Carrier Sense

Multiple Access/ Collision Detection with Non-Destructive Multiple Access/ Collision Detection with Non-Destructive Arbitration)Arbitration)

Some things worth knowing about CAN...

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



...Some things worth knowing about CAN

NODE A

NODE B

recessive

dominant

recessive

dominant

bus idle

CAN BUS

recessive

dominant

Node B sends out recessive

but reads back dominant level

Node B loses arbitration

and switches to receive

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Typical CAN node structure

CAN_H

CAN_L

e.g.SAE81C90

CAN- Transceiver

CAN-Bus

CAN-Controller

Host-Controller

Application

e.g.80C166

e.g.ABS

e.g.C167CR

orC515C

e.g.EMS

Node A Node B

(more nodes)

UDiff

CAN

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



There are mainly two ways of communicating:There are mainly two ways of communicating:- One node is 'talking', all other nodes 'listen'One node is 'talking', all other nodes 'listen'- Node A is asking Node B for something and gets the Node A is asking Node B for something and gets the

answer.answer. To 'talk', CAN nodes use To 'talk', CAN nodes use Data FramesData Frames..

- A Data Frame consists of an Identifier, the data to be A Data Frame consists of an Identifier, the data to be transmittedand a CRC-Checksum.transmittedand a CRC-Checksum.

CAN Data Frames...

Identifier CRC-FieldData Field (0..8 Bytes)

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



- The identifier specifies the contents of the messageThe identifier specifies the contents of the message('engine speed', 'oil temperature', etc.) and the message ('engine speed', 'oil temperature', etc.) and the message priority priority

- The Data Field contains the corresponding valueThe Data Field contains the corresponding value('6000 rpm', '110°C', etc.)('6000 rpm', '110°C', etc.)

- The Cyclic Redundancy Check is used to detect The Cyclic Redundancy Check is used to detect transmission errors.transmission errors.

- All nodes receive the Data Frame. Those who do not need All nodes receive the Data Frame. Those who do not need the information, just don't store it.the information, just don't store it.

...CAN Data Frames

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



To 'ask' for information, CAN nodes use To 'ask' for information, CAN nodes use Remote FramesRemote Frames..- A Remote Frame consists of the Identifier and the CRC-A Remote Frame consists of the Identifier and the CRC-

Checksum.Checksum.It contains no data.It contains no data.

- The identifier contains the information that is requestedThe identifier contains the information that is requested('engine speed', 'oil temperature', etc.) and the message ('engine speed', 'oil temperature', etc.) and the message priority.priority.

- The node that is supposed to provide the requested The node that is supposed to provide the requested informationinformation(e.g. the sensor for the oil temperature) does so by sending (e.g. the sensor for the oil temperature) does so by sending the corresponding Data Frame (same identifier, the Data the corresponding Data Frame (same identifier, the Data Field contains the desired information).Field contains the desired information).

CAN Basics...

Identifier CRC-Field

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



...CAN Basics

Data Frame; Identifier 'oil_tmp';contains desired information

~~~~~~~~~~

Remote Frame; Identifier 'oil_tmp'Node A

Node B

(oil temp.-sensor)

How hot is the oil ?

115°C

115 °C !

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Standard CAN /Extended CAN...

Most CAN nodes talk in the 'language' that most other Most CAN nodes talk in the 'language' that most other CAN nodes understand: They use CAN nodes understand: They use StandardStandard Data or Data or Remote Frames.Remote Frames.- A Standard Frame contains an identifier which is 11 bits A Standard Frame contains an identifier which is 11 bits

long.long.- With this 11 bits, 2With this 11 bits, 21111 (=2048) different messages can be (=2048) different messages can be

addressed.addressed.- CAN nodes using Standard-CAN-Frames use the CAN CAN nodes using Standard-CAN-Frames use the CAN

Specification Version 2.0A.Specification Version 2.0A. Some CAN nodes talk with a special 'accent':Some CAN nodes talk with a special 'accent':

They use They use Extended Extended Data or Remote Frames.Data or Remote Frames.- An Extended Frame contains an identifier which is 29 bits An Extended Frame contains an identifier which is 29 bits

long.long.- ......

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



...Standart CAN /Extended CAN...

- Over 536 million (2Over 536 million (22929) different messages can be ) different messages can be addressed.addressed.

- CAN nodes using Extended-CAN-Frames use the CAN CAN nodes using Extended-CAN-Frames use the CAN Specification Version 2.0B (active).Specification Version 2.0B (active).

Some Standard-CAN nodes don't understand this 'accent', Some Standard-CAN nodes don't understand this 'accent', but they tolerate it and just don't care.but they tolerate it and just don't care.- If an Extended Frame is 'on the air', these CAN nodes If an Extended Frame is 'on the air', these CAN nodes

cannot store the data, but they as well do not produce cannot store the data, but they as well do not produce errors.errors.

- These CAN nodes use CAN Version 2.0A, but are also These CAN nodes use CAN Version 2.0A, but are also known as Version 2.0B passive.known as Version 2.0B passive.

- They can be used in a Controller Area Network where They can be used in a Controller Area Network where Extended Frames are used.Extended Frames are used.

......

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



...Standart CAN /Extended CAN

Some Standard-CAN nodes don't understand and also Some Standard-CAN nodes don't understand and also don't tolerate this 'accent'. don't tolerate this 'accent'. - If an Extended Frame is 'on the air', these CAN nodes If an Extended Frame is 'on the air', these CAN nodes

produce errors.produce errors.- These CAN nodes use only CAN Version 2.0A.These CAN nodes use only CAN Version 2.0A.- They can They can not not be used in a Controller Area Network where be used in a Controller Area Network where

Extended Frames are used.Extended Frames are used.

16 bit parts: 16 bit parts: C167CR, C164CIC167CR, C164CI: V2.0B active: V2.0B active

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Basic CAN /Full CAN...

In some CAN controllers, only the basic CAN functions are In some CAN controllers, only the basic CAN functions are implemented. They are called implemented. They are called Basic-CANBasic-CAN controllers. controllers.- Mostly there's only one transmit buffer and one or two Mostly there's only one transmit buffer and one or two

receive buffers for transmission and reception of the Data- / receive buffers for transmission and reception of the Data- / Remote Frames.Remote Frames.

- Each incoming message is stored. The host CPU has to Each incoming message is stored. The host CPU has to decide whether the message data is needed or not.decide whether the message data is needed or not.

- Therefore these controllers should only be used in CANs Therefore these controllers should only be used in CANs with very low baudrates and/or very few messages because with very low baudrates and/or very few messages because of the high CPU load. Advantage: They use the least of the high CPU load. Advantage: They use the least possible silicon area.possible silicon area.

...... ReceivedMessage

sReceive Buffer

CAN Bus

Host CPU

Transmit Buffer

CPU load

low high

Basic-CAN Controller

Messages

to be sent

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



...Basic CAN /Full CAN...

In the other CAN controllers, also message management In the other CAN controllers, also message management and acceptance filtering are implemented. They are calledand acceptance filtering are implemented. They are called Full-CAN Full-CAN controllers.controllers.- There are several Message Objects, each with its own There are several Message Objects, each with its own

identifier.identifier.- Only if a message for one of these preprogrammed Only if a message for one of these preprogrammed

identifier is received, it is stored and the CPU is interrupted.identifier is received, it is stored and the CPU is interrupted.- In this way, the CPU load is low.In this way, the CPU load is low.

......

Full-CAN Controller

Message Object 2

CAN Bus

Host CPU

Message Object n CPU load

low high

Message Object 1

.

.

Accep-tance

Filtering

MessageManage-

ment

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



...Basic CAN /Full CAN

All SiemensAll Siemens CAN-Controllers are CAN-Controllers are Full-CANFull-CAN controllers. controllers.But they But they alsoalso provide provide Basic-CANBasic-CAN functionality functionality- one message object can be used like a Basic CAN receive one message object can be used like a Basic CAN receive

registerregister

CAN BusCAN Bus18

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Features of the CAN Module onC167CR / C164CI...

19

Functionality corresponds to Functionality corresponds to AN 82527AN 82527

Complies with CAN spec Complies with CAN spec V2.0B activeV2.0B active(Standard- und Extended-CAN)(Standard- und Extended-CAN)

Maximum CAN Transfer RateMaximum CAN Transfer Rate(1 MBit/s)(1 MBit/s)

Full CAN DeviceFull CAN Device- 15 Message Objects with 15 Message Objects with

their own identifier and their their own identifier and their own status- and control bitsown status- and control bits

- Each Message Object can Each Message Object can be definedbe definedas Transmit- or Receive as Transmit- or Receive ObjectObject

......

CAN ModuleCAN Module

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



...Features of the CAN Module onC167CR / C164CI

19

Programmable Mask Registers for Acceptance FilteringProgrammable Mask Registers for Acceptance Filtering- Global Mask for incoming Messages (Full-CAN-Objects)Global Mask for incoming Messages (Full-CAN-Objects)- Additional Mask for Message Object 15Additional Mask for Message Object 15

(Basic-CAN-Feature)(Basic-CAN-Feature) Basic CAN Feature (Message Object 15)Basic CAN Feature (Message Object 15)

- Equipped with two Receive BuffersEquipped with two Receive Buffers- Own Global Mask Register for Acceptance FilteringOwn Global Mask Register for Acceptance Filtering

Connection to the Host CPU (C166-Core)Connection to the Host CPU (C166-Core)- Module access via chip-internal XBUSModule access via chip-internal XBUS

(16-bit demultiplexed mode)(16-bit demultiplexed mode)- Interrupt connection to the CPU; Flexible interrupt event Interrupt connection to the CPU; Flexible interrupt event

controlcontrol To connect the application to CAN only a CAN transceiver To connect the application to CAN only a CAN transceiver

is neededis needed


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Connecting the to CAN

19

CAN-BusTransceiver

Receive

Transmit

CAN_H

CAN_L

P4.5

P4.6

CAN_L

P2.0

Pa.b

Pc.d

C167CR/C161CI

CAN_H CAN_RxD

CAN_TxD

R(opt)

(Standby)

Vref

n.c.

Connectionto the

Application


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



I2C moduleC161RI only

20II22C moduleC module

7 and 10-bit addressing, 400KHz7 and 10-bit addressing, 400KHz 2 channels (multiplexed)2 channels (multiplexed) master modemaster mode slave modeslave mode multimaster modemultimaster mode

SDAx

SDA0

SCL0

SCLx

OutputControl

OutputControl

Genericdata lineGeneric

clock line

I²CI²C

ModuleModule

µCµC

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Real Time Clock(RTC) - C161RI / C164CI

Real Time ClockReal Time Clock

Counts Time TicksCounts Time Ticks Time Ticks are defined by external crystal frequency and Time Ticks are defined by external crystal frequency and

programmable prescaler (trim register)programmable prescaler (trim register) Cyclic time based Interrupt (see separate foil)Cyclic time based Interrupt (see separate foil)

- Cycle Time can be adjusted via Reload Register (trim Cycle Time can be adjusted via Reload Register (trim register)register)

- Interrupt Request on XPER3 Interrupt NodeInterrupt Request on XPER3 Interrupt Node Additional FunctionAdditional Function

- RTC register and programmable prescaler can be RTC register and programmable prescaler can be concatenated to build a 48-bit timer unitconcatenated to build a 48-bit timer unit

21

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



RTCBlock Diagram

Interrupt

32-bit Timer

RTC High RTC Low RTCClock Driver

T 148 bit

Prescaler

16-bit Timer

16 bit Reload Value

Trim Register

Crystal orexternal Oscillator

external Oscillator

Programmable Divider

Time between two InterruptsOscillator Frequency Minimal Time Maximal Time Possible Time Base RTC

1 s4 MHz 0.064 ms 4.1 s5 MHz 0.052 ms 3.35 s 1 s8 MHz 0.032 ms 2 s 1 s

10 MHz 0.026 ms 1.6 s 1 s12 MHz 0.022 ms 1.3 s 1 s16 MHz 0.016 ms 1 s 1 s20 MHz 0.013 ms 0.8 s 0.1 s24 MHz 0.011 ms 0.6 s 0.1 s

OscillatorXTAL

21Real Time ClockReal Time Clock

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



RTC Cyclic time based Interrupt

Combination of Active Mode and Idle ModeCombination of Active Mode and Idle Mode During Active Mode all not used peripherals are disabled (Flexible During Active Mode all not used peripherals are disabled (Flexible

Peripheral Management)Peripheral Management) Cyclic waking up from Idle Mode to Active Mode via Cyclic waking up from Idle Mode to Active Mode via

programmable RTC interruptprogrammable RTC interrupt Waking up on external events via interrupt (ASC, SSC, CAN, EXIN)Waking up on external events via interrupt (ASC, SSC, CAN, EXIN)

IDLE MODE

1 Cycle

Active Mode with flexiblePeripheral Management

Active Mode with flexiblePeripheral Management

21Real Time ClockReal Time Clock

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Watchdog Timer(WDT) at 16 MHz

16-Bit timer overflow results in:16-Bit timer overflow results in:- Software resetSoftware reset- Pulls RSTOUT Pin lowPulls RSTOUT Pin low- Sets identification bit and leaves WDT enabledSets identification bit and leaves WDT enabled

Programmable input clockProgrammable input clock High Byte reload registerHigh Byte reload register Timer period from 32µs to 588msTimer period from 32µs to 588ms Can be reloaded with a special instructionCan be reloaded with a special instruction

WatchdogWatchdog22

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167





Programmable input clockProgrammable input clock High Byte reload registerHigh Byte reload register Timer period from 25.6µs to 470msTimer period from 25.6µs to 470ms Can be reloaded with a special instructionCan be reloaded with a special instruction

WatchdogWatchdog22

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167





Programmable input clockProgrammable input clock High Byte reload registerHigh Byte reload register Timer period from 20.5µs to 376msTimer period from 20.5µs to 376ms Can be reloaded with a special instructionCan be reloaded with a special instruction

WatchdogWatchdog22

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



serviceWDT

8-bitreload zero

RSTOUT

SoftwareReset

16-bit Timer

high Byte low Byte

WDT control

CPU CLK / 2 onoverflow

WDTBlock Diagram

CPU CLK / 128

22WatchdogWatchdog

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



System Clock FeaturesPLL

On-chip PLL circuit implementedOn-chip PLL circuit implemented

Variety of different clock options available:Variety of different clock options available:System Clock can be selected to be 0.5, 1, 1.5, 2, 2.5, 3, 4 System Clock can be selected to be 0.5, 1, 1.5, 2, 2.5, 3, 4 and 5 times the externally applied frequency at the XTAL-and 5 times the externally applied frequency at the XTAL-pinspins

In case of external clock failure:In case of external clock failure:- PLL Unlocked Interrupt (XP3INT) is generatedPLL Unlocked Interrupt (XP3INT) is generated- PLL runs on its base frequency (5...10 MHz)PLL runs on its base frequency (5...10 MHz)

C164 and C163 can perform emergency operationC164 and C163 can perform emergency operation External clock is monitored even if clock options 'W' External clock is monitored even if clock options 'W'

(direct clock drive) or '0.5' (prescaler mode) are selected(direct clock drive) or '0.5' (prescaler mode) are selected

PLLPLL23

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Clock Options

0 = external pull- down

ffOSCOSCfCPU

ffOSCOSCfCPU

ffOSCOSCfCPU

ffOSCOSCfCPU

ffOSCOSCfCPU

ffOSCOSCfCPU

ffOSCOSCfCPU

ffOSCOSCfCPU

ffOSCOSC : f : f CPUCPU

default

prescalarmode

direct clockdrive

NoteNotePre-Pre-scalarscalar

OFF

OFF

OFF

OFF

OFF

ON

ON

ON

PLLPLLfactorfactor

4

2

3

5

OFF

OFF

3

5

ClockClockOptionOption

4

2

3

5

W

0.5

1.5

2.5

P0H5P0H5

1

1

0

0

1

1

0

0

P0H6P0H6

1

0

1

0

1

0

1

0

P0H7P0H7

1

1

1

1

0

0

0

0

23PLLPLL

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Power ManagementModular Version 2.0

PowerPower

ManagementManagement

Power ManagementPower Management24

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Modular DesignOverview

Power ManagementPower ManagementPower ManagementPower Management

PowerPowerSavingSavingModesModes

PowerPowerSavingSavingModesModes

FlexibleFlexibleClockClock

GenerationGenerationManagementManagement

FlexibleFlexibleClockClock

GenerationGenerationManagementManagement

FlexibleFlexiblePeripheralPeripheral


FlexibleFlexiblePeripheralPeripheral


RealRealTimeTimeClockClock

RealRealTimeTimeClockClock


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



IDLE ModeIDLE Mode- Disabling of CPU and internal memory modulesDisabling of CPU and internal memory modules- All peripherals can be enabledAll peripherals can be enabled- Enabling of CPU via interruptEnabling of CPU via interrupt

Power Down ModePower Down Mode- Disabling of complete controller functionalityDisabling of complete controller functionality- Optional running of real time clockOptional running of real time clock- Optional disabling of port output drivers (tristate)Optional disabling of port output drivers (tristate)

- Preservation of internal RAM content for VPreservation of internal RAM content for VCCCC voltage higher than 2.5 voltage higher than 2.5 VV

- Enabling of controller functionality via resetEnabling of controller functionality via reset

Power Saving Modes


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Basic Clock SourceBasic Clock Source- Selection between different sources via port 0 configurationSelection between different sources via port 0 configuration

- Direct drive (fDirect drive (fCPUCPU = f = fOSCOSC))

- Prescaler (fPrescaler (fCPUCPU = f = fOSC OSC / 2)/ 2)

- PLL (fPLL (fCPUCPU = f = f OSC OSC * PLLfactor)* PLLfactor)

- Selection can not be changed via softwareSelection can not be changed via software Slow Down Divider Clock SourceSlow Down Divider Clock Source

- Programmable oscillator clock divider (fProgrammable oscillator clock divider (fCPUCPU = f = fOSC OSC / SDD / SDD factor)factor)

- Dividing factor can be changed by softwareDividing factor can be changed by software- Optional lower frequency via second 32 kHz crystal Optional lower frequency via second 32 kHz crystal

(C161RI only)(C161RI only)

Flexible Clock Generation ManagementClock Sources


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Flexible Clock Generation ManagementOverview

XTAL3OSC2

fOSC2

XTAL1OSC1

fOSC1

32 kHz32 kHz

MUX

fCPU

PLLDirect Drive

SDD

2:1

MUX

MUX

MUX

Clock Detection

32:1

XTAL4

XTAL2

fOSC

C161RI only

RCDfRTC

Hardware Selection on Reset

Software

SoftwareSYSCON2.SOSC

SoftwareSYSCON2.RSC


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Flexible Clock Generation ManagementSlow Down Divider (SDD) - Features

Significant reduction of power consumptionSignificant reduction of power consumption Reduced CPU frequency by programmable clock dividerReduced CPU frequency by programmable clock divider

- 5-bit Reload Counter for programmable divider with factor 1-325-bit Reload Counter for programmable divider with factor 1-32

- ffCPUCPU = f = fOSC OSC / SDD factor (e.g. 16 MHz / 32 = 0.5 MHz)/ SDD factor (e.g. 16 MHz / 32 = 0.5 MHz) Notes:Notes:

- Output CLKOUT also shows the reduced frequencyOutput CLKOUT also shows the reduced frequency- No OWD available, if PLL is stopped during Slow Down Clock No OWD available, if PLL is stopped during Slow Down Clock

GenerationGeneration


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Flexible Clock Generation ManagementSlow Down Divider (SDD)

CLKREL

Reload CounterfOSC fSDDOUT

Reload

Slow Down Divider (SDD)

fOSC

fSDDOUT CLKREL=3

CLKREL=5

CLKREL=6

CLKREL=9


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Flexible Clock Generation ManagementOptimized Oscillator

Oscillator Start-up voltage Oscillator Start-up voltage 3 V power supply 3 V power supply Stable oscillation down to 2.7 VStable oscillation down to 2.7 V Minimum oscillator power consumption at Minimum oscillator power consumption at

3 V power supply (oscillator only)3 V power supply (oscillator only) Crystal frequency range:Crystal frequency range:

3.5 MHz 3.5 MHz f fcrystalcrystal 16 MHz 16 MHz

External oscillator input frequency range:External oscillator input frequency range:

1 MHz 1 MHz f foscillatoroscillator 40 MHz 40 MHz


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Flexible Clock Generation Management Register Definition

CLKRELCLKREL CLKCONCLKCON SYSRLSSYSRLSPDCONPDCONSOSCSOSC RSCRSCCLKCLK

LOCKLOCK

SYSCON2SYSCON2 Flexible Clock Generation ManagementFlexible Clock Generation Management

New Bit comparing to V1.1

Moved Bit comparing to V1.1


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Flexible Peripheral ManagementFeatures


Peripherals organized in groups with seperate clock Peripherals organized in groups with seperate clock driversdrivers- Interface Clock Driver (ICD): Interface Clock Driver (ICD): ASC0, SSC, WDT, ASC0, SSC, WDT,

Interrupt DetectionInterrupt Detection- Peripheral Clock Driver (PCD): Peripheral Clock Driver (PCD): all other Peripherals, all other Peripherals,

Interrupt Interrupt Controller, PortsController, Ports

- RTC Clock Driver (RCD): RTC Clock Driver (RCD): Real Time ClockReal Time Clock Disabling of PeripheralsDisabling of Peripherals

- PCD including all connected Peripherals can be disabledPCD including all connected Peripherals can be disabled- Each Peripheral can be disabled individuallyEach Peripheral can be disabled individually- All registers are visible for read and write access while a All registers are visible for read and write access while a

peripheral is disabled individuallyperipheral is disabled individually- Peripheral continues operation after re-enablingPeripheral continues operation after re-enabling

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Flexible Peripheral ManagementOverview: C161RI

CLK Int.Detection

CLKASC

EN

CLKSSC

EN

fCPU

Peripherals

CLKADC

EN

CLKGPT1

EN

CLKPorts

CLK InterruptController

CLK WDT

CLKI2C

EN

CLK

EN

PeripheralClock Driver

CLK InterfaceClock Driver

CLK

EN

CPUClock DriverIDLE

SW SW

SW

SW

SW

SW

SW

CLKCPU

CLKMEM

CLKGPT2

EN

New

Modified


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Flexible Peripheral ManagementOverview: C164CI

Peripherals

CLKADC

EN

CLKGPT1

EN

CLKPorts

CLK InterruptController

CLKCAN

EN

SW

SW

SW

SW

CLKCPU

CLKMEM

CLK CAPCOM2EN

SWCLK CAP

COM6EN

CLK Int.Detection

CLKASC

EN

CLKSSC

EN

fCPU

CLK WDT

CLK

EN

PeripheralClock Driver

CLK InterfaceClock Driver

CLK

EN

CPUClock DriverIDLE

SW

SW

SWNew

Modified


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Flexible Peripheral Management Register Definition

--CC6CC6DISDIS

CC2CC2DISDIS

CC1CC1DISDIS --

GPT2GPT2DISDIS

GPT1GPT1DISDIS

SSCSSCDISDIS

ASC0ASC0DISDIS

ADCADCDISDIS

PCDPCDDISDIS

I2CI2CDISDIS

SYSCON3SYSCON3 Flexible Peripheral ManagementFlexible Peripheral ManagementCAN1CAN1DISDIS

PWMPWMDISDIS

CAN2CAN2DISDIS

SSPSSPDISDIS




C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Counts Time TicksCounts Time Ticks Time Ticks are defined by Time Ticks are defined by

- external oscillator frequency divided by 32external oscillator frequency divided by 32- fixed prescaler (8:1)fixed prescaler (8:1)- programmable prescaler (trim register)programmable prescaler (trim register)

Cyclic time based interruptCyclic time based interrupt- Cycle time can be adjusted via reload register (trim register)Cycle time can be adjusted via reload register (trim register)- Interrupt request shared with PLL interruptInterrupt request shared with PLL interrupt

Additional FunctionAdditional Function- RTC register and programmable prescaler are RTC register and programmable prescaler are

concatenated to built a 48-bit timer unitconcatenated to built a 48-bit timer unit

Real Time Clock (RTC)Features


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Real Time Clock (RTC)

fRTC T14

Reload

T14REL

RTCL RTCH

Programmable Prescaler

Cyclic Interrupt

Time between two InterruptsOscillator Frequency Minimum Time Maximum Time Possible Time Base RTC

32 KHz 0.250 ms 16.3 s 0.1 s4 MHz 0.064 ms 4.1 s 1 s5 MHz 0.052 ms 3.35 s 1 s8 MHz 0.032 ms 2 s 1 s

10 MHz 0.026 ms 1.6 s 1 s12 MHz 0.022 ms 1.3 s 1 s16 MHz 0.016 ms 1 s 1 s20 MHz 0.013 ms 0.8 s 0.1 s

Crystal orexternal Oscillator

external Oscillator

8:1

Optional second32 KHz crystal


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Real Time ClockInterrupt Sharing

-- -- -- -- -- -- -- -- -- ---- --PLLPLLIEIE

PLLPLLIRIR

RTCRTCIEIE

RTCRTCIRIR

ISNCISNC Interrupt Sub Node ControlInterrupt Sub Node Control




C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Power Consumption

Active Mode

Idle Mode

Power Down Mode Ports: OFF RTC / OSC: OFF

Power Down Mode Ports: ON RTC / OSC: OFF

Power Down Mode Ports: OFF RTC / OSC: ON

Power Down Mode Ports: ON RTC / OSC: ON

Active Mode and disabled Peripherals

Idle Mode and disabled Peripherals

FlexiblePeripheralManagement

FlexiblePeripheralManagement

Active or Idle Mode

Active or Idle Mode

SLOW

DOWN

Power Consumption

Existing FeaturesNew Features

Power ConsumptionOverview


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



SYSCON2/3 Access ProcedureState Machine

Step SYSRLS Instruction- 0000b1 1001b BFLDL, OR, ORB, XOR, XORB2 0011b MOV, MOVB, MOVBS, MOVBZ3 0111b BSET, BMOV, BMOVN, BOR, BXOR4 Free access to SYSCON2 and SYSCON3- 0000b

Note:Note: This sequence can be executed in an ATOMIC sequence only!


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



SYSCON2/3 Access ProcedureProgramming Example

EXTR #1 ESFR accessBFLDL SYSCON2, #0Fh, #00h set SYSRLS to 0000b

EXTR #4 ESFR accessBFLDL SYSCON2, #0Fh, #09h set SYSRLS to 1001bMOV SYSCON2, #0003h set SYSRLS to 0011bBSET SYSCON2.2 set SYSRLS to 0111b

access to SYSCON2 / SYSCON3 enabled; e.g.:BFLDH SYSCON2, #03h, #02h set CLKCON to 10b

=>switch to SDD clock=>disable PLL (if implemented)


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Overview Port Structure

The Port lines provide the connection to the external worldThe Port lines provide the connection to the external world- 77 Port lines on the SAB 80C16677 Port lines on the SAB 80C166- 111 Port lines on the C167111 Port lines on the C167- 77 Port lines on the C165/C16377 Port lines on the C165/C163- 59 Port lines on the C16459 Port lines on the C164- 64 Port lines on the C161V/K/O64 Port lines on the C161V/K/O- 77 Port lines on the C161RI77 Port lines on the C161RI

All Port lines are individually addressable and all I/0 lines All Port lines are individually addressable and all I/0 lines are independently programmable for input or outputare independently programmable for input or output

Each Port line is dedicated to one or more peripheral Each Port line is dedicated to one or more peripheral functionsfunctions

Each Port is protected with fast diodesEach Port is protected with fast diodes Programmable open drain buffers Programmable open drain buffers

- P2, 3, 6, 7, 8 on the C167P2, 3, 6, 7, 8 on the C167- P3, 8 on the C164P3, 8 on the C164

PortsPorts25

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Overview Port Structure

25PortsPorts

DirectionRegister

VCC

Vss

OutputLatch

AlternateOutput

AlternateEnable

Read Direction

Write

ClockAlternate Input

Port Pin

Inte

rnal

Bu

s

Buffer

Mux

Mux

Buffer

InputLatch

ESD structure

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



DirectionRegister

OutputLatch

AlternateOutput

AlternateEnable

Read Direction

Write

ClockAlternate Input

Inte

rnal

Bu

sOverview Port Structure

Buffer

Mux

Mux

Buffer

InputLatch

Open DrainControl

25PortsPorts

VCC

Vss

Port Pin

ESD structure

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



WDTOSC.PEC

CPUROM /

RAM

PORTS

CAPCOM

ADCBus

Ext.

Processor -System

Interrupt-System

USART GPTs

Peripheral-System

Flash

Control

X-Bus

Sync Communication PWMPeriphrl.

SummarySummary

The Summary of the C166 Family

26

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



High Computational Power: min 80ns Instruction Cycle High Computational Power: min 80ns Instruction Cycle TimeTime- Fast algorithms (short sample times for closed loop control)Fast algorithms (short sample times for closed loop control)- Fast task executionFast task execution

Control Oriented Instruction SetControl Oriented Instruction Set- Boolean processing / bit-handling and processingBoolean processing / bit-handling and processing- Task switch / power savingTask switch / power saving

General Purpose Register Oriented ArchitectureGeneral Purpose Register Oriented Architecture- Managing of multiple quasi-parallel tasksManaging of multiple quasi-parallel tasks

Powerful Addressing CapabilitiesPowerful Addressing Capabilities- Large address range and powerful addressing modes (HLL)Large address range and powerful addressing modes (HLL)

On-chip RAM, OTP/ROM/FlashOn-chip RAM, OTP/ROM/Flash- For very fast Memory AccessFor very fast Memory Access- In-System reprogrammable Flash MemoryIn-System reprogrammable Flash Memory- one-time programmable ROMone-time programmable ROM

Processor System

26SummarySummary

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Extremely Short Interrupt Response TimeExtremely Short Interrupt Response Timeof typically min. 320nsof typically min. 320ns- Interrupt execution in small time segmentsInterrupt execution in small time segments- Ensures highest real-time performanceEnsures highest real-time performance

Comprehensive Prioritization SchemeComprehensive Prioritization Scheme- Easy scheduling of complex real-time systems by using up Easy scheduling of complex real-time systems by using up

to 64 Priority levels (4 groups within 16 levels)to 64 Priority levels (4 groups within 16 levels) CPU-Independent Interrupt Service via Peripheral Events CPU-Independent Interrupt Service via Peripheral Events

Controller (PEC)Controller (PEC)- Off-loads the CPU from simple but frequent interrupt-Off-loads the CPU from simple but frequent interrupt-

servicesservices- Interrupt-driven “DMA-like” data transfer, without task Interrupt-driven “DMA-like” data transfer, without task

switch of CPUswitch of CPU- Makes peripheral data transfers independent Makes peripheral data transfers independent

of running CPU routineof running CPU routine

Interrupt System

26SummarySummary

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Multi-functional Timer/Counter Units (up to 5 Timers / Multi-functional Timer/Counter Units (up to 5 Timers / Counters) with Complex Concatenation PossibleCounters) with Complex Concatenation Possible

Comprehensive up tp 32 Channel Capture/Compare Unit Comprehensive up tp 32 Channel Capture/Compare Unit with up to 4 Allocatable Time-Baseswith up to 4 Allocatable Time-Bases

Capture/Compare unit (CAPCOM6) Capture/Compare unit (CAPCOM6) for flexible PWM Signal Generationfor flexible PWM Signal Generation

4 high resolution PWM channels4 high resolution PWM channels up to 10-bit Multi-Functional A/D-Converter for Fast Data up to 10-bit Multi-Functional A/D-Converter for Fast Data

Acquisition in Control SystemsAcquisition in Control Systems

Peripheral System

26SummarySummary

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Bi-directional, Protected and Individually Programmable Bi-directional, Protected and Individually Programmable External Port-LinesExternal Port-Lines

Serial Communication InterfacesSerial Communication Interfaces- Standard asynchronous communicationStandard asynchronous communication- Fast synchronous communication in master- & slave-mode Fast synchronous communication in master- & slave-mode

(SPI)(SPI) Easy Adaptation to Special Application or Customer Easy Adaptation to Special Application or Customer

Requirements via Internal X-BUS ArchitectureRequirements via Internal X-BUS Architecture- CAN-Bus, Profibus, SSP, etc.CAN-Bus, Profibus, SSP, etc.

flexible Power Managementflexible Power Management

Peripheral System

26SummarySummary

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



2-chip Emulation Technology

One Bondout chip supports emulation of all related One Bondout chip supports emulation of all related derivatives, new or existing (i.e. C167, C165, C163, C161)derivatives, new or existing (i.e. C167, C165, C163, C161)

New X-Peripherals (XPERs) are emulated using the New X-Peripherals (XPERs) are emulated using the standard chipstandard chip

In emulation mode the standard IC is sleeping and only the In emulation mode the standard IC is sleeping and only the XPER is active. The Bondout chip has full access to the XPER is active. The Bondout chip has full access to the XPER over a particular portXPER over a particular port

No need for Bondout redesignNo need for Bondout redesign User has full emulation control over the XPER without any User has full emulation control over the XPER without any

intrusion of real-timeintrusion of real-time Full access to target system is maintainedFull access to target system is maintained Supported by all major tool manufacturersSupported by all major tool manufacturers

Development ToolsDevelopment Tools27

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



2-chip Emulation Technology

ROMRAM

Standard Peripherals & I/O

GPT CAPCOM ...

I/O

Port0 Port1 Port4

External Bus Interface

P6

CPUCORE

Bus Contr. PORT

PORT

RAMBUS BUS

P-Bus

X-Bus

to User Application

Sim.ROM

to User Application

Port0 Port1 Port4

External Bus Interface

P6

RAM

Standard Peripherals & I/O

GPT CAPCOM ...

I/O

CPUCORE

Bus Contr.

RAM

BUS

P-Bus

ROM /FLASH

X-Bus

XPER

XPERI/O

ROM

BUS

CS#

XPER-Interrupts

X-Bus

to UserApplication

Standardchip

Bondoutchip


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



...just as Siemens Microcontrollers are a constantfactor of success for the products they are designed into!

...just as Siemens Microcontrollers are a constantfactor of success for the products they are designed into!

Development Tools are a constant factor of success for Siemens Microcontrollers...

Development ToolsDirectory

Development ToolsDirectory


C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



Sockets / AdaptersYamaichi ET

EMULATION TECHNOLOGY, INC.

Development ToolsDevelopment Tools

KEILSoftware

Debuggers

pls

TASKING

Evaluation Boards

KEILSoftware

PHYTEC

RIGELHIGHTEC

ertecertecpls

KEILSoftware

Compilers, Assemblers

HIGHTEC

TASKING

Flash Programmers

ertecertecCEIBO

hitexpls

CAN/FUZZY

i+MEINFORMstzp

MicroFuzzy

RTOS

KEILSoftware CMX

Company

HIGHTECtecsi

WindRiver Systems

Emulators

hitex LAUTERBACH

YOKOGAWA

KONTRON ELEKTRONIK

Major Tool Partners

Tektronix

dli

Logic AnalyzersHEWLETTPACKARD

Simulators

KEILSoftware

hitex

TASKING

27

C161C161

C166C166

C163C163

C164C164

C165C165

C167C167



• Robotics

• PLC’s

• Servo-Drives

• Motor Control

• Power-Inverters

• Machine-Tool Control (CNC)

• Engine Management

• Transmission Control

• ABS/ASK

• Active Suspension

Automotive Industrial Control

• DVD / CD-ROM

• TV / Monitor

• VCR / Sat Receiver

• Set Top Box

• Games

• Video Surveillance

Telecom/ Datacom

• Communication Boards (LAN)

• Modems

• PBX

• Mobile Communication

EDP

• Hard Disk Drives

• Tape Drives

• Printers

• Scanners

• Digital Copiers

• FAX Machines

Consumer

Applications for the C166 Family

C166 Family C166 Family

WDTOSC. PEC

CPUROM /

RAM

PORTS

CAPCOM

ADCBusExt.

Processor -System

Interrupt-System

USART GPTs

Peripheral-System

Flash

Control

X-BusSync Communication PWMPeriphrl.

28

C161 C166 C163 C164 C165 C167 HL MC AT, lehmann 16x_all.ppt 30.08.2015, 08:46 - 1 Microcontrollers...

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Transcript of C161 C166 C163 C164 C165 C167 HL MC AT, lehmann 16x_all.ppt 30.08.2015, 08:46 - 1 Microcontrollers...