Business & Technical News from Unaxis Wafer Processing · chip @unaxis.com or fax back the r eply...

Business & Technical News from Unaxis Wafer Processing

June 2004 | Issue

LLS EVO II Re-design

Compatible High Performancewith Unaxis Products:

CLUSTERLINE®

VERSALINE™

VLSI 10 BEST Award 5th Year Running

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Unaxis Insights

Introducing Unaxis Wafer Processing 2

Exceeding Customer Expectations 3

Technical TrainingAn investment into the future 6

Feature

Thin Wafers – Big Performance 7

Advanced Packaging

APiA’s new Virtual Process LineTaking process integration a step further 10

Wafer Level CSP at National Semiconductor 12

Advanced Silicon

Re-launch of the CLUSTERLINE®

Towards zero handling defects 14

Unbeatable RAM: Reliability, Availability,MaintainabilityThe Unaxis CLUSTERLINE® at Philips Boeblingen 16

Power Semiconductors from InfineonBackside metallization by Unaxis 18

Photomask

The Unaxis MASK ETCHER® IV Keeps its Promises 20

Compound Semi&Microtechnology

The new LLS EVO IINew customer benefits 23

GaAs ManufacturingOptimization of low stress PECVD silicon nitride 28

High Performance Oxide Etchon the new VERSALINE™ platform 32

Pressure Control in DSE Processes 36

DSE: Notch Reduction for SOI 39

23

28Unaxis solutions forPECVD silicon nitrideare used extensively in the production ofGaAs devices.

LLS EVO II, the newbatch sputteringsystem from Unaxis:quicker assembly and installation,shorter service times,and easier handling.

14The newCLUSTERLINE®

series featuressignificantimprovements and innovations.

www.waferprocessing.unaxis.com

Unaxis InsightsFront Cover

Backside metallizationon a 300 mm wafer

Editor in ChiefJuerg Steinmann, Global Communications Manager Unaxis Wafer Processing

Executive EditorMarion Turner, U.S. Marketing Communications Manager Unaxis Wafer Processing

Managing EditorVeronika Schreyer, is design

Design /LayoutCactus AG

PhotographyMichael Reinhardand Unaxis, unless stated otherwise

Published byUnaxis Wafer Processing P.O. Box 1000FL-9496 Balzers Liechtenstein

Printed bySüdostschweiz Print AG

If you have any questions or comments, please contact us at [email protected] or fax back the reply card provided in this magazine.

Chip, the Business & Technical News from Unaxis Wafer Processing,is also available online at:www.waferprocessing.unaxis.com

Kenneth T. BarryPresident, Unaxis Wafer Processing

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Unaxis Chip

Welcome to Chip 10!In our continued quest to meet and anticipate customer expectations we are very pleased to report a positive balance half way through the year 2004. Again, for the fifth year running, we have been awarded a place among the 10 BESTsemiconductor equipment suppliers. Responsible for this success are all Unaxisemployees and partners, who share our commitment to business excellence.Another step on the quality ladder is the full compliance with ISO 9001 and ISO 14001 standards in both Wafer Processing technology centers St.Peterburg,Florida, and Truebbach, Switzerland (page 3).

On the product side we can now announce the re-design of our industry-provenCLUSTERLINE® with significant improvements and innovations. We consider this project an extremely important contribution to our customers' product andprocess requirements. On page 14 you find a first article on the details of the re-design. The continued success of the CLUSTERLINE® is demonstrated at ourcustomers' production sites though consistently out-performing our competitors by far. Performance data from Philips Boeblingen can be found in the article onpage 16. Also, the VERSALINE™, which was launched at Semicon West last year, has been developed further to provide our customers with a flexible, andmodular extention of production capacity. Process modules of VERSALINE™ andCLUSTERLINE® are now compatible. Read more about this highly advantgeousfeature in the articles about DSE processes on pages 36–39.

In our last edition of Chip we introduced the improved MASK ETCHER® IV. The system is living up to all expectations under market conditions and showsexcellent results on many different applications (page 20).

The batch sputtering system LLS EVO II is yet another new product from UnaxisWafer Processing that extends and improves existing functionality. Fully compatiblewith the well-known strengths of the LLS EVO, the new system provides quickerinstallation, shorter service times, and easier handling. Details about the LLS EVO IIcan be found on page 23.

I hope you will enjoy reading this edition of Chip, and that we can either answersome of your questions or leave you wanting to know more about Unaxis WaferProcessing and our products. Please contact us, we are looking forward to hearingfrom you.

Sincerely,

Kenneth T. Barry

2 | Chip Unaxis

Unaxis InsightsUnaxis InsightsUnaxis Insights

Capitalizing on synergiesUnaxis has held a majority interest in ESEC since the year 2000. The completeintegration of the two companiesstrengthens Unaxis’ position in chipassembly equipment and processingtechniques for the semiconductor industry.This portfolio reorganization will allow us to leverage our unified Unaxis/ESECbrand structure while maintaining eachbusiness’s specific identity and history.

Clearly, our intention is also to capitalizeon the synergies that exist between the three businesses, with commoncharacteristics in markets, technologies and operations.

We are currently in the process ofintegrating and aligning the Segment’smanagement and legal structure in thecountries where we operate, particularly in Asia. This process should be completedbefore the end of 2004.

At the same time, we are activelylooking at more operational synergies,where and when these make goodbusiness sense for Unaxis and for itscustomers. For instance, a commonapproach to supply chain (manufacturing,purchasing) and customer support

(e.g. spare parts management) will resultin enhanced efficiency and better service.Customers who are common to severaldivisions will benefit from a more comprehensive consideration of theirneeds and working practices.

Future plansThe “Unaxis Semiconductor Equipment”segment will continue to focus its effortson selected growth markets in thesemiconductor and displays industries. By combining its core capabilities in thefields of thin-film and chip-assemblytechnologies with its global footprint insales, service, and support, Unaxis is now best positioned to satisfy customerneeds to an even greater extent and to participate more extensively in futuremarket developments.

Each division’s strategy and operational goals remain unchanged. This reorganization will not affect or alter the working relationship with ourcustomers – assuring continuation of allcurrent customer contacts with Unaxis.

For more information please contact:[email protected]

In September 2003, Unaxis announced its intention to acquire full ownership ofthe ESEC Corporation.This decision wasconfirmed by the ESEC shareholders inOctober 2003. On March 12, 2004, thecourts in Switzerland granted Unaxis andESEC its final approval, and theintegrationof ESEC into Unaxis could proceedaccording to plan. With this acquisition,Unaxis and ESEC together achieve thenecessary size and scale to successfullycompete in the semiconductor capitalequipment industry. The company nowranks amongst the world’s ten leadingprocess solutions and global equipmentproviders.

Consequently, Unaxis introduced itsnew segment “Unaxis SemiconductorEquipment”, which combines itsSemiconductors Back End (ESEC),Semiconductors Front End and Displaysbusinesses; these divisions have beenrenamed as follows:J Unaxis Semiconductors Front End

becomes the “Wafer Processing”Division

J Unaxis Displays becomes the “DisplaysTechnology” Division

J ESEC (Semiconductors Back End)becomes Unaxis’ “Assembly &Packaging” Division The diagram illustrates our new organizational structure.

Introducing Unaxis’ New“Semiconductor Equipment”Segment

Fredéric van MullemVice President Human Resources

Unaxis Insights

New Unaxis organizational structure

SemiconductorEquipment

CoatingServices

VacuumSolutions

Components andSpecial Systems

DataStorage

Solutions

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Unaxis Chip | 3

Previous issues of “Chip” kept you up todate with quality standards development atUnaxis Wafer Processing. In 2004, we areproud to announce full compliance withISO 9001:2000 and ISO 14001 at both our manufacturing sites, St. Petersburg,USA, and Truebbach, Switzerland.

Ecological aspects and sustainabilityhave always played important roles inUnaxis’ production processes. UnaxisWafer Processing is a leader in the field of new production technologies whichreduce the consumable materials duringchip production, as well as in the finishedproduct itself. New technologies andmaterials like silicon-germanium enablethe production of faster and more energy-efficient chips.

Attaining the ISO 14001 certificationrepresents a significant milestone forUnaxis Wafer Processing to continue as a world class leader in thin film productionsolutions.

Another award underlining the payback of our continued dedication to quality: for the fifth time running, UnaxisWafer Processing has been awarded a place among the VLSI “10 BEST”semiconductor equipment suppliers.

From quality standards to businessexcellenceTo fully understand the direction that Unaxis Wafer Processing is taking in expanding its capability of fulfilling

customer expectations, it is essential to understand the process by which theDivision is managed. The strategy is thethree-year vision of where the Division isgoing and what actions it must take tofulfill customer expectations.

Unaxis Wafer Processing set out to fully integrate the Business ExcellenceStrategy (BEx) into the overall DivisionalStrategy. Senior managers representing all business aspects within the Division –Global Sales, Marketing andCommunications, Innovation andTechnology, the Strategic Business Units, Operations, Customer Support,Business Excellence and Finance –

Unaxis Insights

Exceeding Customer ExpectationsWith Business Excellence

Jim CoughlinDivision Business Excellence Manager

converge quarterly to discuss strategicdirection. Following a comprehensivereview, in which the managers questionand evaluate all areas of the division’sbusiness, the new Divisional Strategy isvalidated. It has become the roadmap for the Division’s direction; addressing BExgoals in a broad fashion, in a senseproviding a vision for everyone to follow.

To ensure continual viability, the strategy is under annual review based on changes in the marketplace andcustomer expectations.

4 | Chip Unaxis

Unaxis InsightsUnaxis Insights

Effective implementationThe annual Tactical Business Plan of theDivision contains individual commitmentsby members of the Global ManagementTeam; it establishes the specific tasksrequired to implement the goals defined in the strategy. Internal and externalbenchmarks are set, which enablesmeasurable process improvement and aperformance exceeding expectations.

The quarterly joint reviews ensure adynamic exchange of essential informationabout the collective progress in meetingtargets and challenges faced by allaspects of the organization. Goals aredisseminated to all Unaxis employees andbusiness partners. Effectively, everyoneparticipates in fulfilling the BEx objectivesas reflected in the Division’s Strategy andTactical Business Plans.

The first direct result of implementingthe new BEx Strategy is a markedimprovement of the Unaxis WaferProcessing complaint managementsystem. We have learned to better listento our customers and are now able to act efficiently and effectively worldwide.

Applied “BEx”The primary goal of our BEx Strategy is to ensure that each planning processconsiders health, safety, the environment,risk mitigation, product liability concerns,business process effectiveness, anddesign and product assurance. From an operational standpoint, some BExobjectives are already captured in manyareas of our daily working practice.

Health and Safety: The primary objectiveis to ensure a safe and healthy workingenvironment for all employees. This haslong been part of Unaxis policy and is alsosupported by all our business partners.

The Environment: The Division’s ISO 14001 certification demonstrates our commitment to sustainable andenvironment-friendly production coveringthe complete life-cycle of our product.

Risk Management: Risks managed by the Division on a daily basis include a wide array ranging from those posed bynature, man, the marketplace, currencymarkets, international laws, competitors,and customer expectations. Unaxis Wafer Processing reviews up to sixty-fivedifferent risks, prioritizes them, anddevelops specific action plans to controlor mitigate these risks.

Unaxis Insights

StrategicDirection

Customers

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“Business Excellence simply means living our vision andmission, translating them into real business and productionprocesses for everyday working life. Our Division’s BusinessExcellence Strategy is based on input from all globaloperations, from customers worldwide, from Unaxisemployees, and technology market analysts.” Ken Barry, Division President

Unaxis Chip | 5

Product Liability: All Unaxis products are designed and manufactured tooperate safely. New products are subjectto independent design verification andtesting by recognized third party testingagencies as well as to a combination ofnational and international safetystandards.

Our product liability control programalso informs our customers about the safe use of our products. Due to the large number of environmental health and safety regulations and laws that exist throughout the world, we advise our customers on how to fulfill theirresponsibility to comply with localrequirements and provide trainingwherever necessary.

Product Assurance: We make certainthat Unaxis products meet all specificationrequirements, that they are adequatelytested prior to delivery to the customer,and that each product performs reliably.All of these issues directly relate to ourcustomers’ cost-of-product ownership.

The test of any business excellenceprogram is the way it is put into practice,how it relates to operational realitythroughout the Division worldwide and to customer expectations. We areconfident Business Excellence isbecoming an integral part of our workinglives at Unaxis Wafer Processing resulting in better products, betterprocesses, and better customer relations; it is an investment into our future.


Unaxis creates outstanding benefits for its customers.

J Sustainable above-average growth andprofitability are key to strengthening themarket position of Unaxis and investing innew products and applications.

J Unaxis fosters a corporate culture thatencourages entrepreneurship, team spirit,and personal growth.

J Unaxis contributes to society and environmental improvement.

Unaxis Vision

Unaxis is a global leader in technologies,manufacturing solutions, components and services in selected growth markets.

J The activities of Unaxis span the segments:

Semiconductor EquipmentProduction systems for semiconductors and flat panel displays

Data Storage SolutionsProduction systems for data storage devices

Coating ServicesCoating of tools and components

Vacuum SolutionsVacuum technology

Components and Special SystemsOptical components and aerospacetechnology

J Unaxis creates integrated solutions byleveraging its core competencies in thin film,vacuum and precision technology.

J In long-term partnership with its customers,Unaxis develops unique solutions, providingthem with a competitive edge.

Unaxis Mission

6 | Chip Unaxis

Unaxis Wafer Processing has twoindependent training departments to fulfillthe training requirements of its internal and external customers. One is located in Trübbach, Switzerland; the other in St.Petersburg, Florida. Both offertechnical programs on products that aremanufactured at their respective locations.In addition, training is still provided onproducts which have been discontinued.

All training programs have beendeveloped around the Performance- Based Equipment Training model, or(PBET). The instructors in each locationhave been certified to develop trainingpackages in this format. Programsdeveloped prior to this standard havebeen redefined to meet the PBETobjective. They focus on the actual needs of the student, as it pertains to the performance requirements of theindividual when they are on the job. The training programs are offered atcustomer sites, as well as respectiveUnaxis training centers.

Programs are developed to meet the needs of the equipment operator,maintenance engineer, as well as Unaxiscustomer support engineers. In addition to our standard equipment programs, we also provide specialized programs for our customer support engineers. They include programs in RF, vacuumapplications, and software. All courses are individualized to meet specific needs of our many customers.

With respect to Unaxis’ internal trainingprogram, a semi-annual evaluation ofcustomer support engineer capabilities is performed and compared to present and future needs. Their competencies areidentified in a skills matrix, showingstrengths along with areas where additionaltraining is needed. The matrix also assistsmanagement in choosing the mostqualified person for the job. It helps mapareas to be developed for each engineer to achieve the next step in their career.

The training departments are alsoactively involved with new productdevelopment. Rather than wait forproducts to reach completion, we areactively developing our own trainingplatforms to address the needs of thecustomer support engineer. The engineerwho is responsible for the installation andmaintenance of new systems, is fullyprepared before the system is ready toship. Aside from classroom training thecustomer support engineer receives, theywork closely with manufacturing toacquire troubleshooting skills and realworld experience to prove themsuccessful in the field.

Alternate methods of training are alsobeing explored. Virtual Training online

is becoming a necessity in the age of“greater value for less cost.” We are alsoexploring the integration of manufacturingsoftware currently being used in thedesign of new products into trainingpackages. This software allows the user to view the assembly construction, withthe added capability of rotating theassembly and viewing it from manyangles. These training packages can be adapted to meet specific customerneeds, and we anticipate this reducingcustomer training cost. In developing new programs, we anticipate packagingthese so customers can utilize them in-house. As a self-paced trainingpackage, customers can train theirpersonnel at their own pace. At UnaxisWafer Processing we continually strive to improve our training methodology, anticipating future customer requirements.

Current available training classes can be viewed online at: http://waferprocessing.unaxis.com/en/welcom_413.asp.

For training enquiries please contact ourlocal sales and service office.www.waferprocessing.unaxis.com

Technical Training: A Proactive Investment

Unaxis Insights

David HartelCustomer Support Manager

Unaxis Insights

Unaxis Chip | 7

But this is exactly what power semiconductor manufacturers, such as Infineon and Philips Semiconductors, to name two, are proving. They are part of a growing number of analog semiconductor vendors that are exploitingan innovative thin wafer process, enabledby Unaxis’ CLUSTERLINE® system.

Manufacturers of 150 mm wafers are pushing wafer thicknesses below 100 µm, with 65 µm wafers indevelopment. Slightly thinner than a piece of paper, these wafers have ametalized coating on the backside. In bipolar transistors, electrical resistanceis a function of chip-thickness: thinner

chips offer less resistance and amaximizing of current throughput.

Market segmentsWhen thin wafer dies are used in discretes and semiconductors for powersupply and power management, terrificleaps in efficient power use are achieved.These devices are making their way intowhite goods, such as washing machines, refrigerators, as well as climate controls,pumps, and low-power industrial tooling.The chips are also found inside adaptersand chargers for mobile phones, PDAs,notebook PCs, and toys. An emergingmarket is in new third generation basestation equipment for RF power devices.

Even higher voltage and high-frequencyapplications, such as transformers forelectric welding equipment, uninterruptiblepower supplies, as well as switch modepower supplies and high-voltageconverters for microwave and medicalequipment, are target applications.

Thin wafer dies are highly conductive,switch faster, and can be packaged in such a way using insulators so they cool themselves. This means thattransformers are no longer required inpower modules.

Feature

Unaxis Chip | 7

Valerie Thomson Technical JournalistZurich

Feature

Thin Wafers – Big PerformanceIt is hard to believe that by simply making a silicon chip a few microns thinner, new, super-efficient components andsystems can be built. They have the potential to reduce fuelconsumption of cars by 50 percent, cut energy needs ofhousehold appliances by 30 percent, and slash the electricityused by telecommunications equipment, computers, and TVs in standby mode to zero.

1995 2000 2005 2010

J TV-setJ Analog phoneJ Radio/CRJ VCRJ PCJ Monitor

J TV-setJ Dect phoneJ Radio/CRJ VCRJ PCJ MonitorJ HandyJ Active speaker

J TV-setJ Dect phoneJ Radio/CRJ VCRJ PCJ MonitorJ HandyJ PDA

J Dect phoneJ VCRJ PC

J Notebook PCJ MonitorJ HandyJ PDA

J MP3 PlayerJ DSL adapterJ Active speakerJ DVD playerJ Set-top box

J MP3 playerJ DSL adapterJ Active speakerJ DVD playerJ Flat TV-setJ BeamerJ Home CinemaJ Set-top box

Power consumption with conventional power suppliesPower consumption with innovative switched power supplies

Figure 1: Thinnerwafers reduce powerconsumption ofconsumer electronicsSource: InfineonTechnologies CompanyPresentation 2004,CeBIT Hanover

Power consumption per household

J Packaging which allows for morefunctionality and power dissipation insmaller packages

J Sophisticated drive schemes to powerwhite LEDs

J Advances in trench processes have pushedthe contact resistance RDS(on) to new lows

J Need for high-voltage MOSFETS aimed atautomotive switching applications

J Boost in alternator output in the automotiveindustry from power conversion devices

J Start-up sequencing of multiple convertersto meet system requirements

J Programmable output switching regulators

J Tighter specifications for fuel gauging andbattery charging

J Lower quiescent currents

Source: VDC

Overview of features driving the need for power semiconductor innovation

8 | Chip Unaxis

Feature

8 | Chip Unaxis

A growing market Chip manufacturers who have adoptedthe thin wafer processes are seeingincreased demand, particularly in theautomotive and white goods sectors,according to Dr. Reinhard Benz, Product Marketing Manager PVD at Unaxis Wafer Processing. “Ourcustomers tell us that sales of powersemiconductors are outperforming theoverall semiconductor sector. The totalmarket for semiconductors is growing at CAGR (cumulative average growth rate) of 10 to 15 percent, while powerchips are experiencing 15 to 20 percentgrowth,” said Benz, adding that somecustomers are predicting even highergrowth rates.

Market research firms unfortunately do not track the impact of thin waferprocesses on the power semiconductormarket. Their reports on the powersemiconductor market lump standardchips with thin chips. Furthermore, market research firms tend to grouppower management chips with powersemiconductors.

With this in mind, the market forecastsare nevertheless impressive. Worldwideshipments of power supply and powermanagement integrated circuits were over 5 billion in 2003, and are expected to increase at an annual growth rate of8.8%, reaching close to 7 billion by 2006,according to Venture DevelopmentCorporation, a market research firm, in a report published in January 2003.

Analysts at Intex Marketing Services,supported by World SemiconductorsTrade Statistics and the SemiconductorIndustry Analyst, forecast 9% in 2004 and a growth rate of 12% for powersemiconductors next year.

Table 1: Thin wafersprovide the technologybase for emerging bipolartransistor IC applications.

Figure 2: Worldwide shipmentforecast for power supply andpower management integratedcircuits (published 12/12/03)Source: Venture DevelopmentCorporation (VDC)

Figure 3: Total available powersemiconductors marketworldwide Source: World SemiconductorsTrade Statistics (WSTS) 2003

Battery charging and management New battery chemistries affect the charge control andprotection requirements. In addition, there is a need forbetter fuel gauging and data collection on battery voltage,current, and temperature. These drive demand for bettercontrol ICs fabricated on thin wafers.

Telecommunications The emergence of 2.5 and 3 G mobile telephones andbase stations. These mobile standards require morepower management content – in the form of batterymanagement and charging ICs – as well as improved RFpower devices, enabled by ultra-thin wafer technology.

Automotive A modern mid-size car might contain up to 50 ICs. Thetrend to greater electronic content is pushing the movetoward 42V power systems, creating a new higher marginbusiness line for chip-makers, especially those using thinwafer processes.

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Unaxis Chip | 9

Feature

Market driversPower semiconductors convert and controlthe electrical current that powers virtuallyevery electronic device, from automotivesystems, consumer electronics, computermotherboard and peripherals, electronicoffice equipment, and industrial products to telecommunication and networkingequipment.

According to a recent article in SolidState Technology (Oct. 2003), the powersegment has performed better than other areas due to improvements in theresistance of the transistor in its on-state.This value needs to be as low as possibleto improve current carrying capability and to minimize power consumption.

A thinner wafer is one way to achievethis. For integrated circuit manufacturers,control of lower quiescent currents withtighter tolerances plus integration ofmultiple voltage output functions onto one chip are the drivers of the adoption of a new process in power semiconductormanufacturing.

Table 1 shows where thin wafers canhelp meet demands for emerging bipolartransistor IC applications.

Early adoptersSo who are the early adopters of thin wafer processing? Power semiconductorsuppliers who ship diodes, IGBTs(Insulated Gate Bipolar Transistors), and MOSFETs made from thin wafer dies, such as Fairchild Semiconductors,Infineon AG, International Rectifier Corp.,Agere (a spinoff of Lucent Corp), RoyalPhilips Semiconductors, Ixys, and ST Microelectronics.

These vendors do not say publiclywhether or not growth in sales is beingdriven by product features enabled by

thin wafer processes, partly because they do not want to let the competitors know, but also because the factors influencingmarket demand are complex.

According to Andreas Sperner of IxysCorporation, whose firm has graduallyintroduced this process over the last oneand a half years for a certain type of diodeproduct range, it is difficult for powersemiconductor suppliers to say whether or not recent growth has been spurred bythe use of thin wafer dies, because there is an overall upswing in the market.

“The last boom ended about two and a half years ago, followed by a marketrecession. For the past 8 or 9 months we

see a strong general market increase, but how much new thin wafer productscontribute to the increase is very difficultto say. However, I can say we are seeingcontinuous growth for this productrange,” commented Sperner.

Analog chip vendors might be keepingthe sales impact of thin wafers secret, but their adoption of the process in the fab speaks loudly in favour of it. Moreover,announcements of plans to try to produceeven thinner wafers suggest that thesemiconductor industry is convinced ofthe benefits in terms of cost savings andperformance boosts afforded by theprocess.

Valerie ThompsonMSc., has been a freelance business and high-tech writer for more than 10 years. A Canadian based in Zurich, she tracks the trends and developments of Europe’s purveyors of advancedtechnology.

J A year ago, Agere Systems announced a new line of RF power transistorsmade using a thin wafer process targeted at the mobile communicationsbase station market segment. The RF transistor is the key active buildingblock on power amplifier circuit boards. The transistor boosts signals ofvoice, data, and video in various frequency ranges before the signals aredelivered to wireless subscribers.

J Agere describes the new line as the “World’s Coolest Wireless PowerTransistors.” It also said that the chips could save “billions of dollarsannually for wireless service providers.”

J Its customers apparently agree because Agere has made progress inwinning new contracts. In January of this year, Agere announced it isdelivering the high-performance RF power transistors to NEC for use inthe company’s third-generation wireless base station equipment. “Thesedevices enable NEC’s base station amplifiers to remain cooler, therebysimplifying product design and improving its reliability,” said Agere in astatement.

J “The use of Agere transistors in our base stations will accelerate ourcompany’s 3 G wireless equipment deployment during the next fewyears,” said Dr. Nobuhiro Endo, general manager of NEC’s Mobile andWireless Division in the same release.

J According to Carlos Garcia, vice president and general manager withAgere Systems, “NEC’s selection of our products validates Agere’s abilityto produce and deliver high-performance RF transistors to an industryleader in deployment of operational 3 G base station equipment.”

J A second customer win was announced in the same month. Agere saidthat Sewon Teletech, Inc., the largest supplier of power amplifiers towireless and repeater original equipment manufacturers in Korea, wasalso adopting the RF devices.

Cool Base Stations

1. Texas Instruments 2. STMicroelectronics 3. Infineon 4. Analog Devices 5. National Semiconductor 6. Philips Semiconductors7. Freescale Semiconductor8. Toshiba9. Maxim

10. Fairchild / Intersil

Source: Databeans

Analog semiconductorsvendor ranking

Passivation layer& pad opening

Clean etch &redistribution metal

Metal patterning

Polyimide coating& pad opening

Clean etch &under-bump metal

Advanced Packaging

10 | Chip Unaxis

APiA’s new Virtual Process Line

Since the foundation of the APiA – Advanced Packaging and InterconnectAlliance – back in December 2001, both the consortium and the individualmember companies have increased the momentum towards comprehensiveand risk-free packaging solutions. By introducing the “Virtual Process Line,”the APiA is now moving forward with the worldwide commercially availableprocess integration.

Advanced Packaging Goals and benefits

Advances in the semiconductorpackaging industry require production-proven high-volume manufacturingsolutions within a certain framework ofstandardized processes. APiA’s answer to this is the “Virtual Process Line”featuring the following objectives: J Demonstrate individual toolsJ Demonstrate multiple technologiesJ Provide a commercial offering for each

processJ Provide a platform with flexibility for

integrated process developments andequipment evaluation aiming atmanufacturing solutions

J Appropriate IP protection of alltechnologies involved

The APiA “Virtual Process Line” offers theprocess sequence in a partly distributedsetup. Process steps with a stronginterdependence are clustered in singlelocations for process integration and quick response. This setup ensures themost recent tool and process features will be deployed.

In Figure 1 a simplified process flow is shown with the corresponding singlefab locations of the APiA members.

Process technology portfolioThe introduction of wafer-level packaging(WLP) has mainly been driven by form-

factor needs. During the last years, thisdevelopment spread along the dimensionof device type, from work station MPU, PCMPU, certain chip sets, graphics devicesto high end ASICs and DSP chips. Volumebeing the second dimension for growth, it is expected to develop very quickly. An estimated 10% of today’s 130 nmproducts uses WLP solutions, growing to a predicted rate of more than 80% atthe 90 nm node.

Wafer bumping for flip chip applicationsis a key technology in the field of WLP.

Two major bumping processes being usedin the “Virtual Process Line” are solderplating and solder printing. In both casesthe under-bump metallization (UBM) based on sputter deposition is anessential step in the process flow. Typical UBMs for plating are film stackssuch as Ti-Cu or TiW-Cu, while in case of printing Al-NiV-Cu or Ti-NiV-Cu areoften employed.

In addition to the traditional solderbump, the “Virtual Process Line” will alsocover lead-free bumping technology.

10 | Chip Unaxis

Dr. Christian LinderPVD Process Technology ManagerWolfgang RadloffMarketing Manager

Thick photoresist& pad opening

Unaxis Chip | 11

redistribution layer and solder bumpingprocess flow; for each step thecorresponding APiA member is also listed.

Above-chip passive components are used, for instance, in capacitorsconsisting of thick dielectric layers withtop and bottom metal electrode films. Cu layers patterned as planar (spiral)inductors are another example.

Thick Al or Cu films ranging up toseveral microns are gaining interest forreliable high current flow as for instanceneeded in on-chip power distribution.Such metal lanes can be fabricated either by a sputter seed followed by aplating step (e.g. for Cu) or in one sputterdeposition step (e.g. for Cu or Al with a thickness range of 3 – 5 µm).


Advanced PackagingTypical lead-free material combinations

are Sn/3.5 Ag or Sn/3.8 Ag/0.7 Cu.Regarding the UBM, it is possible to utilize well-established film stacks like Ti-NiV-Cu with minor adaptations such as increased film thickness for the NiV-Cu part.

A further focus of the “Virtual ProcessLine” is the post-passivation layer (PPL)technology comprising dielectric andmetal films and structures above thestandard IC process. Examples of such WLP applications include the

redistribution layer (RDL) technology, on-chip passives, or thick metal lanes.

RDL technology is used for re-routing of the bumps from the perimeter to otherlocations of the chip surface allowing a more relaxed pitch. The processinvolves a first passivating organic layer(e.g. polyimide (PI) or BCB) with openingsto the peripheral bond pads, followed by a metal deposition (e.g. sputtering of Ti-Al or Ti-Cu) and etch, and finallysecond passivation on top with openingsto the bump pads. Figure 2 shows a

Solder electroplating Thick photoresist removal& under-bump metal etching

Solder reflow

Bump inspection

Figure 2:Redistribution layerand solder bumpingprocess flow (cross sections not to scale)

UBM deposition

Photopolymer,coat /bake/develop,stepper photolithography

Solder plating

Solder screen-printing(Alternative option)

Stress buffer cure bake

PR strip & clean,UBM wet etch

Inspection after develop,solder deposit, bumpheight

De-scum

Solder re-flow

X-Ray inspection

Bump shear inspection

Die-bonding for flip-chip

D-Tek Technology Co., LTD

Figure 1: Equipmentlab locations of the“APiA Virtual ProcessLine” (sequencedepending uponprocess type). APiAexecutive membersare: August, Ebara,Steag Hamatech,Ultratech, and Unaxis.

Switzerland

CA, USA

Japan

Taiwan

MN, USA (Optional)

MN, USA

MN, USA

CA, USA

CT, USA

United Kingdom

Austria

NJ, USA

AlignerCooler

Degas

BufferInspectionPre-Heat

New CLUSTERLINE® handling system

Advanced Silicon

14 | Chip Unaxis

The CLUSTERLINE® 200 andCLUSTERLINE® 300 are high volumeproduction systems, one for wafer sizes of 150 to 200 mm, the other for 200 and300 mm wafers. They are the leadingproduction solution for wafer levelpackaging (WLP), thin wafer processing,RF MEMS (BAW), and Interconnectapplications.

Towards Zero Handling DefectsWith Unaxis CLUSTERLINE®

Unaxis launches a new generation of CLUSTERLINE® PVD systems.

Based on the successful CLUSTERLINE® 200 and 300 systems, the new seriesmaintains all the strengths of the current systems – proven and reliable processes,high throughput – while featuring significant improvements and innovations in theareas of wafer handling, accessibility, integration, and serviceability.

Advanced Silicon

14 | Chip Unaxis

Alex NefProduct Manager CLUSTERLINE®

Figure 1: Pre and postprocessing units arefreely configurable.

Our new generation now offers a number of benefits for our customers:J Higher uptime, lower scheduled

maintenance timeJ Increased reliability and extremely safe

wafer handlingJ Higher throughputJ Shorter delivery J Faster installation and ramp-up to

productionJ Easier serviceability

All above improvements result in lower cost of ownership (CoO).

The main new featuresNew transfer chamberJ Unaxis introduces the first

vacuumcluster system featuring in situauto-teaching and auto-calibration,about 10 times more accurate thanoperator teaching and about 100 timesfaster than all handling systems available today. The functions can becalled off the menu in a simple automatictask. Just imagine a system without ateaching panel, no teaching wafers, andnot having to open the sputter modulefor teaching at all. The system performsthese tasks automatically under vacuum conditions.

J On-the-fly realign: every wafer motion to or from any process module ischecked and the wafer is automaticallycentered on each chuck. Smart software

Unaxis Chip | 15

anticipates arising problems andprevents a transfer which could damagea wafer. Wafer breakage is dramaticallyreduced.

J The transfer chamber accepts sixprocess modules and additionally up to six pre- and post-processing units as plug-ins (Figure 1). Available plug-inunits are: buffer, aligner, cooler, pre-heat,degas, and inspection. Double configurations for increased throughputare possible. The transport module isprepared for new advanced features likeAPC (Advanced Process Control)inspection.

J Wafer size conversion is now an easy task – changing the cassette size and endeffector is simple, the autoteaching doesthe rest with just one click in the menu.

J On-the-fly wafer transfer verificationincreases the handling throughput.

New load lockJ Wafer mapping and automatic home

position detection: the wafer mappingdetects critical situations in the loadlocklike cross-slotted wafers, excessive waferbow, and double-loaded wafers.Mechanical tolerances are completelycompensated.

J Ergonomic load lock for 200 mmcassettes for easy and reliable loading of cassettes.

J Safe load lock door design, CE compliantwithout any interlocking.

New support systemJ Latest state-of-the-art components,

like CTI IS 8F, are used on the UnaxisCLUSTERLINE® systems. This ensuresbest availability and global support.

J The media distribution is designed intothe handler base, resulting in easy

installation, simple service, goodaccess, and easy system expansioncapability (Figure 2).

J Modular design leads to fewer individualparts, the smart modules use distributedI/O functions and a powerful Ethernetbus to simplify the system, increasinguptime and productivity.

J The functional and expandablearchitecture of the system results infaster delivery times and reduced rampup-time to production.

J Layout and installation distances aregreatly relaxed, and the footprint of thesystem is reduced.

J The system is designed to meet thenewest ISO 14001 environmentalstandards, conserving water usage and energy.

It is highly exciting to see the manyfeatures performing on our lab tool. These innovative functions provide a

safer level of wafer handling, protectingthe high value of our customers’ wafers.Customers will also benefit from higherproductivity, higher throughput, reducedmaintenance time and, increasinglyimportant, a faster and easier support of their installed systems. The newCLUSTERLINE® system is setting newstandards.

The combination of new featureseliminates some complex tasks liketeaching and calibration of robots. Thisand many other improvements make the CLUSTERLINE® systems easier andbetter to work with.

Good partnerships and close collaboration with our suppliers result inan extremely short time-to-market for thisproject – stay with us, there will be moregreat news in the next Chip magazine.


Advanced Silicon

Figure 2: The newCLUSTERLINE®

handling system,showing the interfaceto process modules.

Advanced Silicon

18 | Chip Unaxis

Villach may be just a small town in Austria, but it is home to the world leading competence center for power semiconductors, where thin waferprocessing is the key technology. Infineon established the facility in 1970,and together with their production facilitiesin Munich and Regensburg, Germany, itforms a manufacturing cluster, called the“PowerFab.” What makes Villach specialis the combination of production anddevelopment at one location.

The relationship between Unaxis andInfineon for backside metallization goesback quite some time. Over ten yearsago, the collaboration started whenInfineon began to use Balzersevaporators. Today, the processes onultra-thin wafers are transferred to several6” and 8” Unaxis CLUSTERLINEs, whichare the “work horses” for backsideproduction.

Power Semiconductors from InfineonBackside Metallization by Unaxis

The Unaxis CLUSTERLINE® 200 is the onlyindustry-proven high volume production tool forbackside metallization of ultra-thin wafers.

Advanced Silicon

Dr. Reinhard BenzProduct Marketing Manager PVD

Infineon Austria develops andproduces semiconductors forthe Automotive & Industrial (AI),Secure Mobile Solutions (SMS)and Wireline Communications(COM) business groups.Additional R&D facilities areprovided by the Infineonsubsidiaries DICE andCOMNEON.

Total surface area:158,000 m2

Workforce:2,600 (including 600 employed in R&D)

Sales/year:EUR 533 million (including DICE and COMNEON)

Production volume:10.4 billion chips/year

R&D expenditure:EUR 132 million

Facts and figures about Infineon Technologies Austria AG

Unaxis Chip | 19

The CLUSTERLINE® at Infineon’s“PowerFab”The product range at Infineon Villachcovers all types of discrete devices basedon IGBTs, MOSFETs, or bipolar transistorsfor products like drivers, converters,transceivers, or switches typically used for power management in power supply or automotive systems.

Especially the power semiconductortechnology out of Villach’s “PowerFab”is always one step ahead of the market,adding more features, performance, andfunctionality to devices while reducingmanufacturing costs, i.e. eliminating thecostly EPI layer to form the back metal electrode.

Regardless of whether the nextgeneration of power devices is driven by cost or technology for higherperformance, wafers will havethicknesses of around 100 µm and evenbelow. This is where Unaxis comes intothe picture and sets a clear milestone in the cost of ownership for waferbreakage, throughput, and processcapabilities. Backside metallization ofultra-thin wafers below 200 µm requires a dedicated handling system and

special attention to stress control of themetal stack on the backside.

The Unaxis CLUSTERLINE® is the onlyindustry-proven production tool withoutstanding throughput performance on 8” wafers of more than 600 wafers per day.The tools for wafer thickness below 100 µmrun with permanent high uptime of over90%. The special Cluster Tool integrationallows us to add necessary pre- and post-treatment steps like wafer cleaningand the annealing to the Si backside, which still results in typical throughputfigures of 35 – 40 wafers per hour.

Keeping aheadThe current collaboration with Infineon is focused on the implementation of nextgeneration thin wafers.

An extremely wide range of differentproducts requires full flexibility forbackside metals with or without carriersupport to help manage the production.

The CLUSTERLINE® covers the fullrange of wafer thickness from 700 micronto the latest thin wafer generation.

For more Information please contact:[email protected]

Advanced Silicon

“Infineon – as a major supplier to the highly demandingautomotive industry – knows the challenge thin waferspose between yield, throughput, and productionreliability. With the CLUSTERLINE® Unaxis offers areliable solution enabling us to stay on the leading edge of technology.”

Edgar Speidel, Director Module Management, Infineon

Ultra-thin wafer(thickness 25 µm) Technology andphotograph byFraunhofer IZM

Edgar SpeidelDirector Module Management, Infineon

Infineon is a leading innovator in the international semiconductor industry. We design, develop,manufacture, and market a broad range of semiconductors and complete system solutions targeted at selected industries. Our products serveapplications in the wireless and wireline communi-cations, automotive, industrial, computer, security,and chip card markets. Our product portfolioconsists of both memory and logic products andincludes digital, mixed-signal, and analogueintegrated circuits, or ICs as well as discretesemiconductor products and system solutions.

In Villach one of the main applications are Power and Automotive Products. In this business the needs of the customers are the driving power forproduct development. In a modern car the number of electronic components has been increasing ataccelerated speed, mainly for comfort and security.Air-condition, Global Positioning System (GPS),Airbags, Antilock Brake System (ABS), fuel injectionas well as infotainment systems have becomestandard or will be in a few years.

Therefore, the reliability, the speed, and the powerconsumption of each individual component are, alongside cost and time to market, crucial forsuccess. To stay at the leading edge co-operationswith strong partners are vital. One of the challengesis the trend to larger substrate diameters withreduced substrate thickness. Handling of thesewafers and processes with excellent stress controlare key to success.

Infineon Technologies Austria AG has a long historyof working together with first Balzers and now Unaxis for backside metallization. Unaxis has astrong technological background on metallizationequipment and materials.The CLUSTERLINE® is a production tool offering good solutions to theproduction challenges. Infineon and Unaxis togetherdevelop the tools to meet current and futurechallenges.

Advanced Silicon

16 | Chip Unaxis

The relationship between Unaxis andPhilips Semiconductors Boeblingen goesback many years. Since 1989, a firstgeneration CLUSTERLINE® has beenoperating at Philips and five old “Balzers”CLUSTERLINE® 9000 systems are still going strong. What better recommendation than a consistent,reliable and cost-effective performance for over 15 years!

Meanwhile, several competitor systemswere added to increase metallizationcapacity, and – since the year 2000 –

two new Unaxis CLUSTERLINE® 200 systems.

In 2002, Unaxis started a reliabilityimprovement program to exhaust the full potential of the tool, exploring the limitsof its performance capabilities. Philipssupported this project, since they werealso convinced their production costscould be lowered significantly with all theadvantages of the CLUSTERLINE® 200.

In a benchmark test comprised ofreliability performance, throughput, processresults, and maintenance costs, a clear and

measurable cost of ownership (CoO)advantage for the CLUSTERLINE® emerged:J System availability ranges consistently

between 90 and 95% (Figure 1).J Excellent average MTBFp (mean time

between failures of productive time) rate (Figure 2).

J 25 – 50% higher throughput over thecompetition and quicker productionramp-up after maintenance – resulting in more than 700 wafers/day (Figure 3).

J Maintenance consumable costs forelectrostatic clamping, as well as ionizedsputtering are 80% less than thecompetitor product.

J Process results are identical on all benchmarked systems in terms of film properties, defects, and device yieldcompared to the competition.

The great success of the UnaxisCLUSTERLINE® in Boeblingen has beenmade possible by the outstandingcooperation and close relationshipbetween all key players. Success wasinsured thanks to Marco Padrun as UnaxisTechnical Project Manager and WolfgangBreyer as Unaxis on-site Service Engineerand their extended and highly motivatedteam comprising process, engineering, and assembly. Also, special thanks to theUnaxis service crew in Munich.

We are confident these superb data,together with our impressive track record atPhilips Semiconductor Boeblingen, willopen new doors in the CMOS world.

Unbeatable RAM: Reliability –Availability – MaintainabilityThe CLUSTERLINE® 200 wins the day at Philips Semiconductors Boeblingen

The Unaxis CLUSTERLINE® 200 helps our customers cut costs with better reliability and throughput. Tests performed at Philips Semiconductorsin Boeblingen, Germany, showed that the Unaxis CLUSTERLINE® 200outperformed even the market leader’s product by far.

Advanced Silicon

Figure 1: The actualavailability of bothCLUSTERLINE® 200systems (CLC 1 andCLC 2) is permanentlybetween 90 and 95%.

Dr. Reinhard BenzProduct Marketing Manager PVD

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

May Jun Jul Aug Sep Oct Nov Dec Jan Feb Mar Apr

CLC 1

CLC 2

Plan

Maintenance availability Unaxis

Figure 2: ExcellentMTBFp rate for bothCLUSTERLINE® 200systems, showing a consistentperformance of 0–2 failures permonth.

0

50

100

150

200

250

300

May Jun Jul Aug Sep Oct Nov Dec Jan Feb Mar Apr

MTBFp Unaxis

Ho

urs CLC 1

CLC 2

Plan

Unaxis Chip | 17

InterviewDr. Uwe Zimmermann, Technical Team Leader CVD + PVD, Mico MIP, PhilipsSemiconductors GmbH, talks about the relationshipbetween Philips Böblingen and Unaxis.

Mr. Zimmermann, Unaxis and PhilipsSemiconductors Boeblingen haveworked together for many years. What do you particularly appreciateabout the cooperation with Unaxis?We appreciate the close partnership and personal connection which hasdeveloped over the years. Our colleaguesat Unaxis know our particular situationvery well and are therefore able to respond to any problems which may arise quickly and efficiently and meet our exact requirements.

Where do you see the main technicaladvantages of the CLUSTERLINE®

compared to other systems?It is a clear and simple piece of equipment,concentrating on the technical essentialswithout unnecessary frills. This means low repair times and, of course, very good uptime. The technical feature that particularly stands out is the Leap-FrogRobot on the handling system, whichspeeds up operation significantly and givesus continuously high throughput rates.

Advanced Silicon

Figure 3: Throughputcomparison representingtypical liner and metalinterconnect layers. Theaverage throughput of the CLUSTERLINE® 200 is 25% higher than that of the competition.Source: Philips

Throughput comparison CLUSTERLINE® 200 /competition

Application Process Competition CL200 Difference

e.g. Al metal X – 25 590 25 32 X 118 30,5 93 38,7 8,2 26,9

e.g. Ti-only X – 49 X 138 26,1 65 55,4 29,3 112,3

dega

s

softe

ch

Ti

AlC

u

Ti-h

ot

TiN

cool

er

sec/wafer wafer/hour sec/wafer wafer/hour wafer/hour %

How do these technical features helpyou reach your own targets?We can rely on the CLUSTERLINE® tomaintain high throughput rates at all times.The average wafer throughput per monthis nearly 25% higher than the tool of alarge competitor. This is essential to reachour production targets, which is also acontributing factor towards reaching ourfinancial goals – as are the reasonableprices for spare parts.

What feedback do you receive fromyour operators and maintenanceengineers regarding the handling of our system?Our staff love the CLUSTERLINE® for itsreliability during high throughput and itssimplicity. Maintenance engineers are very happy with the clean technicalsolutions, but also point out that in someareas the software could be improved.

Over the years, Unaxis and PhilipsBoeblingen have realized manyprojects together. Can you give us a glimpse of future developments and possible co-operations?Together with Unaxis, we will install a betaI-PVD module on the CLUSTERLINE®

here in Boeblingen in 2004. We arelooking forward to this project and theeasy cooperation of a tried and testedpartnership.

And beyond I-PVD?A project on backside metallization is in the planning stages, however, nodecisions have been made yet.

Philips Semiconductors GmbH Boeblingen

Originally IBM’s first semiconductor fab inGermany (1968), Philips SemiconductorsGmbH Boeblingen has an impressive portfolioof semiconductor know-how.

In 1988, the location is the first European 200 mm wafer fab, producing 4 MB memorychips. In 1995, IBM enters a joint venture withPhilips (51% Philips / 49% IBM). 1998 saw the last production of memory chips (16 MB),and a year later Boeblingen became a 100%daughter of Royal Philips Electronics, when the portfolio was changed from memory tologic products. In 2002, the Hamburg andBoeblingen locations were joined in PhilipsSemiconductors GmbH Deutschland.

Semiconductors production:CMOS IC production on 200 mm productionsystems: J Standard CMOS processes with structural

widths of 0.8 – 0.3 µmJ Medium voltage/high voltage CMOS

processes for LC/TFT displaysJ LCOS (Liquid Crystal on Silicon)J Embedded DRAM technology

Capacity: 300 million ICs per year

Photomasks

20 | Chip Unaxis

Cr etch results updateIn Chip 9, we presented unmatched etchresults of 32nm bias and non-uniformity of 12 nm, 3σ on the very demanding one window Ybor test masks. The Ybormasks were designed to be extremelychallenging. There is nothing quite like it in the industry. Unaxis knew this, butwanted to make sure it could deal with the worst-case scenario, and indeed it

worked. When it was time to revert back to the customers’ real mask, all our hardwork paid off. Unaxis again demonstratedgreat results! This was achieved on manydifferent applications such as masks for memory, chip manufacturers,merchants, and foundries. The UnaxisMASK ETCHER® IV has shown thefollowing results: for memory, an etch bias of 7nm with non-uniformity of 4.4 nm;

for gate level chip manufacturer maskproducts, the etch bias is 13 nm with auniformity of 3 nm (Figure 1). These resultshave been demonstrated on customer-supplied parts and are representative ofthe Unaxis MASK ETCHER® IV typicalloads for these customers. Meanwhile,other etch parameters have been keptconstant or improved.

Specification in questionUnaxis often hears machine specificationsare too loose to compare to resultsactually achieved on productionphotomasks. Why does Unaxis not sell the MASK ETCHER® IV with such lowspecification numbers? Surely, this canonly help the sale process? The threemajor reasons for this will be discussed in the following paragraphs.

Customers send very challenging partswhich may not be representative of theirproduction for demonstrations of Unaxis’equipment performance. By overstressinga problem, they can be assured theirproduction will run smoothly. Othercustomers, specifically merchants, have a variety of masks to produce which do nothave typical plates for them. The diversity of products for merchant customers is so great, some of them have the need tocreate their own internal standards.

The Unaxis MASK ETCHER® IVKeeps its Promises

Some of you may remember reading in our previous issue, Chip 9 (Sept ’03), an article entitled “65 nm Dry Etch: the Future of Photomask Has Arrived.” It introduced notions which are particular to photomask applications. This articlepresented progress made by Unaxis Wafer Processing for photomask Cr etchingfrom 1995 to date. Improvements from one generation to the next were mostimpressive. The progress achieved for each single node has allowed Unaxis totake and keep the well-deserved number one position in the photomask market.

Photomasks

Emmanuel RausaTechnical Marketing Manager

Gate leveletch contributioniso clear feature

deviation from average

Average: 12.563 Sigma: 3.04Max: 14.60Min: 8.60Range: 6.00

15.00

30.00

7.50

–15.00

–30.00

Figure 1: TypicalMASK ETCHER® IVetch signature for Cr layer on a gatelevel photomask

Unaxis Chip | 21

The second reason for Unaxis not to exaggerate performance is because measured results are not just etch contributions. Built into these results aremany variables, errors and noise whichcannot be easily separated from themanufacturing process itself. Forexample, the noise of the CD SEM (Critical Dimension SEM) metrology tool is embedded in these results. Anotherissue unaccounted for is the resist profiledistribution across the plate. If the resist is more sloped at the center of the platethan it is at the edge, this will affect thefinal Cr results and could be interpreted by customers as a contribution from theMASK ETCHER®.

Last, but not least, having a Unaxisstandard yet challenging plate helps us build an extensive database on etch

contribution, due to process or hardwarecontributions. In turn, this is used to our customers’ benefit because we canmatch every tool before shipping. Thishelps us identify possible hardware issuesbefore tool acceptance, and minimizescustomer cost in process integrationwhen placing repeat orders.

Current limitations of binary masksDimensions on the photomask surface arefour times those of the wafer dimensionsto be printed. This magnification helpsease manufacturing constraints. Thecurrent technology is still using themagnification, however the use of OPC(Optical Proximity Correction) is nownecessary due to light diffraction in featuresizes smaller than stepper wavelengths.OPCs are nothing more than known

diffraction features. They are carefullydesigned and placed to restore the imageof the main features which the chipdesigner intended to have on the wafer.

The introduction of these OPCs is thereason behind an acceleration inphotomask roadmap requirements and,eventually, in the price of the mask set.But OPCs are not enough anymore. There is need for a more sharply definedimage at the wafer level. In other words,improved contrast is needed at the featureedge. This can only be achieved byplaying on the phase of the light. PhaseShift Masks or PSMs do just that. Figure 2demonstrates the schematic of the phase change on the photomasks. Thereare several types of PSMs which can beattenuated or alternated, requiring etchingof a Cr layer first.

Photomasks

Figure 2: Light phaseshift through binary Cr mask andalternated aperturephase shift mask.

+

–

Reticle

Phase(Energy)

Intensity(Energy2)

Wafer

Quartz (clear)

Chrome (opaque)

Resist threshold

Remaining resistafter develop

Reticle

Phase(Energy)

Intensity(Energy2)

Wafer

Quartz

Chrome

Resist threshold

Remaining resistafter develop

Etched quartz(180° out of phase)

Source: ASML

22 | Chip Unaxis

Photomasks

Quartz etch in the industryAlternated PSMs combined withimmersion lithography have the potentialto extend current photomask technologyusage down to less than 30 nm at thewafer resist level. However, due tomanufacturing and inspection issues and therefore yield and costs, the industry has been using PSMs with greatreluctance so far. Despite these issues,quartz etch is the only current solution to the technical challenges.

Specific challenges in etching quartzQuartz etching has challenges of its ownwhich are not encountered with Cr orMoSi layers. For quartz, one etchesdirectly in the mask substrate. Featuresizes on each mask surface must becontrolled, along with the etch depth ofthe quartz features. This adds a thirddimension to etch control. Challengessuch as etch depth linearity and uniformity must be addressed. Both are important to control the phase of light passing through the mask duringwafer exposure in the stepper. In order to get the same phase change at themask, the etch depth into the quartzsubstrate needs to be independent of two parameters.

Etching depth uniformity and linearityFirst, the depth of quartz needs to be the same regardless of the location on the plate. This is commonly referred to as uniformity. Second, the depth of thetrenches in the quartz must also be thesame, regardless of their dimension or theshape of the feature. This is called etchdepth linearity and is a critical parameter,conversely a lack of depth linearity is called“RIE lag” and is undesirable. It is partic-ularly difficult to get a process whichdelivers depth linearity in the semicon-ductor industry. In everyday words, it is easy to understand: one wants to etchto the same depth in the same time,regardless of the volume of material toremove. Of course, the quality of the trench

needs to be constant. There should bestraight sidewalls with no micro-trenchingsurface roughness. Please see Figure 3for unwanted features on quartz etch.

Etch results on the MASK ETCHER® IVUnaxis’ MASK ETCHER® IV has proven to be an excellent tool to solve thesechallenges and has demonstrated linearityresults below its internal metrologycapabilities. Unaxis process engineershave been using an Atomic ForceMicroscope (AFM) and have measured theetch depth linearity to be within the noise of the AFM instument itself. As shown inFigure 4, the etched features are very cleanand straight. Roughness is below 1 nmRMS, and there is no visiblemicrotrenching.

What next?The Unaxis MASK ETCHER® IV wasdeveloped for photomask etching with the latest technology needed to improvethe process window. Ongoing processwork continues to provide our customers with the latest process improvements for their production needs.


Quartz bump

Surfaceroughness

Sloped side wall

Micro-trenching

RIE lag

Figure 3: Quartz etchimperfections

Figure 4: SEM crosssections showing theprofile of quartz etch on MASK ETCHER® IV. To the left, with Cr intacton top of quartz, a onemicron feature. To theright, quartz only, afeature size of 350 nm.

Unaxis Chip | 23


Compound Semi & Microtechnology

The load lock sputter success The first LLS was built in 1979. Since then, over 240 LLS systems have beensuccessfully installed, more than 100 of them are LLS EVO. Twenty-five years of process reliability in R&D andproduction from this Unaxis product –some of our customers are still orderingretrofits for first generation LLS 800systems! With its high flexibility regardingtarget materials and substrate size, with its excellent film uniformity andreproducibility, co-sputtering, its simpleoperation and easy maintenance, the LLSencountered steadily increasing demandin the market. Many new applicationscould be won thanks to professionalsample work with fast turn-around. Fromlaboratory to production with cassette-

to-cassette auto handling, the LLS coversan extremely wide range of applications atcustomer sites around the world.

Continuous product evolutionOver the past five years, a lot ofinformation has been collected from ourcustomers, but also from our applicationand service engineers, regarding potentialimprovements to the existing LLS EVO.The resulting wealth of experience andideas, plus the requirement to optimize the LLS EVO II (Figure 1) for supply chainaspects were the key drivers for this re-design. Proven modules like thevacuum chamber, the sputter sources,degas, RF etch and ion milling have notbeen touched to maintain processcompatibility with the LLS EVO.

More Customer Benefitsfrom the new LLS EVO IIBatch sputtering system for advanced packaging and compound semiconductor

Hubert BreussProduct Manager Batch Sputtering Systems

Figure 1: LLS EVO II

24 | Chip Unaxis

What is new on the LLS EVO II – whathas changed?

Media supplyWater (Figure 2): Service and maintenanceof the water battery have been simplified.The completely reworked water battery isone of the three main modules. Start-uptime at customer site has been reduceddue to the fact that all interfaces betweenrack cabinet, water battery and vacuumchamber are now equipped with fast plugconnectors. Pneumatic valves and theflow-meter are controlled via “Profibus”,screw couplings are realized in stainless steel. Steering and powercables are separated in defined positionsand the decentralized periphery results in less cables.

Water input and output pressure arecontrolled with a manometer and all waterpipes are equipped with plug connectors.Each cathode has a separate water supply

with flow-meter indicating actual values,the water pipe diameter has changed from 3/4” to 1.5”. “Blow out” of the watersupply (pipes and cathodes) during target exchange is now standard, and the operation is very user-friendly.

Gas (Figure 3): By changing the analogcontrol system to the digital “Profibus”interferences of the Mass Flow Controllers(MFC) could be eliminated. The newdigitally controlled MFC allowed areduction in the large variety of MFCs totwo sizes (50 sccm, 200 sccm), calibratedfor all process gases (Ar, N2, O2 and H2)used in the LLS EVO II.

Front panelThe front panel width could be reduced by more than 15% from 2.5 m to 2.1 m(Figure 4). User functionality has beenoptimized and simplified with a newkeyboard including trackball and anintegrated flat panel display. The function“DOOR UP” has been implemented and is controlled via the Graphic UserInterface (GUI) software, “CAGEROTATION” is integrated in the left “DOOR DOWN” button.

Rack cabinetThe new optimized rack cabinet alsocontributes to a reduction in floor space


Figuer 2: Completely re-worked water battery

Figure 3: “Profibus”-controlled gas battery

Figure 4: LLS EVO IIwith reduced frontpanel width

Unaxis Chip | 25


Figure 6: New graphic user interface

of over 10%. The rack modules (powersupplies, RF generator, PCs) are nowlocated to the left of the control rack. The power rack, which also includes the space for the control and power units of the optional auto handler, is locatedimmediately to the right. Both doors of the power rack can be opened from thefront, so the only space required behindthe control and power racks is for themedia supply (Figure 5b). The newarrangement of the rack cabinet is shownin Figure 5a. Also new and very handy isthe flat panel display integrated into the

front panel of the control rack togetherwith a stow-away keyboard.

Graphic user interface The GUI (Figure 6) has been completelyre-designed and is now state-of-the-artwith a Windows XP operating system,making recipe view and run protocol muchmore user-friendly. A SECS/GEM interfaceis available as an option.

Figure 5a: Rack cabinetwith integrated flat paneldisplay

Figure 5b: Mediasupply of the LLSEVO II

� Highest process flexibility – each of the fivesources can be configured for any of thefollowing options:DC Sputtering: conductive materials and low doped reactive processesRF Sputtering: dielectric materials and high doped reactive processesRF/DC combined sputtering: increasedrate for reactive sputteringPulsed DC sputtering: improvedperformance of low and high reactiveprocesses also stress control for pure metals (e.g. Cr, NiV)Co-sputtering: increased rates or individual mixtures of alloys (up to threecathodes)

� Load lock chamber for degassing; RF or ion beam etching assures clean surfacesand good adhesion.

� A unique valve separates the load lock and main chamber to avoid particles andgaseous contamination, maintainingrepeatable process conditions.

� Moveable shutter between the sourceseliminates cross-contamination and allowspre-sputtering (shutter closed) as well as co-sputtering.

� Vertical sputtering generates fewer particles.

� Optimized rectangular cathode design forhighest field homogeneity results in bettermagnetic fields.

� Easily convertible for different substrate sizes and shapes (small pieces up tostandard 8” substrates, max. 200 x 200 mm,frontside, backside loading).

� Different substrate sizes in same batch arepossible.

� High vacuum pumping systems are tailoredto specific process requirements.

� Fully automatic cassette-to-cassettehandling (Figure 9) avoids potential contamination through the operator (option).

� Operator-friendly Windows XP-basedcontrol system displays status and trends,tracks and registers process information,manages alarms and recipe handling.

� Segment sputtering possible

� Passive cooling enables processes <100°C.

� SEGS/GEM interface (optional)

� Corresponds with ISO14001

Features of the LLS EVO II

26 | Chip Unaxis

used for Soft PLC and GUI (Figure 7).

Both rack module computers are located

at the top of the control rack.

Segment sputtering In addition to dynamic sputtering,segment sputtering is now possible aswell. The new rotary drive enablessputtering of a specific segment, which isparticularly useful for laboratory use whensputtering expensive target materials.

Service hoist The new service hoist significantlysimplifies service and maintenance. It is now integrated into the LLS EVO II as a standard feature. In addition to thesubstrate cage and the rotation engine the new design now also allows removingthe LC pump and the LC high vacuumvalve.

Media consumption display Power, water, Ar, N2, O2, H2 vent nitrogen, and compressed air consumptionare now recorded and available as current, monthly, and annual printoutscorresponding to ISO 14001.

Miscellaneous The three main modules – water battery(Figure 8), rack cabinet, and processchamber on the platform with fixed front panel – result in reduced installationtime at the customer and contribute to simplified logistic processes.

Integrated and improved documentation:DocuCat is an add-on module for SPCat, which links all fields of servicedocumentation (operating instructions,OEM instructions, and spare parts catalog) into one database and integratesthem in a uniform control interface.

Total reduced floor area: Due to thereduction in width and the new optimizedrack cabinet, a total footprint reduction ofabout 20% has been realized.

Improvements at protection shielding:The modified anode frame protects theanode flange from being coated. Theinside of the load chamber (LC) is now fully shielded. The shutter box in the mainchamber (MC) has been modified to granta better gas flow distribution and pumpcharacteristic enabling better film unifor-mities, especially in reactive sputtering.Regardless of the position of the variouscathodes, they perform more uniformlywhen compared against each other –another advantage of the LLS EVO II.


26 | Chip Unaxis

Equipment data

Substrate size Up to 200 mm, square max 200 mm x 200 mm, < 15 mm thick

Batch capacity Front side loaded (round substrates)

75 mm 48 substrates

100 mm 36 substrates



200 mm 9 substrates

Backside loaded (round substrates)

50 x 50 mm 112 substrates (square)

75 mm 36 substrates




200mm 8 substrates

Deposition ratedynamic

Au 200 Å /min (1 kW), WTi 180 Å /min (3 kW), TaN 90 Å /min (1.5 kW), Al > 700 Å /min (10 kW), Cu > 1000 Å /min (10 kW), Ti > 300 Å /min (8 kW), Ni 240 Å /min (3 kW)

Magnet source AKQ515 with 127 x 381 mm target

Heater Degas LC – max 2 kW, power controlledProcess MC – max 4 kW, power controlled, up to 350°C

Etching RF etch >18 Å /kW minIon beam etch > 23 Å /kW min

Vacuum Base press. LC < 5 x 10 E-7 mbar (CTI 8F onboard)Base press. MC < 1 x 10 E-7 mbar (CTI 8F onboard)

Substrate handling Manual or optional automatic cassette-to-cassette

Electrical data 3 x 400/230 V AC, 50/60 Hz, 30 kVA

Water Cooling 18–25°C 60l /min

Compressed air 6– 8 bar (87–116 psi)

Process gas Ar, N2, O2, H2

Figure 7: Optimizedcontrol rack

Figure 8: Supplychain module waterbattery (on wheels)

Control unit

The reduction and optimization of rack

space were the main reasons to change

the control unit. The old Programmable

Logic Control (PLC) Simatic S7 has been

replaced by the latest Soft PLC version,

which is now running on a PC rack

module. Two independent computers are

Unaxis Chip | 27


Figure 9: LLS EVO II with cassette-to-cassetteauto handling

Benefits at a glance� Reduced footprint (–20%)� Lead-time reduced to three months

(with clarified system configuration)� New “Profibus”-compatible components

(Turbo Molecular Pump 1600, MFCs, Dual DC pulsed generator, decentralizedperiphery) replace all discontinuedcomponents.

� New water battery� Segment sputtering� LC door (open) software-controlled� Flat panel display in clean room and

grey room� New Graphic User Interface (GUI)� User-friendly process protocol and

recipe view� Soft PLC controlling unit� Simplified support� New optimized service hoist (standard)� Improved protection shielding� Supply chain modules

(simplified logistic)� New gas battery� Media consumption reporting

(ISO 14001)� Printer as standard� SECS/GEM Interface (option)

All these benefits add up to quickerassembly and installation, shorter servicetimes, and easier handling – contributingto an increase in productivity and reducedcost of ownership (CoO). The well-knownstrengths of the LLS EVO have not beencompromised in the re-design, making the Unaxis LLS EVO II a champion already.


28 | Chip Unaxis

It is well recognized that the stress of the SiNx layer in GaAs-based devicestructures can impact the electricalperformance and lead to degradation. For GaAs MESFET and HEMT devices, it has been demonstrated not only the magnitude of the stress but also the stress state, compressive or tensile, can affect the performance [1]. Stress-induced failure via microvoid formation inSiNx MIM capacitors has also beenreported [2]. Therefore, the capability oftailoring the magnitude and state of theSiNx stress required for a specific devicestructure is very important.

For SiNx, a common technique tocontrol the stress in a conventional 13.56 MHz parallel plate PECVD reactor is through the addition of low frequencypower. At 13.56 MHz, SiNx films preparedfrom standard gas mixtures of SiH4, NH3,

and N2 are typically tensile in nature. Theadded low frequency (< 1 MHz)component results in high energy ionbombardment of the growing SiNx film.This results in a change of the stress statefrom tensile to compressive [3, 4]. AtUnaxis, a He dilution method has beendeveloped as a simpler alternativetechnique to control the stress of PECVDSiNx. As illustrated in Figure 1, the additionof He to the standard gas mixture of SiH4,NH3, and N2, enables stress control fromabout 300 MPa, tensile through zero toabout –300 MPa, compressive.

Plasma-induced damage during theSiNx deposition process, resulting inphysical and electronic degradation ofGaAs devices is a very important issue [5–7]. Without the requirement of a lowfrequency power source, the possibility of damage is reduced with the He dilution

method. The RF power density at 13.56 MHz is very low and typically less than 50 mW/cm2.

A designed experiment (DOE) wasimplemented to characterize and optimizea low stress SiNx process based on the He dilution method on a UnaxisPECVD production platform developed for high volume GaAs manufacturing. To understand the mechanism involved inthis technique for stress control, opticalspectroscopic analysis of different He/N2

plasmas in the PECVD reactor has beenperformed.

ExperimentalAll the SiNx films were prepared on 100 mm Si test wafers from gas mixturesof SiH4, NH3, N2, and He on a UnaxisVERSALOCK® PECVD system [8]. Thisfully automated cassette-to-cassette

Optimization of Low StressPECVD Silicon Nitridefor GaAs Manufacturing

Unaxis solutions for plasma-enhanced chemical vapor deposition (PECVD) siliconnitride (SiNx) are used extensively in the production of GaAs devices. PECVD iscompatible with the low temperature constraints required for GaAs device manufac-turing. With this technique, high quality SiNx can be deposited at temperatures lessthan 400°C. PECVD SiNx is used in many different GaAs-based devices such asMESFETs, HBTs, and HEMTs. In these devices, PECVD SiNx is typically used forpassivation, encapsulation, and as a capping layer. In addition, the large dielectricconstant of SiNx makes it attractive for use as the intermetallic dielectric in MIMcapacitors.


Ken Mackenzie, Brad Reelfs, Mike DeVre, Russ Westerman, and Dr. Dave Johnson, Unaxis Wafer Processing


Unaxis Chip | 29

system is capable of batch handling eight 100 mm GaAs or five 150 mm GaAs wafers. The PECVD reactor is aconventional parallel plate configurationand uses a 13.56 MHz RF power source to generate the plasma. Wafertemperature can be controlled over a range of 100°C to 350°C. To obtain ahigh yield and minimize system downtime,several features in the PECVD reactorhave been implemented to maintainsystem cleanliness. For example, both the chamber walls and the upper gasdistribution electrode of the reactor areheated to minimize particulate formationduring the SiNx deposition process. In addition, an automated plasmaetchback sequencer interfaced to an in-situ optical emission spectrometer is used to achieve and consistentlymaintain the reactor in a clean state.Single wafer modules with either manualor automatic loading are also available for situations where batch processing is unnecessary.

For process optimization, a two level full factorial design on three factors was constructed for the DOE. The three factors were NH3 gas flow rate,N2 /(N2+He) gas flow ratio, and RF power.All films were deposited at 300°C. The diluted SiH4 gas flow rate, processpressure, and the combined N2 and He gas flow rates were held constantduring the experiments.

The measured responses wererefractive index, deposition rate, thicknessnon-uniformity, stress, and wet-etch rate.The thickness non-uniformity is defined as the thickness range divided by twicethe mean thickness expressed as apercentage. The edge exclusion was 6 mm. A buffered oxide etch (BOE)


–400

–200

0

200

400

0 20 40 60 80 100

20 W

50 W

100 W

Str

ess

[MP

a]

Tensile

% N2 in (N2 + He) mixture

Compressive

Figure 2: Generalresponse trendsfrom DOE

Figure 1: Stresscontrol of PECVDSinx by the Hedilution method atthe different rf powerlevels indicated

Responses

Fact

ors

NH3

Power

Index Deprate

Thicknessnon-uniformity

Stress Etchrate

% N2 / He Ô

Ô Ô

Ô

Ô

Ô Ô

Ô

Ô Ô Ô

Ô Ô Ô Ô

Ô Ô Ô ÔÔ ÔÔ Ô– –

solution of 7:1 NH4F : HF was used for the wet-etch rate measurements.

Designed experiment resultsIn Figure 2, the general response trendsfrom the analyzed DOE are summarized.The up and down arrows indicate thedirectional change in the response resultingfrom an increase in a process factor, NH3

gas flow rate, N2 concentration in He, or RF power. Double and single arrowsrespectively indicate a strong or weakdependence of a response on a factorover the range investigated. All threefactors have a major influence on the SiNx

film stress. The measured film stressesranged from about 300 MPa, tensile toabout 400 MPa, compressive.

30 | Chip Unaxis


30 | Chip Unaxis

Low stress optimizationFigure 3 summarizes the typical customerproperty requirements for a low stressSiNx film. Figure 4 maps out the predictedprocess space from the DOE for thesecriteria as a function of NH3 gas flow rateand N2/He concentration in the plasma.These results clearly indicate a practicalprocess regime exists to achieve a low-stress silicon nitride film to meet thedesired criteria. The deposition rate for the low stress films is greater than 100 Å/min. Faster deposition rates arepossible with either higher RF power ormore concentrated SiH4.

Stress control mechanismExamination of the optical emissionspectra of the deposition plasma providesimportant insight concerning themechanism responsible for compressivestress by the He dilution method. Shownin Figure 5 are two 13.56 MHz plasmaspectra, pure N2 and 10% N2/He. Thesecorrespond to deposition conditionsassociated with tensile and compressivefilms. Emission lines at 391.4 nm and427.8 nm are present in the 10% N2/Heplasma and are absent in the pure N2

plasma. These two lines are assigned toN2

+ ions and indicate its presence in the10% N2/He plasma. As shown in Figure 5,these N2

+ spectral lines are also present in a 380 kHz N2 plasma without any Hedilution. SiNx films prepared from SiH4,

Film parameter Range

Stress (MPa) –100 to +100

Refractive index 2.0 to 2.05

Thickness non-uniformity (%) < ± 2.5

Wet-etch rate (Å /min) > 300

Figure 5: Opticalemission spectra forvarious plasmas.Spectra aredisplaced verticallyfor clarity.

Figure 4: Overlay plotfor an optimized lowstress SiNx process.Non-shaded area isthe optimizedprocess regime.Point in centerdenotes center pointof the design.

–1.0 –0.5 0.0 0.5 1.0

10

12

14

16

18

20

< 100 MPa

Index: < 2.05

Index: > 2.0

< -100 MPa

< ±2.5%

Relative NH3 flow rate

% N

2 in

(N2

+ H

e) m

ixtu

re

0

10

20

30

40

360 380 400 420 440 460

Wavelength [nm]

Pla

sma

inte

nsit

y

Compressive

Compressive

Tensile

N2+

N2+

N2+

N2+

100% N2LF: 380 kHz

100% N213.56 MHz

10% N2/He13.56 MHz

Figure 3: Criteria forlow-stress SiNx

process optimization.


32 | Chip Unaxis

Silicon dioxide can be deposited as a thin film by various techniques includingflame hydrolysis at atmospheric pressure,CVD, PECVD, and sputtering. For someapplications, a deposition step alone issufficient, but more commonly thedeposited film is subsequently etched todefine features into the oxide. Because ofthe many different uses of silicon dioxide,it is not surprising that the requirements of the etch process are highly variable.Thus, feature sizes may range from sub-micron to millimeter and etch depths from less than 100 nm to greater than100 micron. The required etched profilevaries from highly vertical to highly sloped, and different mask materials, such as photo-resist and various metals,are used. The substrate material includessilicon, metals, ceramics, and quartz invarious shapes and sizes. Fulfilling theserequirements places a severe demand onthe etch process and platform, with someapparently mutually exclusive constraints.However, since silicon dioxide is used to some degree in all of the Unaxistargeted market areas, solving theseissues and developing an oxide etchsolution has presented a key challenge.

High Performance Oxide Etchingon the new VERSALINE™ Platform

Silicon dioxide is used in the manufacture of many types of devices, both semiconductor-based and other, where it is chosen because its physical properties can meet the needs of a wide range of applications. For example, its excellent electrical properties as aninsulator and dielectric make it suitable for use in the fabrication of capacitors and as aninter-level dielectric material. It finds use in applications such as MEMS and hard drive head construction, where its mechanical strength and good chemical resistance can makeit the material of choice. The optical properties of silicon dioxide (both as a thin film and as bulk quartz) lead to its extensive use in the production of optical devices such asphotomasks, micro-optics, and waveguides.


Dr. Dave Johnson, Director of Research& Development

RF 2 MHz

Gas inlet

Substrate

RF13.56 MHz

Vacuum

High densityplasma

Temperature-controlledelectrode

Figure 1: Inductivelycoupled plasmaprocess module

Table 1: Oxide etch,range of requirements

Parameter Minimum Maximum

Etch depth < 1 µm > 100 µm

Etch rate < 1000 Å /min > 1µm/min

Etch rate uniformity < 2% –

Selectivity (to photo-resist) < 1 : 1 > 10 : 1

Selectivity (metal mask) – > 50 : 1

Wall profile Replicate mask profile 90°

Substrate size 2 inch 200 mm

Substrate type Silicon Quartz, ceramic, metal

Unaxis Chip | 33

Oxide etch processThe solution is not to have just a single“oxide etch process,” but rather a flexibleoxide etch capability, the performance ofwhich is well understood and controllable.Table 1 outlines the range of capabilitiessuch a process must meet. The twofactors which create the biggest challengeare high etch rate and high selectivity to aphotoresist mask. This is best understoodby a more detailed knowledge of the oxide etch mechanism.

The energy necessary to break thestrong Si-O bond is provided bybombardment from plasma-generatedions that have been accelerated to thesubstrate surface. This is convenientlydone in an Inductively Coupled Plasma(ICP) configuration where inductivecoupling is responsible for generating the plasma and a separate substrate RFbias controls the ion energy (Figure 1). In order to achieve a high oxide etch rate,a high plasma density is required, which in turn requires high power operation of the inductive source. Importantly, thisrequires the ability to then handle the heat generated by such a high poweroperation.

Silicon dioxide is etched using variousfluorocarbons such as CF4, CHF3, andC4F8 that react with SiO2 to form volatileby-products. However, these F-containinggases also readily etch photo-resist,especially in the presence of energetic ion bombardment (necessary for a highoxide etch rate). Therefore, to achieveselective etching of the oxide relative tophoto-resist, polymer-promoting gases areusually added in the gas mix. When the gasratio and ion energy are carefully adjusted,such gases will cause the deposition ofpolymer on photo-resist surfaces, but on

oxide surfaces the presence of -O tends to oxidize any polymer and the surfaceremains clean and continues to etch. UsingH2 or H-containing fluorocarbons as thepolymer promoting additives, it is possibleto increase the oxide:resist selectivity ratio to values of 10 and higher. However,the polymer also tends to deposit on other plasma-contacted surfaces, whichultimately leads to flaking, particle contamination, and excessive downtime for cleaning. The deposition can beeliminated by elevating the temperature of these surfaces above the polymercondensation point, and this may be 150°C or higher, depending on the processconditions. This temperature must bemaintained, even when the plasma is off, to ensure long-term process stability.Hence, the requirement of selective etchingdrives the need for high temperatureoperation and control. This, plus the need

for high power operation, represents themajor challenge in designing a flexible oxideetch process.

Hardware designBased on the above requirements, the design of an oxide etch modulebecomes primarily an exercise in thermalmanagement. One of the first steps was to understand the heat balance in terms of power-deposited (from the plasma)versus heat-loss pathways. Temperaturemeasurements and a calorimetric analysiswere used, and the data collected wasused to verify a Computational FluidDynamics (CFD) software model (Figure 2).The close matching of the measurementsand the model-predicted parametersallowed new design options to be firsttested in software, with a high degree ofconfidence that the model output wouldrepresent actual performance.


ICP = 1000Watts

T °C150

140

130

120

110

100

90

80

70

60

50

40

30

Figure 2: CFD modelshowing ICP sourcetemperature

34 | Chip Unaxis

In this way, a design to heat andtemperature control the ICP surfaces was created without the need for time-consuming “cut and try” methods:essentially, the first prototype built met the performance specifications. Thetemperature control achieved with thisnew design versus the original ICP design is shown in Figures 3 and 4.

Likewise, a similar analysis andmodeling of the lower electrode assemblyhelped to recognize a weakness in thecurrent design. With a new design, theheat rejection improved by a factor of ~2,a significant improvement which helpsmaintain temperature control of thesubstrate in high power applications.

Additional changes were made to theRF coupling, permitting continuous highpower operation. Other changes, againbased on CFD modeling, were made tothe reaction chamber, which improved the pumping speed while reducing theinternal volume, aimed at minimizing anycontamination-producing surfaces.

These various components that makeup the High Performance Oxide Etcher(HiPOE) have been designed as modules,which are incorporated into the newVERSALINE™. From conception, thisplatform has been designed with modularityin mind, so such application-specificimprovements can be implemented withthe minimum impact on the overallplatform.

Process results The operation of the oxide etcher with the modified hardware was testedover a range of process parameters,encompassing a number of applications.At one end of the application range is a relatively shallow (< 2 µm deep) etch


Figure 3: ICPtemperature stabilitybefore modification

Figure 4: ICPtemperature stabilitynew design

20

40

60

80

100

120

140

0 20 40 60 80 100

Time [min]

RF cycle:15 min on @ 1 kW3 min off

Tem

p [

°C]

20

40

60

80

100

120

140

160

0 10 20 30 40

Time [min]

RF On

RF Off

Initial warm-up RF cycle:5 min on @ 1.5 kW5 min off

Tset = 125°C

Tem

p [

°C]

Unaxis Chip | 35

into quartz, where etch rate is a secondaryconsideration, but a precise selectivityratio to resist of 1:1 is the primary factor.This ensures that resist features areaccurately transferred into the quartzsubstrate and used to make refractiveoptics. Such an etch, reproducing aFresnel Lens surface is shown in Figure 5.

The same etch can replicate sphericallens surfaces when the photo-resist maskis first heated and reflowed. An interestingmodification to this etch is obtained whenthe selectivity to resist is increased tovalues > 1:1. Then, the original sphericalmask profile is etched into the quartz tocreate an aspherical surface, the opticalproperties of which can be tailored toproduce high efficiency, small numericalaperture lenses suitable for fiber opticcoupling. Figure 6 shows such a lensetched to a depth of ~40 µm into quartz at a rate of ~4000 Å/min. By operating thesource at 150°C for this higher selectivityprocess, essentially no detrimentalpolymer formation takes place.

The highest oxide etch rate process is obtained using high ICP powers andhigh bias powers. Figure 7 shows an etch rate of 1µm/min is obtained at ICPpowers of ~2000 Watts when etchingPECVD oxide. Etch rates up to 1.4µm/minhave been measured at the maximumoperating power level of the ICP.Generally, such high power processes can best exploit the stability of metalmasks and have been used to defineprecise structures into thick oxide films (10 µm) for waveguide applications.

SummaryA new process module has been designedas part of the new VERSALINE™ platform,to meet the many and varied oxide etch

needs. Much of the design involving heat and gas flow was done usingcomputer-based modeling, which cut the need for extensive prototyping. This process has been tested over a wide range of conditions and has showndramatic improvement over priorcapability.



Figure 5: Crosssection of Fresnellens etched intoquartz substrate

Figure 6: Highlyaspherical lensetched ~40 µm deepinto quartz substrate

Figure 7: Etch rate of thermal and PECVDoxides at different biaspowers

0

2,000

4,000

6,000

8,000

10,000

12,000

100 200 300 400

RIE [Watts]

Thermal oxidePECVD oxide ICP = 2,000 Watts

Etc

h ra

te [

Å/m

in]


36 | Chip Unaxis

In a DSE process, different gases areintroduced into a reaction chamber atdifferent rates, and chamber pressures are maintained at different levels in thealternating steps. It is the alternatingprocess conditions that make pressurecontrol challenging.

Conventional pressure control Throttle valves are conventionallyoperated in either pressure mode orposition mode. In these two modes, the internal proportional, integral andderivative (PID) control mechanismsregulate the movement of a throttle valve according to prescribed pressure or position values. In pressure mode, forexample, the chamber pressure is given. A throttle valve adjusts its position toachieve the desired pressure. Very often,gas synchronization and particular mixesof process conditions make it difficult toeffectively control pressure. As illustratedin Figure 1a, chamber pressure exhibitssignificant overshoot or undershoot.

When a passivation step (low pressure)is alternated to an etch step (highpressure) as shown in Figure 1a, thethrottle valve initially moves to a moreclosed position. But etchant gas SF6 isintroduced into the chamber at a higherrate, so pressure overshoot occurs. Thethrottle valve then moves to a more openposition and subsequently settles in a final

Pressure Control in Deep Silicon Etch Processes


Dr. Shouliang Lai, Senior Process EngineerRuss Westerman, Director of TechnologyDr. Dave Johnson, Director of Research & Development

80

60

40

20

0

–20

70

60

50

40

30

20

Pre

ssur

e [m

T]

Po

siti

on

[%]

0 5 10 15

Time [s]

20 25 30

P (etch)setpoint

P (dep)setpoint

5s dep/4s etch

Pos (etch)setpoint

Pos (dep)setpoint

Desiredpre (etch)

Desiredpre (dep)

40

30

20

10

0

–10

–20

70

50

30

10

0 10

Time [s]

20 30 40 50 60 70

Pre

ssur

e [m

T]

Po

siti

on

[%]

Figure 1a: Pressure (left axis)and throttle valveposition (right axis)in pressure mode.Pressure overshootand undershootoccur when processsteps alternate.

Figure 1b: Throttle valveposition (right axis)and the resultantpressure (left axis) in position mode.Chamber pressureexhibits slowresponse andundesired profile.

a

b

From telecommunication, to automotive, to biomedical applications,MEMS technology plays an increasingly important role. In the manufactureof such MEMS devices the time division multiplexed (TDM) plasmaprocesses are widely applied for deep silicon etching (DSE)[1]. The processemploys cyclically alternating etching and passivation steps[2].

Unaxis Chip | 37

position. When an etch step is alternatedto a passivation step, the throttle valve hasa more opened position initially, causing apressure undershoot. Generally speaking,such pressure deviations get worse whenprocess steps get shorter. Pressure over-and undershoot harm plasma stability andetch performance, and spuriousmovement of throttle causes valvewearing and particle contamination.

In position mode, the position of thethrottle valve is given. A learningprocedure is required to establish thecorrespondence between pressure and position. As shown in Figure 1b,pressure response is slow, and actualpressures are not stabilized even when the throttle is positioned at constantvalues. Moreover, since pressure controlnow is essentially an open-loop control,long-term pressure drift occurs, causingproblems in maintaining DSE processrepeatability. There have been someefforts in devising methods to bettercontrol chamber pressure in alternatingprocesses [3–6]. While these approacheshave their own advantages, variousdrawbacks exist.

New pressure controlRecently, a novel technique has beendeveloped to improve pressure controlcapability in DSE. The method isillustrated in Figure 2. In pressure mode,pressure overshoot and undershoot occurin transient periods td1 and te1, while instable periods td2 and te2 pressure is wellregulated. In position mode, overshootand undershoot tend to be suppressed,while pressure in the stable periods is notwell regulated. Thus, a combination ofpressure mode and position mode mayhave the benefits in both suppressing

pressure irregularity and maintainingpressure control. In doing so, a throttlevalve can be pre-positioned properly inperiods td1 and te1, when an open-loopcontrol is enabled. In periods td2 and te2, a close-loop control is used to regulatepressure. The internal PID functions of the throttle valve are utilized to facilitatesuch controls.

The new pressure control technique for TDM etch processes has been testedon a DSE™-III tool, which has a highvacuum conductance and is equippedwith an ICP source. A High-density SF6

plasma is used for etching and a C4F8

plasma for passivation. Figure 3 showsimproved results with the new pressurecontrol technique. The etchant andpassivation gases have flow rates of

400 and 50 sccm, respectively, and thegiven pressures are 50 and 20 mTorr. As illustrated, the pressure overshoot andundershoot during transition periods arecompletely eliminated. Pressure has anearly “squared” profile, and pressuretransient times are reduced.

This novel pressure control techniquealso improves long-term process stability.It is usual that the temperature of chamberwalls varies during and between processruns. Such temperature variation affectsplasma pressure. Because pressure is oneof the primary determinants of etch rate,DSE performance would fluctuate overtime if long-term pressure stability is notmaintained. This issue is especially aconcern in the position control mode. In essence, our new technique exerts


Figure 2: Newpressure controltechnique: in thetransient periods,open-loop pressurecontrol is enabled; inthe stable periods,close-loop pressurecontrol is enabled.

Figure 3: Improvedpressure profileobtained with thenew pressure controltechnique

Passivation Etch

Transientperiod

Stableperiod

Transientperiod

Stableperiod

td1 and te1: Transient periods, open-loop pressure control enabled

td2 and te2: Stable periods, close-loop pressure control enabled

td1 td2 te1 te2

10

20

30

40

50

60

0 10 20 30

Time [s]

Pre

ssur

e [m

T]

3s dep/4s etch

38 | Chip Unaxis

close-loop control on pressure. It enablesthe long-term pressure drifts to beeliminated, as demonstrated in Figure 4.The etch pressure remains at 90 mTorrduring a continuous process operated forover 70 minutes at very high ICP power.

Application in MEMS manufacturingMEMS manufacturing demands TDM etch processes to satisfy a wide range of etch performance requirements, and often trade-offs must be made. For example, high etch rate and smoothsidewall smoothness are normallyincompatible in conventional TDM etchprocesses. But in some MEMSapplications, optically smooth surfacesare needed along with high etch rate for throughput considerations. A fast gasswitching technique has been developedby Unaxis Wafer Processing to achievehigh etch rates while minimizing scallopson the Si sidewall [7]. The process stepsare short, close to 1.0 second only, andconventional pressure control methods donot apply.

The new pressure control technique isespecially advantageous in controllingpressure in processes with very short steps. Pressure response time is reduced,and pressure profile is improved. Thus, the new control is an enabler to the fast gasswitching technique. Figure 5 shows theimproved plasma etch capability. Trencheswith a4 µm wide opening are etched into 150 mm silicon wafer. The trenches have an aspect ratio of 10:1. As demonstrated,the overall etch rate is 6.4 µm/min, while the scallop depth is below 10 nm. Theplanar view SEM image on the right confirmsthe smoothness of etched silicon trenchsidewalls.


Figure 4: An exampleof long-termpressure stabilityusing the newpressure controltechnique.

Figure 5: Opticallysmooth deep siliconstructure etched in aDSE™ process withshort steps. Scallopdepth is below 10nm, and overall etchrate is 6.4 µm/min.

75

80

85

90

95

100

0 200 400 4,0001,800 2,000 2,200 4,200 4,400

Time [s]

Pre

ssur

e [m

T]

ICP = 3000 WSF6 = 400 sccmP(etch) = 90 mT

In conclusion, the new pressure controltechnique opens up a new dimension inDSE processing. The Unaxis proprietoryDSE™ III process technology workstherefore with a unique algorithmimplemented in combination with thevalve’s internal PID control function.Pressure over- and undershoot and long-term pressure drift are eliminated and response times are significantlyimproved.

DSE™ III provides higher processreliability and etch rates for DSE MEMSmanufacturing.


References1 K. Suzuki et al., U.S. Patent No. 4,579,623, April

1, 1986; F. Laermer and A. Schilp, U.S. PatentNo. 5,498,312, March 12, 1996.

2 S. Lai et al., Chip Magzine, Vol. 8, March 2003,pp. 35–36.

3 M. Puech, U.S. Patent No. 6,431,113, August 13, 2002.

4 F. F. Kaveh et al., U.S. Patent No. 5,758,680,June 2, 1998.

5 B.K. McMillin et al., U.S. Patent No. 6,142,163,November 7, 2000.

6 C. Beyer et al., U.S. Patent No. 5,944,049,August 31, 1999.

7 S.L. Lai et al., Proc. on Micromachining andMicrofabrication Process Technology VIII, SPIE-4979, pp. 43–50, San Jose, California,2003.

Unaxis Chip | 39


The deep silicon etching process found in widespread industrial use [1, 2] is oftenreferred to as being Time DivisionMultiplexed. The reason for this name is the process cycles alternating betweenetching and passivation cycles. Usingwell-known established SF6 chemistry in an ICP dry-etching chamber, silicon is etched at high rates followed by a fluorocarbon deposition step to keep theetched profile vertical. In addition tosatisfying high etching rate requirements,the DSE™ process meets the conditionsof smooth sidewalls, selectivity-to-masking

materials, and lateral mask undercut. [3]SOI wafers have the additional constraintthat “notching” [4] must be eliminated. Unaxis Wafer Processing removes SOIlimitations with its DSE™ technology.

Charging of buried oxide and notchingSOI wafers have a layer of single crystalsilicon atop a silicon oxide layer. In itssimplest forms, the SOI wafer is an oxidefilm on a silicon wafer where the oxide is deposited either through thermaloxidation, PVD, CVD, PECVD, or even

simpler, a silicon wafer bonded to glass. In these cases, a membrane can beformed by etching of the silicon wafer and stopping on the oxide or insulatinglayer. In more complex designs, the oxidelayer can be “buried” beneath anotherlayer of silicon. When used in this manner,the oxide can also behave as an etch stop or as a local release “sacrificial layer.”Typically, with an etch stop layer, the effects of Aspect Ratio DependentEtching (ARDE), where different featuresizes etch at different rates, should not be apparent. In ARDE, mass transfer ofreagents and reaction products result inwider features etching faster and reachingthe buried oxide layer faster than thenarrower or higher aspect ratio features.During the time between when the widerfeatures have reached the oxide and thenarrower features are still being etched,positive charge builds up on the widerfeatures. The positive charge built upbefore the buried oxide layer is exposedrecombines effectively through the bulksilicon as shown in Figure 1a. Once theoxide layer is exposed to the plasma, a positive charge builds up on theinsulator. Simplistically, this accumulationof positive charge leads to preferentialetching of silicon at the Si-oxide interface,as is illustrated in Figure 1b.

DSE™ Notch Reduction for SOI

Sunil Srinivasan, Associate Scientist Dr. Dave Johnson, Director of Research& DevelopmentRuss Westerman, Director of Technology


Micro-Electro-Mechanical Systems (MEMS) applications areincreasingly turning towards silicon-on-insulator (SOI) wafers.The creation of low-stress, flexible structures made possible with SOI wafers is increasing surface micro-machining opportunities. One of the critical processes in many MEMSfabrication flows is the Deep Silicon Etch (DSE™) of high aspect ratio silicon structures.

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Figures 1a and 1b:Charging mechanismin conventional DSE™TDM etch

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The bulk of silicon in the SOI wafer isetched with a conventional DSE process(t1). This process produces smoothsidewalls at a fast etching rate, with highselectivity-to-mask, and minimumundercut. The second part is a “finish”etching process that is utilized to etch the smallest features and is equal to theoveretching period t3. A critical

40 | Chip Unaxis40 | Chip Unaxis

The profile of the feature formed from this preferential lateral etching is called“notching.” The notch formed at the Si-oxide interface is a function of aspectratio (feature depth divided by featurewidth) and the time of the overetch [5].Usually, “overetch” on a cleared feature is described as the percentage of overallprocess time it is exposed to the plasma,while the smaller features are beingetched. Due to ARDE and the range offeatures sizes on a wafer, overetchpercentages may be as high as 60% onthe wider features. The aspect ratiodetermines the extent to which notchingoccurs and worsens as the aspect ratioincreases.

Unaxis DSE™ SOI solutions The problem of charge formation andnotching with conventional DSEprocesses prompted Unaxis WaferProcessing to develop a proprietarymethod to reduce and in certain cases,eliminate notching. This method requiresthe etching process be divided into two parts, as illustrated in Figure 3a.

component of this hybrid process is thetransition between the bulk and finishetching steps. Since notching is sensitiveto the overetch percentage, any significantexposure of the oxide to the plasmaduring t1 will cause notching. In order tomake the transition at the appropriatetime, Optical Emission Spectroscopy(OES) is used to detect initial exposure

Figure 2: Notching at Si-buried oxideinterface in conventional DSE™ TDM etch

Figures 3a and 3b:Process schematicshowing bulk DSE™ III TDM andUnaxis proprietaryDSE™ III TDM finish etch DSE™ III TDM

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DSE™ III TDMFinish etch, t3

Process time, t Buried oxide layer

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Unaxis Chip | 41Unaxis Chip | 41

of the oxide in the widest features. This is t2 in the Figure 3a. With Unaxisproprietary OES endpoint algorithmuniquely programmed for TDM, exposedoxide in the lowest aspect ratio features is detected at as little as 2% open area ona 150 mm wafer.

As illustrated in Figure 3b, the etchingdepth in the various features depends onthe feature widths. The feature on the farright is almost entirely etched using thebulk etch. The OES end point algorithmsdetect when the features equivalent to thefar right feature are cleared throughout thewafer. The unetched silicon in the higheraspect ratio features is then etched usingthe DSE finish etching process. Figure 3bhighlights the transition between the DSE bulk etching step and the DSE finishetching step with respect to the differentfeatures. Using this hybrid process,notching at the Si-oxide interface is greatlyreduced. Innovative Unaxis finish etchingprocess technology compensates for the conditions leading to notch formation,namely, positive charge accumulation on the buried oxide interfaces.

The SEM in Figure 4a is a cross-sectionof a standard Unaxis SOI test structureetched with this hybrid DSE SOI process.The aspect ratios range from 22:1 to 5:1in the cross-section for the 30 microndeep features. As seen, the notching iscompletely eliminated from 10:1 aspectratio feature and lower. By using thishybrid process for SOI wafers, significantoveretching of the smaller aspect ratiofeatures is possible. Even with significantoveretching, notching is not seen on the5:1 aspect ratio features and lower. This is illustrated in Figure 4b with a high-magnification image of the silicon-oxideinterface on a 5:1 aspect ratio feature.

ConclusionsThe emerging importance of SOIsubstrates for MEMS processing is thedriving force behind Unaxis’ DSE SOIhybrid process. The opportunity forMEMS designers to incorporate SOIstructures in their devices requireseliminating notching without sacrificingetching rate, sidewall smoothness, profile,or selectivity. This recent progressmaintains the advantages of using a high-density plasma for high-rate deepsilicon etching. A two-step hybrid processthat relies on sensitive endpoint detectionand charge dissipation effectivelyeliminates notching.

Figures 4a and 4b:Notch reduction withUnaxis proprietaryDSE™ III TDM finishetch

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References1 F. Laermer et al., U.S. Patent No. 5,498,3122 Suzuki et al., U.S. Patent No 4,579,6233 S. L. Lai et al., Proc. on Micromachining

and Microfabrication Process Technology VIII, SPIE-4979, pp. 43–50, San Jose, California,2003

4 Gyeong S. Hwang et al. , J. Vac. Sci. Technol. BJan/Feb 1997

5 Gyeong S. Hwang et al., J. Apply. Phys. 82(2) ,July 1997

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