Business & Technical News from Unaxis Semiconductors · Silicon Technology 10 High-Performance...

Business & Technical News

from Unaxis Semiconductors

March 2003 | Issue

■ China – the New Hub of theSemiconductor Industry?

■ Introducing theSHUTTLELINE™

■ MEMS for Hard Disks

■ Unaxis Customers Benefitfrom New Service Packages

co

nte

nts

co

nte

nts

4

22The new Unaxis

SHUTTLELINE™ –

the world’s most cost

effective etching

and deposition tool

for R&D and pilot

production

China has become

an important player

in the semiconductor

industry

www.semiconductors.unaxis.com

Unaxis Insights

Skills Management at Unaxis Semiconductors 2

Quality Service – Quantity YieldSuperior service and maintenance packages from Unaxis Semiconductors 3

Unaxis Shanghai Has Opened it’s DoorsThe Unaxis Greater China team has movedinto the new Shanghai regional headquarters 4

Feature

The People’s Republic of ChipsChina’s rise in the semiconductor industry 5

Advanced Silicon

SiGe – a Basic Material for Silicon Technology 10

High-Performance Bipolar Transistors 13

Together We SucceedSiGe joint development projects 16

LEPP 300 – SiGe Process Development Part II 17

Advanced Packaging

Unaxis and ASE – Expanding Performanceand Partnerships Across the Globe 19

Under Bump Metallization forPb-Free Bumping 20

Compound Semiconductors

Introducing SHUTTLELINE™The latest product offering from Unaxis Semiconductors 22

GaN Dry Etching ProcessesRecent advances in process solutions 26

MEMS Enhance Hard Disk Drive PerformanceHigh-performance hard disk drives are a promising arena for the next generation of MEMS devices 28

High Rate Reactive Alumina DepositionInvestigating dielectric fill applications with the Unaxis CORONA® system 34

DSE™ III – Unaxis’ New Deep Silicon Etch TechnologyThe next generation of faster, more capable, dry etching tools 35

Index 37

3New service and

maintenance

packages from Unaxis

Semiconductors

Unaxis Chip | 37

ind

ex

ind

ex

B

BiCMOS 10Boron out-diffusion 14

C

Carbon 14China 5CLUSTERLINE® LEP 16CMOS 10, 16Coil fill 34Complete solutions 21Compound semiconductors 11, 22, 26CORONA® 34Customer support 2, 3, 4, 21

D

Deep Silicon Etching (DSE™) 23,30,35Deposition 10, 13, 16, 17, 22, 34Dynamic frequency divider 11

E

Etching 13, 22, 23, 26, 36

F

Flip-chip 20

G

GaN process solutions 27Global Key Account Management 3Greater China 4Gummel plot 15

H

Hard disk drive 28HBT 10, 16, 23HDP 23Hetero CMOS 16High rate reactive alumina 34High bias 34

I

IC packaging 20IMC 20ICP 23, 26

J

Joint development 16, 21

L

LEPC 17LEPECVD 16, 17Loadlock 24Low pressure 34

M

Maintenance 3MEMS 28, 35Microactuators 29

N

Nitride 26Non-selective epitaxy 13, 14Non-selective SiGe:C epitaxy 13

P

PECVD 23P-MOSFETs 16Pb-free 20Poly-SiGe 14

R

Relaxed buffer 18RIE 23

S

Sales 3Scaling power 11Service 2, 3, 4SHUTTLELINE™ 22Sidewall smoothing 36SiGe 10, 13, 16, 17Silicon on insulator 36Silicon-based high speed

bipolar transistors 13Skills Management 2Solder 20Step coverage 34Strained silicon 12

T

TDM 35Titanium self-aligned silicide

process 15

U

UBM 20UHV-CVD 16

V

Virtual substrates 16, 17

A � Z

North America

Unaxis USA Inc., [email protected] Tel +1 727 577 4999Fax +1 727 577 7035

Europe

Unaxis Deutschland GmbH, [email protected] Tel +49 89 7550 5251 Fax +49 89 7550 5111

China

Unaxis (Shanghai) Co., [email protected] Tel +86 21 5057 4646Fax +86 21 5057 4647

Singapore

Unaxis IT Pte. [email protected] Tel +65 6890 6288 Fax +65 6890 6290

Korea

Unaxis Korea Ltd., [email protected] Tel +82 31 708 8666Fax +82 31 708 7666

Taiwan

Unaxis Taiwan Ltd., Hsin [email protected] Tel +886 3597 7771Fax +886 3598 6161

Japan

Unaxis Japan Co. Ltd., [email protected] +81 3 3225 9020Fax +81 3 3225 9043

Other Markets

Unaxis Balzers [email protected] Tel +423 388 4986Fax +423 388 5909


Feature

Front Cover

UnderstandingUnder BumpMetallizationthrough hands-ontraining on the 300 mmCLUSTERLINE®

Editor in Chief

Juerg Steinmann, Global CommunicationsManager UnaxisSemiconductors

Managing Editor

Veronika Schreyer, is design

Design /Layout

Cactus AG

Photography

Michael Reinhardand Unaxis, unlessstated otherwise

Published by

Unaxis SemiconductorsP.O. Box 1000FL-9496 Balzers Liechtenstein

Printed by

Südostschweiz Print AG

If you have any questions or comments,please contact us at [email protected] or fax back the reply cardprovided in thismagazine.

Chip, the Business & Technical News from Unaxis Semiconductors,is also available online at:

Dr. Martin Bader, Executive Vice President, Unaxis Semiconductors

and President Unaxis North America

ed

ito

rial

ed

ito

rial

Unaxis Chip

Welcome to our newest edition of Chip!Despite the delay in the promise of industry upswing, Unaxis Semiconductorscontinues to progress. Focus on customer service, investment in R&D and,especially, our expanding global presence have all been important to our strongposition in the slowly recovering market.

This issue of Chip includes a feature article on Greater China (p. 5), because this fascinating country and its role in the semiconductor industry warrant closerexamination. China, currently with an unrivaled growth rate is considered a majordriving force in today’s world economy, despite the fact it produces just 4% of the world’s gross product. Unaxis Semiconductors has been in China for over 30 years and by opening its new regional headquarters in Shanghai (p. 4) has again strengthened its presence.

We consider service excellence a prerequisite for long-term business successand are committed to improving our position within the "10 BEST”. Our new Service Packages and skills management are another step forward (pp. 2–3).

Unaxis Semiconductors is introducing a new tool, the SHUTTLELINETM. Merging the technology of four systems with the extensive experience of aninstalled base of more than 650 tools, the SHUTTLELINETM is ideal for smallvolume production. Its multi-process platform for etching and deposition givessuperior process solutions for HBTs, HEMTs, SAW, Photonics and MEMS (p. 22).

Our SiGe development collaborations have made significant advances (pp. 17–18). An interesting application on high performance bipolar SiGe transitions is reported by Ericsson (p. 13–15).

I hope you find Chip 8 informative and a pleasure to read. Thank you for all thepositive feedback on our last issue. Please feel free to send us your questions orcomments to [email protected] or use the inserted Reply Card.

Dr. Martin Bader


10

20

30

40

50

60

70

80

90

100

110

BAK EVO handling systemZ620 system type

Vacuum

SAP basics

PVD

BAK EVO Add. PLC

PECVD

BAK EVO system type

BAK familiy with old controllers

BPU420(G)(E)431 for BAK

Business process knowlegde

CVD

Clean room

�� Actual profile �� Required profile

2 | Chip Unaxis

Unaxis Insights

With the many Unaxis products andprocesses, how do we assure that ourservice and application engineers aretrained to the required high skill level? Here, as well as for the service packagedescribed in our “Quality Service –Quantity Yield” article, the starting pointwas our Customer Care Program.

Speed is the magic word for customerswho are waiting for a service engineer to repair their machine. The problems are complex, involving products andprocesses, and for any solution –especially a quick solution – the right skills and qualifications of engineers are essential. The Unaxis SkillsManagement program meets this need.

The objective of this project is to assessthe current skill level of service and

application engineers, compare them tothe requirements in the field and assessany skills gap which become apparent inthe process (Figure 1).

A special SAP application was createdwhich helps in the assessment,evaluation, and choice of appropriatetraining opportunities.

Each engineer is assessed and qualifiedaccording to:� Basic competence� Product competence� Process and software competence

A level of 1–5 is assigned to the qualifications. The program generates a training proposal according to thedifference between the current qualification profile and the required

profile (Figure 2). The line manager thendecides whether training measures arenecessary. If they are, training courses areeasily reserved by clicking on “pre-book”in SAP. This information is automaticallyrelayed to the respective training centerwhich returns a quotation and invitation.Once the training course is successfullycompleted, the technician’s file is updatedwith the new qualification.

By the end of 2002 all relevant data was implemented in SAP and the firstSkills Management training courses havebeen sceduled. The global roll-out startedin January 2003.

For more information please contact:[email protected]

Unaxis Insights

Skills Management at Unaxis Semiconductors

Figure 1: Skills

Management

overview

Figure 2: Example

of skills comparsion

HR

da

ta o

n S

AP

Qualifications

Positiondetails

Requiredqualification

Personaldetails

Actualqualification

Comparison

Skills gap

detected

Training

required

Event management

Training center

New

Qualification

Adrian Lodder,

Customer Support Manager,

Unaxis Semiconductors

“The Unaxis Skills Management program lays the foundations for a newunderstanding of quality. It is a stepping stone into the future that uniquelycombines field service requirements with personnell management and trainingresources to the benefit of our customers. Developed to enhance our serviceperformance, it is foreseen to extend this program to the entire sales andcustomer support organization.”

Ralf Kuhlmann, International Sales and Market Manager

Unaxis Chip | 3

Customer Satisfaction is the key to a mutually profitable relationship. The deciding factors which make thisrelationship work are a high skill level of employees, structured knowledgemanagement, and measurableperformance. Unaxis Semiconductors’Global Key Account Managementhas set out to develop service packageswhich will give Unaxis customers the edge.

The Unaxis Semiconductors

Service Packages

The service packages aim to support and improve all areas that influence machineperformance. Increased up-time willincrease yield and – in the long term –lower the cost of ownership. The servicepackages cover the whole product lifetime

and can be tailored at various levels toeach customer’s needs.� Commissioning

Unaxis offers pre-installation site facilitiessurveys, on-site commissioning, andvarious start-up and production ramp-upsupport programs.

� Training

Excellent service requires excellentpeople (see “Skills Management” p. 2).The Unaxis Semiconductors SupportPackage places special emphasis oncustomer-specific training programs,tailored to a particular productionplatform and maintenance requirements.Training can take place at the customer’slocation or at Unaxis training centers on selected systems. All training focuseson “hands-on” diagnosis and theoptimization of production needs.

� Production

Customized maintenance programs atvarious levels are available to coverspecific and unique needs, like 24/7support contracts or global inventorymanagement. The highly qualifiedUnaxis support engineers and servicespecialists are ready to advise both in person or at the other end of anemergency hotline. Increased regionalpresence and parts depots also allowUnaxis a rapid parts delivery.

Proven performance

Measuring our performance is a centralrequirement for a functioning serviceorganization. Service cycle times aremeasured and monitored and thecomplete downtime history is registered.This gives both Unaxis and our customersa fully transparent measurement of the process and a basis for review andcontinuous improvement.

This superior service and maintenancepackage will set the benchmark for further improvements in Global KeyAccount Management. Unaxis customerscan rely on highly competent partnershipsat all levels.


Quality Service – Quantity Yield

In September 2001, Unaxis Semiconductors’ Sales and Servicedepartments were joined into one organizational unit. Our vision was toprovide a superior level of customer care – worldwide. February 2003 marks the rollout of our new global Customer Support Package, designed to maximize our customers’ productivity and reduce cost of ownership.

Unaxis Insights

Ralf Kuhlmann,

International Sales

and Market Manager,

Unaxis

Semiconductors

Superior

Extended

Basic

Warranty

Post-warrantyWarrantyTime

Service coverage

Service packages

4 | Chip Unaxis

Unaxis Insights

The ceremony started at 2 p.m. with the traditional lion dance. In addition to local employees, our key customers,Shanghai government officials, the Swiss General Consul in Shanghai, and Unaxis management were all invitedto join this celebration. After HeinzKundert, Unaxis CEO, painted the lion’s eyes to “bring it to life”, and cut the ribbon, the regional headquarter was officially in operation, housing salesand service teams and a Unaxis Opticsproduction facility.

Unaxis has a long and successfulhistory in Asia. The initial operation inHong Kong can be traced back to the1980s. Unaxis Taiwan, established in1996, has grown rapidly into a unit with100 employees. Unaxis has alreadyprovided the Chinese Market for manyyears with its innovative solutions. Now China has become the secondlargest producer of electronic goods in the world, and – especially after it joinedthe WTO (World Trade Organization) –many of our customers have investedhere. To stay close to our customers,Unaxis announced the Greater Chinaorganization in April 2002, followed by the establishment of a flagship legal entity in Shanghai. Like Mr. Kundert stated in his welcome speech, “… thedevelopment and building of ourheadquarters here is not where it ends.This is just the beginning. We are fullycommitted to supporting and sharing inChina’s growth and development.”

To integrate the resources and share the knowledge, the Greater ChinaSemiconductors team took theopportunity of the inaugurationcelebrations to gather in Shanghai for the first Greater China Strategy Meeting.Team members shared their experiencesof the first fruitful year under the newstructure. Unaxis’ cost effective systemshave gained an excellent reputation in the fields of Advanced Silicon, Advanced Packaging and CompoundSemiconductors. Looking into 2003, ourbusiness is estimated to grow another10% in the Greater China area.

We at Unaxis have always valued our customers as partners. While we are committed to our long standingpartnerships, we expect to build new,equally successful and lasting ones. The single Unaxis Greater China structureis a further step towards providing thebest service and support for both existingand potential customers.

For more information please [email protected]

Unaxis Shanghai Has Opened it’s Doors!Drums clattered! Lions roared! The festival rattle declared the inauguration ceremony of Unaxis Shanghai, the new regional headquartersfor Greater China in the Waigaoquio Free Trade Zone, on Dec. 6th, 2002.

Unaxis Insights

Dr. Gordon Shyu, Vice President,

Unaxis Greater China,

Ling-ying Weng, Marketing Communication

Supervisor, Unaxis Greater China

Dr. Martin Bader

with the Unaxis

Semiconductors

Greater China team

FeatureWithin the past ten years China has gone

from producing low end calculator andtelevision chipsets to inspiring industryexperts, such as Craig Addison, a regularcontributor to Semiconductor Magazine,to predict that “within 10 years mainlandChina will produce almost all of the world’scommodity semiconductors”.

China has reached a critical mass inresources, technology and productionskills, say experts. It has a supply chainfalling into place and now looks like it willbe a major, if not the major, volumesemiconductor manufacturing siteworldwide within the next 10 years.

The key message seems to be after along struggle and many joint technologyand production contracts with technologyleaders, the country has the foundation toproduce semiconductors on a large scale.

The flamboyant technology guru,George Gilder, goes further than others,writing “within two years, China willcommand more advanced, more diversemicrochip manufacturing capabilities than the US does.”

The reason people believe the chipindustry will be big in China is its trackrecord with other technologies. A numberof high tech manufacturing businesseshave already made significant shifts toChina, including printed circuit boards,motherboards, monitors, scanners, CD and DVD-ROMs, and desktop PCs.Experts say that China leapfroggedTaiwan in the manufacturing of IT goodsfor the first time in 2000, when thePeople’s Republic ranked third in theworld behind the United States and Japan.

Growth in the China market

Merrill Lynch says China is Asia’s strongest and steadiest economy. It is this growth when many other countries are experiencing minimum or evennegative growth which is attractingequipment vendors from around the worldas they face diminished opportunities intheir traditional markets due to recession.

For the past few years, China hasposted a reported annual GDP growth

rate of about 8 percent. Its neighbors’growth rates have been more volatile.

China’s semiconductor marketaccounts for 6 per cent of worldwidedemand, making it the largest after theUnited States, Japan and Taiwan.Nevertheless, it only produces 1 out ofevery 4 chips it consumes, say experts.

Reviewing China’s IC manufacturinghistory, Sunday Huang from the newUnaxis Shanghai office, points out China is still considered an emerging semiconductor market.

One reason for hoping it will soondevelop into a hot market for capitalequipment suppliers is the lag betweenChina’s cutting edge and the world’s isdecreasing, Huang points out.

In 1994, SGNEC developed a 6"production line, eight years behind the first 6" line installed outside the country,according to Huang. The same occurredin 1999, when Infineon and Mortorolasucceeded in the cooperation of the first12" line, while China ran its first 8" line.China’s first 12" line is scheduled to be

The People’sRepublic of Chips

China is pegged as one of the fastest growing markets for semiconductors, asforeign firms move foundry and supply chain businesses to the People’s Republicto serve the domestic market, as well as produce chips for export.

“For many years China

has been forecast

to be a growing market,

now this appears to be

a reality.”

Benjamin Loh,

President Unaxis Greater China

Feature

Valerie Thomson,

Technical Journalist, Zurich

6 | Chip Unaxis

Feature

installed by the Shanghai-based foundry,Semiconductor Manufacturing InternationalCorp (SMIC), in its new Beijing foundry.

Huang makes a comparison based on processes and also sees a reduction in the time lag between China and the rest of the world. For processes between1.5 µm and 0.5 µm, China was 8 to 10 years behind the rest of the world. In 2002, SMIC, announced the release of VeriSilicon’s Standard Design Platformfor its 0.18 µm CMOS process, whichbrings the lag down to three years.

Falling barriers

Investments in Chinese suppliers haveincreased in the past years, a sign that one of the most significant barriers tosemiconductor trade are falling. Manyinternational semiconductor andelectronics manufacturers have invested in Chinese factories and chip-relatedbusinesses (Table 1).

In addition to supporting foundry build-outs semiconductor manufacturingequipment makers are strengthening their presence in the China market. BesidesUnaxis, many large equipment supplierslike Applied Materials and TEL haveestablished a sales and service office inShanghai. Unaxis first established a localoffice in 1995 in Shanghai, and has nowexpanded its operation into the ShanghaiWaigaoqiao Free Trade Zone in 2001.

Taiwan factor

Companies worldwide, especially fromTaiwan, are planning to build fabs inShanghai or Beijing. Six new 200 mm 0.25 µm fabs are planned or underconstruction (Table 2).

Taiwan is following Japan in moving chipmanufacturing to China. Two open chip

foundries, Semiconductor ManufacturingCompany International (SMIC) and Grace Semiconductor ManufacturingCorporation (GSMC) are pioneers in the advanced open-IC industry.

SMIC began pilot productions inSeptember 2001, offering 8" processingcapability with 0.25 to 0.18 µm technologytransferred by partners in the US andJapan.

Now UMC is aiming to enter China’sgrowing semiconductor market, as is its competitor chip maker TaiwanSemiconductor Manufacturing Co. Ltd.(TSMC). Applications have been filed tosecure Taiwanese government approval for plans to build an 8" wafer fabricationfacility in Shanghai. Once TSMC getsapproval from the Taiwanese government,the company will establish a wholly-ownedsubsidiary, TSMC Shanghai Corp, in China.

The availability of engineers, labor, and real estate, plus a fast-growinginternal market, and a government which is increasingly friendly towards businessare helping to drive investment.

The lowest production costs in theworld are also contributing to the buddingchip industry there.

The right policies

Local experts say the country has the rightpolicies in place to support semiconductormanufacturing on a large scale. Governmentmeasures include fiscal policies, such asexemptions from paying income tax.

“Chip manufacturers with investmentsover 8 billion USD or technology below0.25 µm, are usually exempt from taxes forfive years after they break even, and theypay only 50% of the regular tax rate in the subsequent 5 years”, according toMontgomery Research’s Future Fab

magazine (Vol 13 August 2002). In addition,the normal value-added tax is to bereduced from 17 percent to 6 percent forsemiconductors sold domestically.

The Chinese government also offersduty-free and import VAT-free treatment formaterial, instruments and equipmentrequired by fabs, and local governmentsoffer a variety of incentives such asdiscounts on land prices, financial support,the provision of loans as subsidized interestrates, according to the Future Fab’s report.

Another sign China sees growth in thesemiconductor arena is that the president’sson, Jiang Mianheng, has invested in a foundry, along with other investors. The country also has one of its detailed “ten year plans” in place meant to developthe chip industry.

Supply chain phenomenon

The supply chain to support an indigenoussemiconductor industry is falling into place.

Figure 2: Time lag for

semiconductors discrete

devices in China

compared to world

SSI

(SmallScale IC)

MSI LSI VLSI ULSI

1955

1960

1965

1970

1975

1980

1985

1990

1995

2000

Source: Unaxis

ChinaWorld

Figure 1: Time lag for

ICs in China compared

to the rest of the world

Ge Alloy

transinstor

Si Alloy

transistor

Plan

diffused Si

transistor

Si MOSFET GaAs

device

1945

1950

1955

1960

1965

1970

ChinaWorld

Source: Unaxis

Feature

Japanese firms such as Sony, Nintendo,Sanyo Electric and Mitsubishi Electric havemoved assembly as well as manufacturingof electronics products to the Chinesemainland.

Labor costs which are one twentieth toone thirtieth of Japanese costs are a driver.According to a report in SemiconductorMagazine (Vol 3. No.4), China is acompelling location for new chip foundriesbecause it helps the Japanese to competewith Taiwanese and Korean manufacturers.

Chip manufacturers, such as MatsushitaElectric, which already has a high-end LSIfacility in Shanghai producing system chipsfor mobile phones, and Hitachi havefollowed suit.

NEC has a 6" MOS wafer fab and an 8" fab, while Toshiba LSI System SupportCo. has a design lab in Shanghai whichemploys 30 to 40 engineers. Toshiba plansto increase this to 1,000 employees by2003. Similarly, Mitsubishi Electric intendsto increase its current 35 engineers inBeijing to as many as 300 over the nextseveral years.

The same goes for Matsushita, whichplans to raise the number of engineers at itsBeijing design center from the current 100to 1,500 by 2005.

8 | Chip Unaxis

Feature

MOTOROLA To invest $10 billion in China during the comingfive years at the same time it retreats from otherlocations

ERICSSON Plans a $5 billion investment plan for China overthe coming five years

NOKIA Is implementing a $1.2 billion project called the“Star Net Park” in Beijing

DELL Moved manufacturing operations fromSoutheast Asia to China

Invested about $500 million over the last fiveyears in its Chinese production facilities

National Testing and assembly factoriesSemiconductor

Fairchild Semi Testing and assembly factories

Infineon SMIC to make standard memory chips. The jointventure, financial details were not released,means Infineon will transfer its 140 nanometerDRAM trench technology to the Chinese firm,and will do the same with its 110 nanometertechnology.

Oki Electric Established a sales company in Shanghai toIndustry Co market Oki's semiconductor products, in

particular system LSIs, to local Chinesecompanies. Also to provide chips to Oki'sexisting customers which have shifted or intendto shift their production from Japan to theChinese market.

ALCATEL Moved its Asia Pacific headquarters fromAustralia to Shanghai

China is a magnet for electronics investment

Table 1: Electronics

giants such as

Motorola, Hitachi,

Nokia, and Dell

invest in China

Source: Unaxis

Feature

Table 2: Systems

and sub-systems

manufacturers have

already migrated to

China. Now China

is ready to add IC

production as well.

Valerie Thompson

MSc., has been a freelance business and high-tech writer for more than 10 years. A Canadian based in Zurich, she tracks the trends and developments of Europe’s purveyors of advancedtechnology.

58 Major packaging &testing companies

250 Design companies

4 200 mm wafer fabs

12 Assembly and testfacilities built by Intel, IBM, Philips,Fairchild, Samsung,Mitsubishi Stone,Amkor, GemServices, and Taiwan Inc./ASE,Siliconware.Cumulativeinvestmentsbetween ’01 and ’05 will be more than $1.2 billion

Number of Supply chain

businesses segment

The supply chain is in place

for an indigenous Chinese

semiconductor market

Advanced Silicon

10 | Chip Unaxis

SiGe Milestones

The history of germanium is as long as the history of integrated circuits. Some of the first ICs used germanium. In 1948,Bill Schockley, one of the inventors of thetransistor, suggested Ge heterojunctionsin his original patent.

Just a few years later Kroemer tried to build a SiGe HBT. Shortly theirafter, IBM began its work in SiGe. Its firstbreakthrough was in 1987. The upside of the discovery was the cost structureand economies of scale are similar to silicon-wafer processing, but the downside was an increase in manufacturing complexity and it took

almost another ten years to overcome that hurdle.

In 1996, it qualified the world’s firstmanufacturable SiGe HBT process. Since then its goal has been to show silicon with germanium can achieve the high-frequency performance of any III-V chip and more.

IBM promotes both its processes,tooling, and SiGe know-how, including the Unaxis UHV-CVD epitaxy system. “It is the only UHV-CVD non-selectivetechnique which enables the growth ofdevice quality layers at low temperature to allow almost arbitrary composition”,says Harame.

The first commercial applications ofSiGe were power amplifiers and RF analogapplications in the nineties. Today it isshowing up in optical networking chips,measurement tools, wireless, high-speedlocal area networks, and globalpositioning chips.

SiGe is compatible with CMOSprocesses and intellectual property,enabling more leverage of existing know-how (Figure 1). This compatibilitywith CMOS enables SiGe to really breakthe cost barriers.

SiGe BiCMOS sales totaled $320 million in 2001. Of that total, 80%was made by IBM and used Unaxistooling. In addition, IBM holds 80% of the $600 million a year global market for early SiGe transistors.

The SiGe market is projected to grow to $2.7 billion by 2006 according to the“2002 McClean Report”, published byresearch firm IC InsightsToday.

Performance

The fastest circuit in any technology is aSiGe HBT Ring Oscillator. It can even beatInP with 55% less power and 15% lowerswing (Figure 2).

There is no further reason to use III-Vnow that SiGe has matured. It is no longertrue to say III-V has the fastest circuits –SiGe is easily as fast as III-V. A SiGe HBT

SiGe – a Basic Material for Silicon Technology

“SiGe BiCMOS technology is mature and here to stay”, says David Harame, Distinguished Engineer, IBM. He has been circling the globe for the past few years demonstrating SiGe is ready to become a part of the CMOS universe. It is a robust, highperformance, cost effective way to fulfill the demands of the CMOS roadmap, which is based on Moore’s Law.

Advanced Silicon

Figure 1:

The compatibility

with CMOS enables

SiGe to break cost

barriers

Dr. David Harame, Director RF/Analog

and Mixed Signal, Semiconductor

Research Development Center,

Microelectronics Division, IBM

Based on a talk at last November's

technology workshop on SiGe at

Unaxis headquarters

“Base-after-gate” integration flow� Major thermal cycles prior to base deposition� Low thermal-cycle HBT module

CMOS/common

Bipolar/analog

Shallow trench isolation

FET well implantsDual gate oxide & gate formationLDD implants & annealsSpacer formation

nFET S/D/G implantspFET S/D/G implants

Source/drain and emitter annealSilicide contactsStandard 2 to 6 metal layers– includes MIM capacitor

Subcollector & n-EPIDeep trench isolation

Collector plug implant

HBT module:– Bipolar window open– SiGe Epi base growth– Extrinsic base, collector

& emitter formation

Thick metal add-on module

Unaxis Chip | 11

also has the fastest dynamic frequencydivider in any technology (Figure 3). SiGefrequency output continues to improve.Alternatively, frequency can be a trade-offfor power gains.

The potential for integration in SiGe istremendous. Harame shows a referencedesign belonging to an anonymous IBMcustomer who is using the IBM 0.18 micronSiGe BiCMOS process for a wireless chipthat includes 6,000 HBTs, 7 million CMOStransistors, a noise isolation technologyand a host of capacitors. “It is our mostcomplicated chip with an RF analogsystem-on-chip that operates at 2 GHz”,asserts Harame.

IBM has selected the Unaxis SiGeepitaxy because it is a mature technologywhich has been manufactured since 1996.Its UHV-CVD non-selective techniquegrows device quality layers. The defectsare very low, with few failures. “In fact, itdoesn’t get any better!” exclaims Harame.

Now IBM is making a “smart investment”in bandgap engineering as a result ofusing Unaxis process tools. IBM hasselected the Unaxis SIRIUS® as the “toolof choice” because the equipment hasbeen tested and is fully functional.

CMOS roadmap in trouble

There are a couple of ways to achieve the continuous improved processingpower and cost advantages that Moore’sLaw demands. Scaling is one of them.Scaling means to continuously shrink thesize of integrated circuits, increasing thenumber of transistors in a sliver of siliconwhile increasing the size of the wafers they are processed on. This has workedwell in the past, but scaling is leading to an almost unmanageable level ofcomplexity.

Not only is complexity increasing butthe industry is reaching its physical limitsas oxide thicknesses shrink to only a fewatomic layers of thickness (Figure 4).

The leveling of scaling power also has to do with costs. The capital expendituresrequired to achieve these increments isbecoming prohibitively expensive. A new fab has a price tag of $2 to 3 billionattached to it these days.

An alternative to scaling to achieveperformance gains and fulfill the demandsof Moore’s Law is to use advancedmaterials processes, such as compoundsemiconductors which boostperformance because of their physical

Advanced Silicon

Figure 4: Oxide

thickness is reaching

a few atomic layers

Figure 2: SiGe ring

oscillator beats the

speed records

Figure 3: Fastest

divider in any

technology

“SiGe is a breakthrough technology andalready very important for the semiconductorindustry. I believe it will become even more so over the next five years because it providesthe industry with the means to carry outMoore's Law”.

Dr. David Harame

12 | Chip Unaxis

properties (e.g. SiGe’s molecular structureenables electrons to pass across thecircuits faster, plus the signals gain energybetter than Si alone).

Implicit to Moore’s Law is that it featuresperformance benefits, and innovations do not cost more than the market is willingto bear. An economy of scale must be inplace. For the past 30 years, transistorscaling has been enabling the leap everyeighteen months without significantchanges in the CMOS manufacturingprocess as demanded by the industryroadmap.

However, the economics of CMOSscaling are no longer valid. Gross margins are narrowing at the same time as capital expenditures required to buildour next-generation fabs is climbingdramatically.

Strained silicon provides a path. “I suggest that strained silicon CMOS isthe answer to the limits described,” saysHarame. It has been shown that pullingsilicon crystals apart or straining thesilicon enables electrons to movethroughout the circuits much faster. It improves electron flow by 70% and chip performance by 35%.

A few issues remain to be overcome for the use of strained silicon – once wafer costs are addressed, the nextconsideration for this technology is theease of fabrication of strained Si devicesand circuits.

Such chips are manufacturable today,however the straining process doesintroduce defects. There is still much to beunderstood about relaxation mechanismsand control dislocation densities andsurface morphology.


Advanced Silicon

Vendor Product

Envara LAN chips

New Focus Inc.'s 3.5 GHz optical-to-electrical (O/E) converter

Zarlink Single-Chip radio transceiver for TDMA/AMPSdigital cellular networks

Atmel and u-blox GPS chipset in SiGe HBT

Motorola One chip integrated GPS device

Maxim Integrated Linear power amplifiers for 5 GHzProducts wireless-LAN applications

Narad Networks Analog signal processor quintuples coaxialcable bandwidth

Big Bear Networks PSP products, including 10 Gigabitsubassemblies and transponders and 40 Gigabittransponders for cross-office, metro core/inter-office facility and long-haul transmission.

Sirenza Family of SiGe active receive mixers ideally suitedMicrodevices to 2 G, 2.5 G, 3 G, WLAN, and fixed-wireless

infrastructure applications.

Source: Unaxis

Recent SiGe product announcements

Dr. David Harame

David Harame received his PhD in Electrical Engineeingfrom Stanford University in1984. He joined IBM in 1984 at the T. J. Watson ResearchCenter in Yorktown Heights,New York, where he immediatelybegan working using epitaxialgrowth techniques in silicontechnology to improve deviceperformance. He worked onboth SiGe HeterojunctionBipolar Transistors (HBTs) andSiGe Channel FETs. Dr. Haramewas involved with the SiGe HBT work at IBM from itsinception and is widely creditedfor taking the technology fromresearch to manufacturing. He developed and qualified the first manufacturing SiGeHBT process in the AdvancedSemiconductor TechnologyCenter in Hopewell Junction,NY. He then worked on BiCMOSand moved to Essex Junction,Vermont, where he developedthe first fully manufacturingqualified SiGe BiCMOS processin a large-volume fabricator. Dr. Harame now lives in EssexJunction, Vermont, where hedirects IBM’s SemiconductorResearch Development Center,Microelectronic Division,RF/Analog and Mixed SignalTechnology Area. This areadevelops both RF-CMOS- andSiGe-BICMOS-technologiesand provides models and design kits for RF/Analogenablement. Dr. Harame hasauthored/co-authored over 130 technical articles and holds16 patents. He is a seniormember of the IEEE, anexecutive committee member of the IEEE Bipolar BiCMOSCircuits and Technologycommittee, and a member of the Compact Model Council.Dr. Harame is a DistinguishedEngineer of the IBMCorporation.

To make chips with similar features and performance to GaAs

or other expensive compound semiconductor processes requires

an investment of $2.5 billion whereas bandgap engineering

exploits existing CMOS processes with the addition of just one

extra process tool, resulting in a total investment $2.5 million.

Unaxis Chip | 13

Advanced Silicon

Advanced Silicon

The performance of silicon-based high-speed bipolar transistors has greatlyimproved over the last few years. Recently,a transistor with a record cut-off frequencyof 210 GHz was presented by IBM [1]. The basis of this technology is anepitaxially grown SiGe base, making itpossible to engineer the band gap andachieve a narrower base than ever before.The inevitable boron out-diffusion from the base layer can be minimized by theaddition of carbon.

Because of its relative simplicity, non-selective epitaxy is commonly used for this type of device. One drawback is thesubsequent non-self-aligned patterning of the layers necessary to build up theemitter and the connections to the base[1, 2 ]. So far, only a rather complicatedprocess flow has been demonstrated,which includes conversion of poly-Si tooxide for the manufacture of self-alignedtransistors from a non-selective epitaxiallygrown base [3].

Another approach starts with aselectively grown base layer in the emitterwindow [4]. However, selective epitaxy is known to suffer from severe loadingeffects. This means the epitaxialparameters will need to be tuned for eachlayout with a different device density.Moreover, the selective process is verydifficult to control, which easily leads tovoids and poor base contacts.

A common problem in all self-aligneddouble-poly processes is related to thesubsequent removal of the silicon used for the extrinsic base inside the emitteropening without etching down into theunderlying monocrystalline silicon. Thisbecomes more severe for a processinvolving an epitaxial base: since the baselayer is formed prior to the emitter windowetch as opposed to a process where the base formed by ion implantationthrough the etched emitter opening. Many solutions have been suggested in literature. In the case of SiGe-basednon-selective epitaxy, the etching problem has recently been addressed [5].Here, a boron silicate glass (BSG) layerwas used both as an etch stop and as adiffusion source for the electrical link-upbetween the external and the internalparts of the base.

This article is based on a recentlypresented conference paper [6]. All SiGe-depositions have been performed in aUnaxis SIRIUS® UHV-CVD system. Themodular concept used for the extrinsicbase can also be applied to a moreconventional double-poly bipolar processflow which uses an implanted base.

Device manufacture

The fabrication of the device follows anearlier process scheme up to theformation of the collector contact [7]. A nitride and silicon seed layer are thendeposited and patterned prior to a non-selective SiGe:C epitaxy of theintrinsic base. This is followed by thedeposition of a bi-layer of poly-SiGe andpoly-Si for the extrinsic base layer. Beforethe deposition of an oxide, the extrinsicbase region is implanted with a high doseof boron. The implanted boron will later beout-diffused, thereby forming the extrinsicbase connection. The stack is thenpatterned and etched to form the emitterwindow. Subsequent processing follows aconventional double-poly bipolar processflow. A schematic cross-section of theresulting transistor is shown in Figure 1.

Intrinsic base module details

The intrinsic base was grown in a Unaxis SIRIUS™ UHV-CVD system. The depositions were made at a working

High-PerformanceBipolar Transistorswith SiGe:C and Poly-SiGe

Dr. Johan Pejnefors, Scientist, Dept. of Microelectronics and

Information Technology, Royal Institute of Technology, SE-164 40 KISTA, Sweden.

Dr. Ted Johansson, Expert RF Transistor and Process Design,

Ericsson Microelectronics, SE-164 81 KISTA, Sweden (*)

The successful use of poly-SiGe as the extrinsic baselayer in a self-aligned process with non-selective epitaxyof SiGe:C for the intrinsic base. STI

DTI

Intrinsic base

Extrinsic base Poly-SiGe (30%)Non-selective epitaxy

C

EB

p

n+

nn+

n–

p+p+

n+

Figure 1: Schematic

cross-section of the

fabricated device

(*) Current address:Infineon Technologies Wireless Solutions Sweden AB,SE-164 81 Kista, Sweden.

14 | Chip Unaxis

Advanced Silicon

planar surface compared to that of the polycrystalline film on the field area.Furthermore, as a consequence of ahigher epitaxial growth rate, thecommonly observed shrinkage of theactive area – due to a polycrystalline over-growth during non-selective epitaxyin RP-CVD reactors – was found to beessentially absent when the film is grownunder UHV-CVD conditions.

Extrinsic base module details

After the intrinsic base was grown, poly-SiGe with about 30% Ge was deposited atlow-temperature in the UHV-CVD system.The deposition started with a thin Si seedlayer in order to facilitate the nucleation of the subsequent poly-SiGe film. Then a 500 Å thick poly-SiGe film with 30% Gewas deposited and capped with a thin Si layer. AFM analysis of the poly-SiGe filmshowed the surface roughness was about60 Å in the active and the field areas. The extrinsic base was completed by thedeposition of a 600 Å thick poly-Si filmusing an ordinary LP-CVD furnace.Subsequently, the poly-Si layer wasimplanted with 2x1015 cm–3 of BF2 at 35 keV.Finally, the extrinsic base stack wascovered by a deposited oxide layer.

The emitter window was opened by dryetching of the isolation oxide, followed byan etch of the poly-Si and poly-SiGe layersusing an HBr/Cl2 based chemistry. Usingthe system monochromator, the 3040 Åemission line from the etch plasma wasused to indicate the location of theinterface between poly-Si and poly-SiGe.The endpoint of the etch was triggered by the signal reaching maximum intensity.Timed etching was then used to etchthrough the poly-SiGe layer, stopping atthe underlying Si epitaxial layer.

An XSEM (cross-sectional scanningelectron micrograph) of the emitteropening after the timed poly-SiGe etch isshown in Figure 3. The uniformity of theextrinsic base etch across the wafer wasfound to be excellent and no loadingeffects could be detected.

Figure 4 shows a cross-section of thetransistor after completed processing.

Figure 2: XTEM of

the non-selective

epitaxy

Figure 3: XSEM of the

emitter window after

a timed etch of the

poly-SiGe film

Figure 4: XSEM of

the transistor after

HF treatment as

recorded in the

backscattered mode

pressure of approximately 1 mTorr and a temperature of about 550°C. SIMS (Secondary Ion Mass Spectroscopy)analysis showed the oxygen concentration in the epitaxial films to be lower than 1x1018 cm–3. The epitaxiallayer consists of five different sub layers,which were grown in an uninterruptedsequence. Closest to the substrate is anundoped Si buffer layer, followed by anintrinsic SiGe layer with a Ge concen-tration of approximately 12%. Thenfollows a SiGe layer with 5% Ge, which is boron-doped to 1x1019 cm–3. Carbon, at about 0.2% was added to the boron-doped layer in order to minimize boronout-diffusion during the subsequentdevice processing in order to keep theintrinsic base narrow. Next follows a SiGelayer with 5% Ge and boron concentrationof 4x1018 cm–3. The final layer is a Si caplayer with 4x1018 cm–3 boron.

An XTEM (cross-sectional transmissionelectron micrograph) of the non-selectiveepitaxial layer is shown in Figure 2.The higher epitaxial growth rate in theactive area has resulted in an almost

Unaxis Chip | 15

Advanced Silicon

Tungsten plugs and SiGe films are seen as bright layers. It has been reported theoxidation rate of SiGe is enhanced by afactor of three compared to Si, and thatGe segregates to the interface of thegrowing oxide [8]. However, the poly-Silayer which covered our poly-SiGe filmprotected the latter from oxidation duringthe densification of a sacrificial oxide layeron the base.

The poly-Si covering the poly-SiGe layer also facilitated the titanium self-aligned silicide process in themetallization step; the poly-Si was thickenough to prevent the formation of athermally unstable germano-silicide. No difference in sheet resistance wasobserved between a standard Ti silicidation of Si and the silicided poly-Si/poly-SiGe film stack.

Electrical measurements

The current quality of the manufacturedtransistors is demonstrated in Figure 5,which shows a Gummel plot for a single

transistor with an emitter area of 0.4x10 µm2 at a base-collector voltage of 0.1 V. The collector currents displayideal characteristics which indicate thatthe epitaxial base layer is dislocation free. The relatively low collector saturationcurrent, extracted from the singletransistor, is due to an out-diffusion ofboron from the SiGe layer into the Sisubstrate. For the single transistor, thebase current is ideal over several decadesof current. A peak value of about 100 canbe extracted for the current gain. Figure 6shows the extraction of fT = 53 GHz andfmax = 80 GHz for a single device. Althoughfmax is considerably higher than fT, whichindicates a good extrinsic base formation,the fT can be increased further byoptimization of the base-collector region.


Figure 5: Gummel

plot for a single

transistor with an

emitter area of

0.4 x10 um2

Figure 6: Extraction

of fT and fMAX for a

fabricated device

Ted Johansson

is a specialist on RFtransistor and processdesign at EricssonMicroelectronics (nowInfineon TechnologiesWireless Solutions AB),in Kista, Sweden. He spent several yearsdeveloping high-powertransistors for basestation transmitters and now devotes most of his time tovarious advancedsemiconductor processdevelopments forwireless applications.He joined Ericsson in 1989 and holds a Ph.D. in ElectronicDevices from LinköpingInstitute of Technology,Sweden. He haspublished around 40journal and conferencepapers, and holds morethan 20 patents.

Johan Pejnefors

received an M.Sc. in Physics of Materialsfrom Uppsala University,Sweden, in 1996 and a Ph.D. from the RoyalInstitute of Technology(KTH), Stockholm,Sweden, in 2001. His doctoral researchconcerned CVD of Si and SiGe for high-speed bipolartransistors. Since 2001, he has been workingwith integration of aSiGe:C base in a projecttogether with EricssonMicroelectronics (nowInfineon TechnologiesWireless Solutions AB) in Kista, Sweden.

0.3 0.5 0.7 0.9 1.1 1.3Base-Emitter voltage [V]

Bas

e or

col

lect

or c

urre

nt [A

]

1.E–10

1.E–08

1.E–06

1.E–04

1.E–02 IC [A]IB [A]

Frequency [GHz]

Sm

all s

igna

l cur

rent

gai

n (h

21),

and

unila

tera

l pow

er g

ain

(U) [

dB

]

45

40

35

30

25

20

15

10

5

00.1 1 10 100

Uh21

Vce = 3V

We = 0.4 µm Le = 10 µm

Acknowledgements

This work is financially supported by the SwedishAgency for Innovation Systems (VINNOVA) and ispart of the MEDEA+ T204 Program ASGBT.

References

1 S. J. Jeng et al., IEEE Electron. Device Lett., vol. 22, Nov. 2001, pp. 542–544

2 H. Baudry et al., Proc. BCTM, 2001, pp. 52–553 C. A. King et al., IEDM Tech. Dig., 1999,

pp. 565–5684 D. L. Harame et al., IEEE Trans. Electron.

Devices, vol. 42, 1995, pp. 469–4825 F. S. Johnson et al., Proc. BCTM, 2001,

pp. 56–596 J. Pejnefors et al., ESSDERC 2002, Firenze,

Italy, Sep. 24– 26, 20027 M. Forsberg et al., Proc. 30th ESSDERC, 2000,

pp. 212–2158 F. K. LeGoues et al., Proc. Mat. Res Soc.,

vol. 105, 1988, pp. 313–318

16 | Chip Unaxis

Advanced Silicon

Joint development projects offer anexcellent opportunity for a betterunderstanding of customer and marketneeds, and for bringing together processknow-how and research experience.

The Unaxis SiGe team is involved inseveral joint development projects in bothSiGe market segments: the SiGe HBT(hetero bipolar transistor) market, and thefuture hetero CMOS market (virtualsubstrates for strained silicon).

Carbon doped SiGe for high

performing HBT

Carbon incorporation into SiGe structureshas become more and more common, andvery good results have been achieved interms of maximum frequency of thedevices. The carbon in the SiGe alloycompensates lattice constant differencesbetween silicon and germanium. But moreimportantly, it improves the stability ofboron and supresses boron diffusion,especially when high temperature stepsare following in the process sequence (seealso p. 13 in this edition of Chip).

SiGe for CMOS – a challenge for

process and equipment

In order to realize strained silicon layers,typically a thick buffer layer is needed,consisting of a Si layer with gradedgermanium content followed by a layerwith constant SiGe composition.

To enable high quality/low cost growthof such layers, new processes need to bedeveloped – the new CLUSTERLINE® LEPwith its LEPECVD process intends to fulfillthis requirement. According to the ITRS2001 CMOS roadmap, the SiGe CMOS

market is expected to reach maturity in2004/2005 (Intel has recently announcedit will have products based on strainedSilicon ready in 2003, therefore this datemight shift forward). Together with severalpartners, Unaxis has initiated a number ofprojects to meet this challenge.

KTI projects

KTI projects are initiated by the SwissFederal Commission for TechnologyInnovation. Two of these projects supportUnaxis´ SiGe CMOS activities.

KTI-Project No. 4759.1 ran untilSeptember 2001 in cooperation with NTB(Interstate University of Applied Science,Buchs, Switzerland) and the FederalInstitute of Technology in Zurich. Objectives of this project were:� Checking UHV-CVD for SiGe CMOS� Comparing the UHV-CVD process

with LEPECVD� Developing virtual substrates grown

with LEPECVD� Processing of test p-MOSFETs with

LEPECVD grown SiGe layers

KTI-Project No. 6033.1 has been runningsince July 2002 in cooperation with NTB(Completion is scheduled for June 2003).Objectives are:� Development of low temperature

pre-epi cleaning and plasma enhanceddeposition of virtual buffers for SiGeCMOS

� Selection of suitable buffer for deviceproduction

ECOPRO-SiGe (G5RD-CT-2001-00558)

ECOPRO (Economical Production of SiGe Material for Microelectronics andOptoelectronics Applications) is financedby the European Commission. The

LEPECVD process is central to thisproject. It addresses the economicalproduction of SiGe virtual substrates forCMOS and the growth of optoelectronicmaterial (GaAs and other III-V) on siliconsubstrates.

Partners of Unaxis in this project are:ST Microelectronics, France, the NationalUniversity of Ireland in Cork, CentreNational de la Recherche Scientifique,France, Politecnico of Milan, Italy,University of Warwick in Coventry, UK, and Universität Linz, Austria.

This project commenced in August of2001 and is scheduled for a duration ofthree years.

LEPECVD 300 (IST-2001-38121)

In August 2002 a second EuropeanCommission supported project was started. This time with partners from the semiconductor industry: ST Microelectronics, France, Motorola,USA, Picogiga, France, Wacker Siltronic,Germany.

The objective is semiconductorequipment assessment (SEA). The UnaxisLEPECVD tool, the CLUSTERLINE® LEPwill demonstrate feasibility and suitabilityfor the production of graded SiGe bufferand pure germanium layers grown with high deposition rates at low cost. The capability of the system as a highthroughput, bridge-type cluster tool for200/300 mm wafers, must also be provenduring the project.

We would like to thank all partners for their excellent cooperation and lookforward to continuing these fruitfulrelationships in the future!


Advanced Silicon

Together We Succeed SiGe joint development projects

Dr. Martin Buschbeck, General Manager,

Dr. Jürgen Ramm, R&D Manager, Unaxis Semiconductors

Unaxis Chip | 17

Advanced Silicon

Advanced Silicon

In Chip 7 we demonstrated the high rate homo epitaxial growth of silicon bylow energy plasma enhancement at lowtemperatures (< 600°C). The processsequence for this application consists of only two steps: low energy plasmacleaning (LEPC) and low energy plasmaenhanced chemical vapor deposition(LEPECVD). In LEPC, the wafer surface is immersed in an intense hydrogenplasma in which the ion energies are kept below the sputtering threshold. It is important to control the ion energies in this pre-epi clean to avoid damages to the single crystalline wafer surface. A similar control of the ion energies isnecessary in LEPECVD to exclude defect

creation during epitaxial growth. We alsoapplied this short process sequence tothe growth of virtual substrates.

Virtual substrates (VS) and the

CMOS roadmap

The next generations of CMOS technologycan only be realized by the increase of theelectron and hole mobilities in transistors.This band gap engineering is based on the formation of strained silicon andsilicon/germanium layers. Strainedepitaxial layers are obtained by the growthof hetero epitaxial layers with a mismatchin the lattice constant. For a strainedsilicon channel, the silicon wafer first has tobe transformed into a silicon/germaniumsubstrate, called a virtual substrate. Inother words, the silicon wafer will continueto be the substrate for CMOS technology,but with a thin layer of single crystallineSiGe at its surface. This is achieved by the

growth of hetero eptaxial layers of SiGewith different germanium concentrations.The objective is to grow these layers with aquality (defect density, surface roughness)comparable to the bare silicon wafer.However, the strongly cost driven CMOSmarket – doubling the density oftransistors every 2 years – necessitateseconomical production of these VS.According to the CMOS technology roadmap, bulk VS are prospected for node 90 nm and 65 nm. To date the best qualityfor these bulk VS has been provided by a SiGe layer with a linear gradient of Ge (with about 10% increase in Geconcentration over 1 µm) to the desiredconcentration and finally covered by alayer of constant Ge concentration ofabout 0.5 µm (see also Chip 4, page 27). It seems obvious, that a high ratedeposition technology like LEPECVD is best suited for an economical growth of VS based on these thick layers.

Growth of VS on the LEPP 300

cluster tool

The VS deposition was performed in the 200/300 mm LEPP 300 cluster tool inthe Unaxis Semiconductors laboratory.The wafers were processed in the LEPC-LEPECVD process sequenceavoiding any additional treatment (e.g. wet chemical clean) before loading to the cluster tool. Prior to epitaxial growth, wafers were cleaned in hydrogenplasma for two minutes to removecontamination and the protective oxide(about 2 nm) from the wafer surface. Wafer temperature during this plasma

Low Energy Plasma Processing (III)

LEPP 300 – SiGe ProcessDevelopment Part II

Dr. Jürgen Ramm, R&D Manager, Advanced Silicon

Research Team: G. Chabanne, A. Erhart, Y. Goeggel,

M. Kummer, C. Rosenblad, S. Wiltsche, J. Ramm,


Figure 1: Germane

concentration in the

reactive gas flow

in comparison with

the germanium

concentration in

the deposited layer

The next generations of CMOS technology can only be realized

by increasing the electron and hole mobilities in transistors.

0

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0 0,5 1 1,5 2

Depth [µm]

Ge

rma

niu

m

co

nc

en

tra

tio

n

in t

he

la

ye

r

0

0.02

0.04

0.06

0.08

0.1

0.12

0.14

Ge

rma

ne

flo

w c

on

ce

ntr

ati

on

(Ge

H4/S

iH4+

Ge

H4)

Gas compositionas monitored

Filmcomposition

18 | Chip Unaxis

Advanced Silicon

cleaning step did not exceed 150°C, which is considerably lower compared to the 800°C – 900°C of the conventionalpre-epi bake in hydrogen.

Wafers were then transferred to theLEPECVD module, where deposition was initiated once the wafer was attemperature. In this example, a wafertemperature of 680°C and a depositionrate of about 5 nm/s were chosen. Figure 1 shows the ratio of the germanereactive gas flow over the total reactive gasflow during Ge ramping and constant Gegrowth. It is compared to the SIMS depthprofile of the germanium concentration for the resulting VS layer stack. The curvesare more or less indistinguishable, whichindicates a complete dissociation of theprecursors – a unique feature for epitaxialgrowth by CVD processes.

Characterization of the interface

of the VS

A damage-free pre-epi clean at lowtemperatures is a challenge for high qualityepitaxial growth. However, this process willbe necessary for future CMOS technology– not only for the economical production of bulk VS, but also for other applicationslike cleaning of the gate oxide before gate

contact deposition or the epitaxialdeposition of source and drain (elevatedsource-drain). Lowering thermal budget ofprocess steps will continue to be an issueduring further miniaturization in CMOStechnology. The shortest processsequence for the fabrication of VS is acombination of LEPC followed byLEPECVD. In Figure 2, the depth profilesobtained by secondary ion massspectrometry (SIMS) for oxygen, carbonand boron in an epilayer/wafer interfaceare shown for such a process sequence.Although there is additional potential toimprove the quality of LEPC, there is no or only little indication of interfacecontamination from this measurement.

Characterization of the VS

The benchmark for the quality of VS is thesilicon wafer. However, today VS qualitycannot compete in surface roughness and defect densities with silicon. Therelaxation during the growth of the VSresults in a cross-hatch pattern (misfit

dislocations) which increases the surfaceroughness. To reduce this surfaceroughness, a chemical mechanicalpolishing (CMP) is applied to the grownlayers to reduce the surface roughness.Among the different approaches tofabricating VS, the concept of the thicklinear graded relaxed buffer shows thebest results to date. The atomic forcemicroscope (AFM) picture of the VSsubstrate grown with a Ge concentrationof 14% (Figure1) is shown in Figure 3.The RMS value of the surface roughnessof this layer is 1.2 nm, which is equal or better than the values usually obtainedfor VS grown by competing growthtechnology like LPCVD. Besides the thick relaxed buffer concept there are alsoother approaches under investigation,which try to reduce the thickness of thebuffer and to reduce or avoid misfitdislocations. Also here, plasmaprocessing shows great potential.The next steps in process development arefocused on the improvement of the qualityof the VS for germanium concentrationsbetween 15% and 25%, and for 80% to 100%.


Figure 2: SIMS

depth profile of

an epilayer/wafer

interface (low

temperature silicon

growth at 680°C).

Before epitaxial

growth the wafer

surface was cleaned

by LEPC only.

Figure 3: AFM picture

of the surface of a

VS with an end

concentration of

14%. The VS was

prepared in a

two step plasma

process sequence

without additional

pre-treatment of

the wafers.

1.E+16

1.E+17

1.E+18

1.E+19

1.E+20

1.E+21

0 0.1 0.2 0.3 0.4 0.5

Depth [µm]

Co

nc

en

tra

tio

n [

cm

-3]

O C B

Epi-Si Substrate

Unaxis Chip | 19

Advanced Packaging

Advanced Semiconductor Engineering(ASE) Group is a global leader in providingsemiconductor backend manufacturingservices with more than 23,000employees worldwide. Since itsestablishment in 1984, ASE has alwaysbeen committed to providing customerswith complete solutions. The partnershipbetween ASE and Unaxis began in 1998when Unaxis started to provide ASE withUnder Bump Metallization and RDL(rerouting) sputter process tools such asthe CLUSTERLINE 200, and the LLS EVO.During that year, ASE invested inadvanced technologies such as bumpingand flip-chip substrate manufacturing. Inthe following year, ASE completed fourmajor acquisitions in the IC assembly, testand EMS (Electronic ManufacturingServices) areas. These expansions in

service offerings and presence led ASE tobecome the only backend turnkey solutionprovider with a truly global footprint.

As equipment technology advancedand 300mm wafer bumping became areality, the partnership bloomed with ASEand Unaxis’ active cooperation on thedevelopment of next generation flip-chiptechnology.

"Over the past five years, we have beenworking closely with Unaxis to provideprofessional and advanced semicon-ductor services to our customers. Unaxisis an extremely valuable working partnerand I am very pleased with their continuedefforts in providing us with excellentservice”, said Steve Fang, Director ofASE’s Bumping Line. "Unaxis not onlysells us equipment, it also provides a totalsolution which encompasses the entireprocess as well as both product andcustomer support”.

"Besides having to stay ahead insatisfying the continued demand forimproved electrical performance insemiconductor chips, we also face a greatchallenge in dealing with the increasingvariety of wafers required by our

customers. The application of flip-chiptechnology is emerging and, in closecooperation with Unaxis, we are able tostay abreast of the latest technologydevelopments and offer our customersaccess to production systems which meettheir requirements with both flexibility andefficiency”, Fang added.

"Similar to ASE, with operations strate-gically located at the world’s leadingsemiconductor manufacturing centers,Unaxis has a global infrastructure withlocal resources to support its customers”,said Fang. "In Asia, its presence in GreaterChina, Singapore, Japan, and Korea willprovide strong local support to itscustomers, which gives us an extra levelof confidence”.

Unaxis has been very glad to witnessASE’s growth. We are even more pleasedwe have had the opportunity to contributewith our expertise to ASE and operate as its working partner in providing turnkeysolutions.

For more information please [email protected]

Advanced Packaging

Unaxis and ASEPartnership for Improved Semiconductor Services

Dr. Gordon Shyu, Vice President Greater China,


Steve Fang, ASE

Engineering Center

Director (2nd from

left), and the Unaxis

Sales team (from left

to right): Julien Wu,

Kevin Chen and

Gordon Shyu

Turnkey services provided by ASE

Material

IC design Engineering Test

Wafer Manufacturing

WaferProbing

Final Test

DesignManufacturingService

AssemblyEngineering Test

IC design Wafer Manufacturing

WaferProbing

Final Test

DesignManufacturingService

Assembly

Material

"Unaxis’ total solution, including process and productsupport, helps US to achieve our goal of providing thehighest possible quality service to our customers”.

Steve Fang, ASE Engineering Center Director

Advanced Packaging

20 | Chip Unaxis

Advanced Packaging

In today’s electronic packaging world, flip-chip is a key technology to get asmaller package size and better electricalperformance, and to provide multi-chippackaging solutions for System-in-Package (SiP). An area array flip-chiprealizes over 1000 I/Os in one chip and the number is still increasing withtechnology development.

Another big trend in electronicpackaging is the “Pb-Free” movementtowards environmentally friendly products.This is driven not only by regulations on Pb usage but also by “Green Product”marketing competition. Already majorOEM companies such as IBM and Sonyannounced their plan to purchase Pb-Freeparts and products starting from themiddle of 2003. Flip-chip processes – eventhough they use only very small amounts

of Pb – would not be exempt fromregulations. Au, Cu, or electroless Nibumps with ACF (Anisotropic ConductiveFilm) /NCP (Non-Conductive Paste) wouldbe one way to realize Pb-free flip-chipinterconnection. However, these ACF/NCPmethods need very well defined chip andsubstrate conditions because thephysically bonded interconnect is verysensitive to adhesion between polymerlayers. So far, making a ‘chemical bonding’by reflowing solder bumps is accepted as a more robust interconnection forgeneral purpose IC packaging.

Pb-free bumping

In wafer level solder bumping two mainprocess categories are competing witheach other: solder paste stencil printingand electroplating.

Stencil printing is a good approach for a small ball size and low cost bumping.However, printed solder pastes, a mixtureof solder powders and flux, experiencesignificant volume change during thesolder reflow process. As a result relativelylarge spaces between solder bumps,usually over 150 µm, are necessary for the process.

Electroplated bumping is a goodapproach to meet fine pitch requirementsand cost effectiveness for high volumeproduction. Many in-house bumping linesand bumping service providers adoptedelectroplating for solder bumping massproduction. However, changing soldermaterials and UBM is not as easy with stencil printing. There have been technicalissues with plating of prominent binary and ternary Pb-free solder alloys. Majorelectrolyte providers and platingequipment companies are actively working in this field.

UBM

Under Bump Metallization, two to threemetal layers under the solder bump, is indispensable for reliable flip-chip interconnection. Figure 1 illustrates a cross-sectional flip-chip and UBMstructure, and Figure 2 shows an exampleof flip-chip failure. In many cases, flip-chipfailures appear in UBM neighboring sitessuch as chip/UBM and UBM/solderinterfaces. Therefore, understanding theinterface reactions between UBM andsolder and further controlling them toimprove the flip chip reliability are importanttasks. So, why not use the conventionalUBM systems of eutectic Pb/63Sn for Pb-free solder bumps? Figure 3 comparesthe cross-sectional images of eutecticPb/63Sn and Pb-free Sn/3.5Ag solderbumps after extreme 20 min reflow with four different UBM systems(TiW/Cu/electroplated Cu, Cr/CrCu/Cu,NiV/Cu, and TiW/NiV combinations).Compared to Pb/63Sn solder bumps, Pb-free Sn/3.5Ag solder bumps show athicker IMC (Intermetallic Compound) layerwhen TiW/Cu/electroplated Cu UBM isused. Even IMC spalling occurred from theinterface in case of Cr/CrCu/Cu andTiW/NiV. IMC spalling is a detachment ofIMC grains from the UBM/solder interfaceafter total UBM consumption by excessiveIMC growth. These images indicatechanging solder material from Pb/63Sn to high-Sn content Pb-free results in fastUBM consumption during reflow processeswhich leads to reliability degradation.

Sputtered NiV/Cu UBM

Interestingly, in the case of NiV/Cu UBM,the IMC spalling is not observed with bothsolders, as shown in Figure 3e and 3f.A cross-sectional TEM (Transmission

Under Bump Metallizationfor Pb-Free BumpingSe-Young Jang, Ph. D, Micro-Joining Lab.,

Mechatronics Center, Samsung Electronics Co. Ltd.

Heinz Gloor, Product Manager Unaxis Semiconductors

Si

Solder

PCBCu

UBM

Adhesion layerDiffusion barrier layerSolder wettable layer

Figure 1: Schematic

structure of flip-chip

interconnection

Figure 2: One

example of flip-chip

failure (UBM/solder

interface crack)

Unaxis Chip | 21

Advanced Packaging

Electron Microscopy) image of NiV/CuUBM and Sn/3.5Ag solder is shown inFigure 4. It can be clearly observed anunreacted NiV layer still exists underneaththe reacted Cu-Sn IMC layer. The mostplausible explanation for no IMC spalling in thin NiV/Cu UBM is, the underlying NiV layer provides a continuing IMC growth site even after the total Cu layerconsumption and slows down the IMC growth rate.

However, extreme multiple reflows over 15 times also result in total UBMconsumption and bump delamination.

Sputtered Ti(W)/Cu(or Ni)/

electroplated Ni UBM

In general, Ni is known to have a slower IMCgrowth rate than Cu with Sn containingsolder. For this reason UBM systems usinga Ni final layer are preferred for Pb-freesolder bumps to restrict excessive IMCgrowth. A very interesting phenomenon

about Ni UBM with Pb-free solder is eventhough only a very small amount of Cu iscontained in Pb-free solder (such as 0.5 ~ 1 wt.% Cu), the IMC phase formedbetween Ni and solder interface is normallyCu,Ni6Sn5, not Ni3Sn4 [1]. This is due to thelower free energy at formation of Cu,Ni6Sn5

than Ni3Sn4. This phenomenon results inless consumption of Ni UBM because IMCgrowth consumes Cu in the solder first, andthen consumes Ni UBM. Figure 5 showsthe Ni UBM consumption rate with variousPb-free solder materials. Sn/3.5Ag showsrapid Ni UBM consumption compared to Sn/0.7Cu and Sn/3.7Ag/0.5Cu. Itimplies the Ni UBM consumption rate isdramatically decreased with the addition ofa small amount of Cu to the solder bumps.

One concern about using electroplatedNi UBM is that normally Ni has higherinternal stress than other metal layers and possibly induces chip cratering orcracking.

What is the status?

It seems there are two main options inselecting a UBM system for Pb-freebumping. One can continuously use theconventional UBMs such as sputteredTiW/Cu/electroplated Cu and sputteredAl/NiV/Cu combinations. But strongrestrictions on following reflow conditionsare required to avoid excessive IMCgrowth. The other option is to enroll lowstress electroplated Ni on top of sputteredTiW/Cu, TiW/Ni or Cr/Cr-Cu/Cu. Somecompanies are using a stress bufferpolymer layer between UBM and chip padto reduce stress related issues. In order to introduce brand new UBM systems,intensive practical, as well as fundamentalstudies are required.

Additionally, it is very important to selecta proper PCB finish metallization. Forexample, when the PCB surface finish is CuOSP, Cu-rich IMC growth is observed atthe Ni UBM and solder interface, eventhough both UBM and solder originallydidn’t contain a Cu element. Cu in PCBsurface finish diffuses through the solderbump and forms Cu-rich Cu-Ni-Sn IMC on chip side UBM. This type of IMC growthrate is very high and it is hazardous topackage reliability. Therefore, themetallurgical design of flip-chipinterconnects (chip side UBM, solderbump, PCB surface finish) should beconsidered as a whole for successfulimplementation of Pb-free flip-chip.

References

1 K. Zeng, K. N. Tu, “Six cases of reliability study of Pb-free solder joints in electronic packagingtechnology”, Materials Science Engineering: R 38, p. 55, 2002

For further information please contact:[email protected]

Se-Young Jang

is currently a seniorengineer at Micro-Joining Lab.,Mechatronics Center,Samsung ElectronicsCo. Ltd. She received a Ph.D degree inMaterials Science andEngineering from theKorea AdvancedInstitute of Science and Technology(KAIST), Taejon, in2002. From 2000 to2001, she worked in the Department of High DensityInterconnect & WaferLevel Packaging at the Fraunhofer IZM,Germany, as a visiting researcher. Her research interests are flip-chip interconnection and system-in-package (SiP).

Sn/3.5AgSn/4.0Ag/0.5CuSn/0.7Cu

–3.2

–2.8

–2.4

–2.0

–1.6

–1.2

–0.8

–0.4

0.0

0.4

–1 0 1 2 3 4 5 6 7 8 9

280°C

260°C

280°C

280°C

260°C

260°C

Re

ma

inin

g N

i U

BM

th

ick

ne

ss [µ

m]

Reflow time [min]

Figure 5: Ni UBM

consumption of three

Pb-free solders with

increasing reflow time

(courtesy of Y. D. Jeon,KAIST)

Figure 4:

Cross-sectional TEM

bright field image of

the interface

between NiV/Cu

UBM and Sn/3.5Ag

solder bump after 5

min reflow at 250°C

Pb/63Sn Sn/3.5Ag

Cr/Cr-Cu/Cu – Pb/63Sn Cr/Cr-Cu/Cu-Sn/3.5Ag

NiV/Cu – Pb/63Sn NiV/Cu – Sn/3.5Ag

TiW/NiV – Pb/63Sn TiW/NiV – Sn/3.5Ag

TiW/Cu/ep.Cu – Pb/63Sn TiW/Cu/ep.Cu – Sn/3.5Ag

Figure 3: SEM cross-

sectional images

of eutectic Pb/63Sn

and Sn/3.5Ag solder

bumps on different

UBM systems after

20 min reflow at

210°C for Pb/Sn and

250°C for Sn/Ag.

Pb-free Sn/3.5Ag

shows more

aggressive reaction

with UBM than

eutectic Pb/63Sn.

a b

c d

e f

g h

22 | Chip Unaxis


The SHUTTLELINE™ Product Mission is to provide our entry level and R&Dcustomers with the world’s most costeffective solutions for their thin film etchingand dielectric deposition requirements. At Unaxis Semiconductors we accomplishthis through the marriage of two of theworld’s foremost suppliers of thesetechnologies, formerly known as Nextraland Plasma-Therm. We combine all of the best processes and technologies fromour resulting Grenoble, France, andSt.Petersburg, Florida, facilities (overallmore than 2,000 plasma systems shippedsince 1978), and leverage them onto anew common platform called theSHUTTLELINE™.

Unique in the world of entry level plasmaprocessing products is the fact that allSHUTTLELINE™ process chambers arevacuum loadlocked as a standard. Years of experience have taught that processchamber isolation is necessary in order toguarantee repeatable and predictableperformance, month after month. This isas true in the lab as it is in manufacturing.

Equally important to our R&Dcustomers is the user friendly but truly

Introducing the SHUTTLELINE™The latest product offering from Unaxis Semiconductors

Jim Pollock, Director, Claude Dupuy, Sales Engineer,


SHUTTLELINE™

NE D200 PECVD

NE D200 R PECVD

790 RIE

790 PECVD

NE 860 RL RIE

NE 860 R RIE

NE 860 L HDP

SLR RIE

SLR PECVD

SLR ICP


SHUTTLELINE™

advanced etching

system – ICP version

Unaxis Chip | 23


sophisticated and flexible control and data logging system. All SHUTTLELINE™products are operated through our field-proven NAPS-II, Windows™-baseddistributed control system.

Process technologies available on theSHUTTLELINE™ product line include:� Inductively Coupled Plasma (ICP)

Etching� Reactive Ion Etching (RIE)� High Density Plasma (HDP)

(microwave) Etching � Plasma Enhanced Chemical Vapor

Deposition (PECVD)

In addition to the deposition of dielectricthin films including SiO2, Si3N4, SiOxNy andBPSG are addressed etching requirementsover a broad variety of materials with theSHUTTLELINE™ product line. Here aresome of the materials for which starting-point etch processes are available:� Dielectrics – SiO2, Si3N4, Al2O3, AlTiC,

Photo Resist, Polyimide � Metals – Al, Cr, Molybdenum, Ti, W, Ta � Semiconductors – Si, SiC, TaSi � Compound Semiconductors – GaAs,

InP, AlGaAs, InGaP, InSb, GaN

HBTs

� Backside via etch� Frontside collector etch� Frontside emitter etch� Frontside isolation etch� Frontside nitride etch

HEMTs

� Backside via etch� Frontside gate recess etch� Frontside channel recess etch� Frontside nitride T-gate etch

SAW devices

� Aluminum feature etch� Aluminum trim etch� Quartz trim etch

Photonics

� VCSELs� EELs� Gratings� Lenses� LEDs� Wave guides

Microelectronics

� Accelerometers� Sensors� Moveable mirrors� Micro actuators� Switches� Tuneable discreet devices� Antennas

Deep Si etch for

GaN etching with controlledslope profile

1. GaN etching: Light Emitting Diode application

Vertical profile

GaN

Mask Type Etch rate Selectivity/mask Uniformity

(nm/min) (%) on 2 wafers

Resist mask 100 to 200 1 to 4 +/– 3%

Ni/SiO2/SiN 300 to 400 10 to 12 +/– 3%

BPSG deposited on stepstructure. No seam defectcan be observed.

BPSG deposited on groovestructures. Excellent fillingproperties can be observed.

2. BPSG deposition based on HMDSO / O2 / TMPi / TMB

chemistry: Array Wave Guide application

Results obtained on 4” diameter wafer. Deposited thickness 6 µm,HDMSO provides excellent step coverage, while avoiding any “seam” effect.

Opto/Electro-

Telecommunications

Refractive index Deposition rate Uniformity on 4" wafers

1.4579 +/– 0.0005 > 270 nm/min < +/– 1%

MEMS

Example of results obtained in the lab with the

SHUTTLELINE™

Owing to the inherent flexibilityof the SHUTTLELINE™,process technologies offeredcan be applied a number ofmarkets and a large variety ofdevice types. Just a fewexamples are:

SHUTTLELINE™

loadlock – Unloading

a processed wafer

from the “shuttle”

mechanism

24 | Chip Unaxis


All SHUTTLELINE™ systems will beequipped with a manual loadlock systemensuring excellent repeatability from run torun and a reduction of particle contami-nation. Substrates are loaded onto ashuttle in the loadlock (or pieces areloaded onto a carrier in some cases) and are then shuttled into the processchamber. A set of three pins lifts thewafer/carrier from the shuttle whichretracts and the cathode assembly risesto clamp the wafer/carrier and form thereaction chamber. The cathode isdesigned to accommodate all SEMIstandard wafer sizes from 2" to 200 mm.

In our high-density ICP systems, wafertemperature control is guaranteed throughthe use of wafer clamping coupled withbackside helium thermal transfer.

DeviceNet™ compatible componentssuch as MFCs, transducers, and valves,have been designed into theSHUTTLELINE™ series. Today, thisadvanced solution simplifies wiring and enables faster and easier design,

The SHUTTLELINE™ includes:

� Friendly user interface

� A unique capability of realtime

and after-run process control

(Particularly adapted for R&D)

� Different user groups where

each group has a specific

machine configuration,

parameter ranges and screen

appearance

� Alarm reporting: Warning

or alarm messages are stored

with indication of

type of alarm, failed

components, date, hour

and operator

build and field maintenance. In the future,the DeviceNet™-based components willsupport self-diagnostic functions. This,coupled with the “Telemaintenance”

Closing the loadlock

and preparing to

process a wafer

modem option, will permit fasttroubleshooting and minimize systemdown time.

To ensure each SHUTTLELINE™system is optimally configured for each customer’s application, UnaxisSemiconductors offers a comprehensivelist of optional equipment including endpoint detectors, temperature controllers,extra MFCs, wafer size change kits andspare parts kits.

For further detailed information on theSHUTTLELINE™ please contact:[email protected]

Feature

Your tool for R&D and pilot production

SHUTTLELINE – ICP version

USA Tel. +1 727 577 4999 KOREA Tel. +82 31 708 8666EUROPE Tel. +49 89 7550 5251 TAIWAN Tel. +886 3597 7771CHINA Tel. +86 21 5057 4646 JAPAN Tel. +81 3 3225 9020SINGAPORE Tel. +65 6890 6288 Other Tel. +423 388 4986


The SHUTTLELINE™merges the technology of

four systems and an extensive experience with an installed

base of over 650 tools, making it an ideal platform for R&D

and pilot production:

Multi-process platform for etching and deposition

including ICP, RIE and PECVD

Superior process solutions for HBTs, HEMTs, SAW,

Photonics and MEMS

Loadlock equipped for consistent process results

User friendly software standardized for all versions

Unmatched process support from the Unaxis

technology centers in the US and Switzerland

Secure your success in the Semiconductor business with the

new SHUTTLELINE and the support of our experienced Unaxis

professionals.

US

C/S

HU

TTLE

LIN

E/V

1/10

.02.

03

Merging the essence of

the SHUTTLELOCK, 790,

NE 860 and NE D200

Etching of quantum

well LEDs

SHUTTLELINESHUTTLELINE

26 | Chip Unaxis


Gallium nitride (GaN) has become animportant compound semiconductormaterial in the fabrication of an array ofoptical and electronic devices includinglight emitting diodes (LEDs), transistors,and laser devices for CD and DVD players. GaN is capable of operating at very high frequencies and power levels,demonstrating excellent thermal tolerance compared to other compoundsemiconductors such as gallium arsenideand indium phosphide.

Since bulk GaN is not commerciallyavailable, it is epitaxially grown on anappropriate lattice matched substratematerial such as sapphire or silicon carbide.Variations in the quality of the as grownGaN, coupled with the high bond energiesassociated with “III-nitride” materials (Table 1), present unique challenges for dryetching processes. As shown in Figure 1,GaN-based devices are often comprised of many epitaxial layers, including ternarycompounds incorporating different dopingtypes and concentrations. This article

presents recent etching results achievedusing high density Inductively CoupledPlasma (ICP) technology and chlorinebased process chemistries.

Using this technology, bulk, doped and multiple layer epitaxial structures canbe etched to meet device geometry andperformance requirements. Additionally,some comparisons are made withconventional Reactive Ion Etching (RIE)technology.

ICP GaN etching performance

Successful etching of GaN is characterized by smooth surfaces andappropriate profiles. This requires not only overcoming the strong nitride bondenergy but also adjusting the processconditions to deal with inherent defects inepitaxially grown GaN. An un-optimizedetching process can result in surfacemorphologies that include pits and/orpillars. While the GaN etching processproduces (volatile) chemical byproductssuch as GaCl3, the etching will notproceed without sufficient energetic ionbombardment due to the high bondstrength of the material. Defects in theGaN appear to be particularly sensitive to etching conditions and respond by etching faster or slower than thesurrounding material, ultimately formingpits or pillars. Fortunately, ICP systemsallow the flexibility to compensate for the material defects through the nearlyindependent control of the physical and chemical components of the etchmechanism. Two separate power suppliescontrol the plasma density (influencing the chemical component of the etching)and the ion energy (dominating thephysical portion of the process). Thisallows process optimization for a variety

of GaN structures and material quality. An example of this optimization flexibility isillustrated in Figure 2. When the ICP poweris increased, the process is driven into amore chemical regime through productionof higher concentrations of free radical(chlorine) etchant species. At the sametime, when the ion energy is maintained by increasing the cathode power theetching results in a smooth surfacemorphology. Unacceptable pitting or pillarformation will result if the balance betweenthe physical and chemical aspects of theprocess is not maintained.

Depending on the type of device beingfabricated, control of the GaN etchingprofile is desirable. In the case of a

Recent Advances in GaN Dry Etching Process Capabilities

Mike DeVre, Applications Lab Manager,

Russ Westerman, Principal Process Engineer,

Graham Muir, Business Unit Manager,

Laurent Bellon, Process Engineer, Unaxis

Semiconductors

Table 1:

III-nitride

bond

energies

Compound Bond energy

(eV/atom)

AIN 11.5

GaN 8.9

InN 7.7

GaAs 6.5

Contacts

Substrate

n- GaN

InGaN

p- GaN

Figure 1: Typical structure for GaN

based light emitting diode (LED)

ICP Power (plasma density)

RF

Po

we

r (io

n e

ne

rgy)

Figure 2: Pit /Pillar formation

vs RF/ICP power


Unaxis Chip | 27


transistor device, a sloped profile canbenefit post-etching metallizationprocesses. For an edge emitting laserdevice, a vertical profile is essential forlight guiding and reflecting properties.Over the range of GaN devices currently in use today, the ability to control etchingprofiles between 45 and 90 degrees may be necessary. To address thisrequirement, a combination of maskselection (material, profile) and etchingchemistry can be used to meet etchingprofile criteria. Figure 3 illustrates profilecontrol by selecting different maskingmaterials while using fixed processchemistry. While the silicon nitride, siliconoxide and metal are all consideredhardmask materials, the selectivity(difference in GaN and mask etching rates)variation and initial mask profile lead tochanges in the GaN etch profile.Conversely, for situations where maskselection is limited by process flow,adjustments to etching chemistry can be made to control the selectivity andhence, the resulting slope of the GaN. This capability is shown in Figure 4, where GaN is masked by a silicon dioxide filmand a metal film. While the slope of theoxide mask is different from that of the Nimask, the increased selectivity to theoxide mask (brought about by changes inthe process chemistry and conditions)results in the same degree of verticality inthe etched GaN.

Process alternatives – RIE and

ICP solutions

Current epitaxy and substrate materialtechnologies produce two and recently, three inch GaN wafers. These smallerwafer sizes (in comparison to silicon andgallium arsenide), coupled with market

pressures to reduce the cost of GaNbased devices, demand high throughputcapability for dry etching systems. Onesolution to this issue is to use a RIE basedprocess and run large batches of wafers. A comparison of RIE and ICP performanceis shown in Table 2. The drawbacks to theRIE approach are obvious, particularlywhen the device fabrication requires theetching of several microns of GaN material.

While the deficiencies associated withthe RIE approach can be offset by theability to batch load (six or more waferscan be etched at one time, depending onthe size), there is a significant reduction inetching rate associated with the increasedloading, as shown in Figure 5.

The concept of batch loading can beextended to the ICP system as shown inFigure 6, provided the “carrier” consists ofa process compatible material. Note thesubstrate (in this case the carrier) must beclamped and actively cooled (i.e., heliumbackside pressurization) in the ICP systemdue the high ion flux/energies. For thisapplication, quartz has been successfullyutilized and other materials, such asgraphite or sapphire, may also provebeneficial. Much like the batch RIEapproach, the process performance isaffected by the increase in wafer loadingas well as the selection of the carrier

material. As in the case of batch loadingthe RIE, there can be changes in etchingrates in the ICP as well. Despite theseeffects, the batch ICP performance is stillsuperior to that of the RIE.

GaN process solutions – meeting

technology requirements

Unaxis’ suite of dry etching equipmentand process solutions clearly offers GaNdevice manufacturers the right options to stay competitive in this growing marketsegment. While Unaxis still offers a RIE GaN etching solution, future effortswill focus on increasing throughputcapabilities by increasing ICP etchingrates while maintaining the presentdegrees of process flexibility outlined inthis article.


Figure 3: GaN profile

via mask selection

(nitride (a), oxide (b),

metal (c)), fixed

process chemistry

Process metric Typical performance

RIE ICP

Etching rate (Å/min) 750* 5000

Selectivity (GaN:Hardmask) ≥ 5:1 ≥ 10:1

Non-uniformity % ≤ ± 5 – 10* ≤ ± 3

Etched surfaces smooth smooth

*load dependent

Figure 4: GaN profile

via process chemistry

adjustment

Figure 5: GaN etch

rate vs wafer loading

Figure 6: GaN

substrates “batch”

loaded on single

carrier for ICP etch

Standard RIE – batchGaN etching rate vs loading

200

300

400

500

600

700

800

900

0 1 2 3 4 5 6 7

Wafer load [2"]

Etc

hin

g r

ate

[Å

/min

.]

1

2

3

45

Table 2: GaN etching

mode comparison

Wafer carrier – clamped/cooled

28 | Chip Unaxis


Microelectromechanical Systems (MEMS)were first introduced commercially in the early 1990s to activate airbags in cars and dispense ink in printers. MEMStechnology is a collection of miniaturesensors and actuators which are fabricated based upon semiconductor manufacturing techniques. Now MEMSare being introduced in a wide range ofconsumer products such as bloodpressure monitors, DVD players,camcorders, and PDAs. However, onepromising arena for next-generationMEMS devices is high-performance Hard Disk Drives (HDD).

As HDDs are introduced in newapplications, more stringent performancerequirements are encountered. Forexample, the use of storage devices incamcorders requires HDDs to withstandvibrations and handling; high-end market

Drive-Array Servers (DAS) require superiordata transfer characteristics which can be enhanced by detecting and correctingfor rotational vibrations in the system rack.One method to mitigate the effects ofvibrational and shock disturbances to theHDD uses a secondary control systemwhich includes sensitive MEMS-basedaccelerometers. These can be used toprovide a feed-forward correction signalfor the voice-coil motor (VCM) drive circuitto anticipate disturbances to the flyingread/write head.

The need for high capacity HDDs hasskyrocketed with increased processingand transmission of data. To meetincreasing storage capacity requirements,disc drive manufacturers can either putmore discs in a drive, which significantlyincreases component costs, or increasethe amount of data which can be stored per disc by increasing areal storagedensity (i.e., the number of Gigabits persquare inch that can be stored on the disc surface). Increases in areal densityrequire more precise head positioning as the read/write head flies over thespinning disc. MEMS microactuators can be used to achieve the desireddynamics and control precision of theread/write head.

Need for microactuators –

increasing data density

hard disk drives store digital data on amagnetic medium by setting the magneticfield of a small domain (one bit) to one oftwo polarities. The domains,corresponding to the digital data, areorganized in concentric rings on the discsurface called tracks. The read/write head (slider) is located at the end of abeam that flies over the disc surface asthe disc rotates (Figure 1). The separationbetween the slider and the spinning disc is created by an air bearing which isformed by etched cavities on the slidersurface. The beam which suspends theslider is actually comprised of two maincomponents: a very rigid beam called thee-block and the suspension. This is aspecially formed piece of stainless steelwhich both transfers lateral force from the e-block to the slider and provides thedownward force required to balance thelift generated by the flying slider. The e-block is attached to a pivot point and ismoved parallel to the disc by a VCM. TheVCM is responsible for keeping the headon the data track (track following), and formoving from track to track (seeking). For


MEMS Enhance Hard Disk Drive Performance

Roger Hipwell, Kyle Bartholomew,

Wayne Bonin, Zine-Eddine Boutaghou,

Seagate Technology

Abdul Lateef, Senoir Process Engineer,


Figure 1: Disc drive

diagram – actuation

system

Imagine an airplane flying at 5 million MPH but only 1/64 inchabove the ground on a 72,000lane highway where the lanes are only one inch wide. Theairplane is expected to switchlanes every few seconds andprecisely follow that lane. This analogy briefly describesthe challenge of flying andpositioning read/write headsfaced by today’s Hard Disk Drive (HDD) designers andmanufacturers.

VCM (primary actuator)

Pivot pointE-block

SuspensionSlider or transducer location

Unaxis Chip | 29


many years this system has successfullyperformed the track following and seekingfunctions even with tremendous increasesin areal density.

There are two basic ways to increasedata density on the disc surface. First, thesize of the magnetic domain which makesup a bit can be decreased, thus increasingthe number of bits per linear inch of trackcircumference. The second method ofincreasing data density is to decrease thewidth of the concentric tracks so moretracks can be recorded on a disc.However, a smaller track is more difficultto follow and at some point the VCMsystem is unable to compensate fordisturbances sufficiently to keep the headon track. The addition of a second-stageactuator (microactuator) to fine tune head position greatly extends the track-following capability of the VCM.

While a microactuator is primarilydesigned to improve tracking, it can alsoimprove the seek operation of the VCMsystem by actively compensating fordisturbances generated during the rapiddeceleration of the head as it settles ontoa new track. Figure 2 gives an example ofnarrowing track size and the impact ondata density and tracking capability.

Secondary actuation can beimplemented at three levels: at thesuspension, the slider, or as part of theread/write transducer itself.

Suspension-level microactuators arelarger scale structures which move all orpart of the suspension to achieve the finepositioning of the transducer. Theytypically use bulk piezoelectric elementsas an actuation mechanism. Such milli-scale devices have been built andtested, and are likely to be the firstimplementation of second stage actuation

in commercial disc drives. However, there are limitations in stroke and dynamicrange of suspension-level systems.

Slider-level microactuators areconsidered mid-size solutions on the disc drive microactuator roadmap. These devices are attached at the end of the suspension and move the entireslider body (which contains the read/writetransducers). Seagate’s MAGMA microactuator (to be discussed in the next section) is a slider-level MEMSmicroactuator.

Further miniaturization and integrationof MEMS technology in the slider leads to transducer-level microactuators whichmove the read/write transducer itself.Transducer-level microactuators offerdefinite advantages in terms of reducedmass and power consumption, but thefabrication and integration problemsposed by this type of device are

significant, and likely preclude their use in disc drives in the near future.

Seagate MAGMA Head-Level

Microactuator – a case study

One achievable state-of-the-artimplementation of MEMS for secondaryactuation is Seagate’s MAGMA (MAGnetic MicroActuator).

MAMGA device design

Seagate’s MAGMA is designed to significantly enhance the track followingcapability of the VCM system while stillmeeting the demanding mechanicalrobustness and cost requirements of the disc drive industry.

In configurations using a slider-levelmicroactuator, the read/write head isfabricated in the conventional manner.However, it is mounted onto the microactuator rather than directly on

Figure 2: Illustration

of improved track

following with

second stage of

actuation

Tracks narrow from 2.5 µm to 0.10 µm from 1 to 100 Gb/in2

Single stage servo Dual stage servo� Disturbances drive head off track � Improved frequency response� Voice coil cannot compensate enables more accurate tracking

Track boundaryHead travel-path

30 | Chip Unaxis


the suspension. The microactuator deviceis then mounted upon the suspension and moves the entire slider to fine tune the position of the read/write transducer in relation to the data track (Figures 3a and 3b).

Some MAGMA design considerationsinclude:� Sufficient stroke (amount of off-track

adjustment available) for tracking� High sensitivity (movement

distance/current or µm/mA) so powerrequirements are acceptable

� Use of voltage already available in drive to leverage current technology

� Mechanical ability to withstand largeforces – especially considering this will not be a packaged device

� Optimize natural frequency of theMAGMA device in relation to drivesystem disturbances

� Low cost of production� Ease of assembly� Minimal mass� Integration of the MEMS device with

existing drive infrastructure

MEMS fabrication techniques wereselected for their ability to producedevices of the size scale required, as well as the inherent cost advantagesfound in wafer-level batch fabrication. Bulk silicon micromachining, as opposedto surface micromachining, was alsochosen due to the need for high aspectratio structures.

The first two requirements, stroke and sensitivity, are met by using an electromagnetic motor for the MAGMAdevice. Choice of electromagneticactuation versus electrostatic actuation,allows usage of voltages already availablein the disc drive; however, higher current isrequired. Another important consideration

when using an electromagnetic motor in amagnetic media drive is containment ofthe magnetic flux. MAGMA employs aspecific type of high permeability metalformed into a magnetic keeper to shieldthe magnetic field from the disc surface.

The high aspect ratio (deep etchedsilicon) linear springs used in the MAGMAare critical because they provide a largeamount of stiffness perpendicular to thedisc while still remaining sufficiently flexibleparallel to the disc allowing a modestlysized driver to produce the needed stroke.Stiffness in the direction perpendicular tothe disc allows MAGMA to withstand thehigh G-force specifications placed on discdrives during shock events. The geometryof the springs, in conjunction with themoving mass, determines the resonantfrequency of the MAGMA device. Thespring geometry was chosen so the naturalfrequency of the device is not coupled withother known resonance frequencies in thedrive system. Such coupling can signifi-cantly hinder, or render impossible, goodtracking. Deep Silicon Etching (DSE™)technology from Unaxis Semiconductors is used to form the critical spring structuresin the silicon substrate.

DSE™ also defines the body of themicroactuator in the silicon wafer, as wellas creating recessed areas to which theslider and motor magnets are mounted.

MAGMAelectricalconnections

Suspension

Top keeper

Silicon body

Slider electricalconnections

Slider

Silicon stator(non-moving, attached to suspension)

Silicon rotor(moving, holds magnet and slider)

Magnet/bottom keeper

Narrow beam flexure(connects rotor to stator)

Read/write transducer

Electrical connections toread/write slider

Electrical connections to drive coil

Suspension

Figure 3a: Top view

of a MAGMA device

assembled and

mounted on a

suspension; MAGMA

device attached to

a suspension on

a dime (inset)

Figure 3b: Bottom

view of a MAGMA

device assembled

and mounted on a

suspension

Unaxis Chip | 31


The MAGMA body itself is designed such that automated pick-and-placetechnology can be used to assemble the silicon and non-silicon componentsefficiently.

MAGMA components and operation

The primary components for actuation area permanent magnet and conductive drivecoil. In addition, high permeability metalkeeper elements are used above andbelow the magnet and coil to contain andguide the electromagnetic field. Finally, a microfabricated silicon rotor /statorstructure is used to hold the componentstogether. The silicon structure also hasstandoffs to mechanically define the separation between the coil and the magnet.

To operate the MAGMA microactuator,current is driven through the copper coil.Electromagnetic theory indicates whencurrent runs through a magnetic field, a force is imparted upon the wire with across product vector relationship:

The direction of motor movement is controlled by the direction of thecurrent. The actuation force is proportional to the magnitude of thecurrent. The lateral force component(parallel to the disc surface) causes the rotor to move against the relativelyflexible silicon beams. Any vertical forcecomponents due to fringing effects nearthe edges of the magnet are absorbed by the high aspect ratio structure.

The components of the microactuatorare assembled together with the disc drivesuspension, electrical connections, andthe read/write head. A current of 50mAwill give approximately ± 5µm stroke. A key for manufacturability is assembly of the components. Automated batchassembly of the various components of a complicated device, such as MAGMA,can be the difference between beingsimply a novel device and a market revolutionizing, cost effective productionsolution.

The metal bottom keeper is formed by wet etching or mechanical stamping.The magnets can be diced to the desireddimensions by magnet manufacturers.

Drive coil fabrication

An exploded view of the epoxy encasedcopper coils is shown in Figure 4. As isdetailed in the process cross-sections of

Figure 5, the copper coils are formed byelectroplating in a photopatterned, high-aspect-ratio photoresist mold. Figure 6shows a view of this photoresist mold.

Figure 4: Exploded

view of the

integrated MAGMA

coil and top keeper

assembly

Top keeper

Solder pads

Top insulator

Copper sense coil (optional)

Middle insulator (optional)

Copper drive coil

Bottom insulator

Silicon body

Magnet

Bottom keeper (stainless steel)

Integrated coiland topkeeper assembly

Read/writeslider

Copper seed layer

Bottom epoxy layer

High permeability metalsubstrate

1. Photoresist is applied and patterned

2. Copper is electroplated to required height

3. Photoresist and seed layer are removed

4. Encapsulation epoxy is applied

5. Metal top keeper / substrate is wet etched to isolate individual die

Figure 5: Coil and top

keeper fabrication

process

Figure 6: SEM image

of photopatterned

resist electroplating

mold for drive coil

(Futerex NR9)

Resist platingmold

Conductiveseed layer forelectroplating

F=iL⊗ B where F = induced actuation forcei = current through coil

elementL = length of wire segmentB= magnetic field from

permanent magnet

32 | Chip Unaxis


The resist is subsequently stripped toallow for removal of the conductive platingseedlayer. Each coil layer is thenencapsulated in a spin-on photoimagableepoxy, Microchem SU8. SU8 has becomeextremely common in the MEMS industryfor its high aspect ratio patternability aswell as its mechanical and chemicalrobustness. Rather than build thesecomponents on a silicon substrate, theyare fabricated on a metal keeper wafer.This metal substrate is eventually wetetched from the opposite side to form thetop keeper element.

Silicon body fabrication using

Unaxis DSE™ process

The silicon rotor/stator body is formedusing DSE™ technology on a UnaxisVERSALOCK® platform. As is detailed inSteps 1 and 2 of Figure 7, approximately50 µm high mechanical standoffs areformed by etching into one side of a250 µm thick, double-side-polished siliconwafer. These mechanical standoffsdetermine the precise separation betweenthe top coil structure and the siliconrotor/magnet.

Next, oxide is deposited on the reverseside of the wafer with either thermaloxidation or Plasma Enhanced ChemicalVapor Deposition (PECVD). This oxide film is used as a hard mask for etching thesilicon. A Suss Microtech front-to-backcontact aligner is used with standardlithography techniques to pattern thestructure for the beams, slider pocket and magnet pocket. The oxide is thenpatterned with dry etching processessuch as Reactive Ion Etching (RIE) or HighDensity Inductively Coupled Plasma (ICP).The new DSE™-II offers increasedproductivity as compared to previous

DSE™-I performance and is used toobtain vertical walls in the narrowchannels forming the beams. Thesebeams, typically 10 – 50 µm wide, act assprings connecting the rotor and statorelements. Typical etching dimensions forthese channels in this device are 50mmwide by 200 µm deep. This etch goescompletely through the remaining 200 µm thickness of the silicon wafer as is shown in Step 5 of Figure 7.

The silicon rotor stator devices are held into the wafer using breakawaysilicon tabs. This allows the componentsto be retained in a wafer form after thethrough-wafer etch. It also allows forassembly of the other components(magnets, keepers, coils, sliders) to thesilicon body at the wafer level. The tabsare formed in the same step as etchingthe beams. This can be accomplished by capitalizing on an otherwise

Parameter Value Description

Etch rate > 6.5 µm/min

Within wafer uniformity < 2.5% (Max-Min)/2*average on 4 inch Si wafer

Selectivity > 600 :1 oxide:Si

Sidewall angle 90º ±1º

Figure 7: Silicon

structure fabrication

process1. Photolithographypattern of spacers

2. DSE etching to form spacers

5. DSE etch to formthe stator/rotor,beams and breakaway tabs

3. Blanket oxidedeposition &photolithographypattern to definemicroactuator structures

4. Oxide hardmaskdefinition withdry etching

Narrow trench definingbreakaway tab

Spacertabs Narrow spring beams

Magnetpocket

Table 1: Summary

of the Unaxis

DSE™ II – process

results optimized

for the MAGMA

application

Unaxis Chip | 33


Rotor

Stator

Breakawaytab

Narrow springbeams

undesirable etching effect called RIE lag.RIE lag is an aspect ratio dependentetching phenomenon. Silicon etch ratedecreases as aspect ratio increases. A standard silicon etch process wouldencounter difficulty in defining twofeatures of drastically different dimensionsin the same step. With the DSE™-II it ispossible to minimize this effect. However,for this application, the depth of the scribe line can be controlled by the widthof the trench. RIE lag would then causethe etching to stop in the very narrowtrench which defines the breakaway tab.This yields a robust enough structure tofinish the assembly process but allows for easy separation of the individual diewhen it is time to package it on thesuspension. Figure 8 shows scanningelectron microscope (SEM) images of aMAGMA structure following the finaletching steps.

To accomplish the deep silicon etch,Unaxis’ DSE™-II technology is utilizedwhich offers high etching rates, highselectivity to mask, as well as excellentprofile control. This technology enablesthe process engineer to optimize the

performance of the process to achievespecific goals such as minimizing sidewall roughness, minimizing RIE lagand maximizing etch rate.

Acknowledgements

The authors acknowledge the key contributors of the MAGMA microactuator process team in theSeagate MEMS Technology Group: K. Vang, T. Erickson, L. Walter, B. DuFrene, P. Crane, B. Wissman, B. Polson, J. Tushar, B. Ihlow-Mahrer,S. Hao, A. Swann, and M. Markuson. The authorswould also like to acknowledge the keycontributors of the Seagate Advanced TrackingTechnology group and Advanced AssemblyTechnology group: B. Vermeer, A. White, J. Limmer,M. Mangold, M. Bowers, D. Aamoth, J. Engbrit, M. Krosch, J. Hurley, K. Staub, and C. Hardie.

References

1 US Patent 5,501,893 “Method ofAnisotropically Etching Silicon”

2 US Patent 6,387,778 “Breakable Tethers forMicroelectromechanical Systems UtilizingReactive Ion Etch Lag”

3 US Patent 6,525,822 “Magnetic Microactuator”4 US Patent 6,414,823 “Coil Structures for

Magnetic Microactuators” 5 US Patent 6,362,939 “Balanced Microactuator

Suspension” 6 US Patent 6,282,066 “Microactuator with

Multiple Narrow Beams” 7 US Patent 6,198,606 “Disc drive actuation

system having an injection molded magneticmicro-actuator with metal beam inserts and its method of fabrication”

8 US Patent 6,351,354 “Head to flexure interconnection for disc drive microactuator”

9 US Patent Application 2002/96944 “MovingCoil Microactuator with Reduced Rotor Mass”[Patent Pending]

10 US Patent Application 2002/18322 “Micro-Actuator Structure for ImprovedStability” [Patent Pending]

11 US Patent Application 2002/8943 “BondingTub for Improved ElectromagneticMicroactuator in Disc Drives” [Patent Pending]

12 US Patent Application 2002/48577 “FabricationMethod for Integrated Microactor Coils” [PatentPending]

13 US Patent 5,501,893 “Method ofAnisotropically Etching Silicon”

Figure 8: Magma

silicon structure

following final

structure DSE-II™

34 | Chip Unaxis



For dielectric fill applications, an important property for a depositionprocess is the ability to obtain goodcoverage for features which have a highaspect ratio. The Unaxis CORONA®

high rate reactive alumina depositionsystem provides good step coverage, as demonstrated here. To obtain theseresults, deposits were made underdifferent process conditions for stepcoverage evaluation.

The parameters which were investigatedin this study were the total processpressure and the applied substrate bias.Deposits were made on test structuresconsisting of parallel metal lines with aheight of 5 µm and spacing of 2 to morethan 20 µm. Figures 1, 2 and 3 clearlyshow how the trenches are filled.

All the deposits described here wereobtained with a combination of RF and DCpower to the aluminum target. The RF andDC power in these experiments were allkept at the same level (2150 W RF and2300 W DC). Applying RF power to thesubstrate table induced the substrate bias.The argon flow was adjusted to obtainoptimum pressure control conditions, and the oxygen flow was adjusted to avalue calculated from the flow at which the aluminum target goes into the poisonmode. This value is determined byincreasing the oxygen flow in steps of one sccm until the target poisons. This can be observed by a sudden drop ofseveral hundred volts in the target potential.

Table 1 shows whether the trencheswith different aspect ratios (AR) are

High Rate ReactiveAlumina Depositionfor Dielectric Fill Applications

Dr. Gerard van der Leeden, Senior

Process Engineer, Abdul Lateef, Senior Process

Engineer, Unaxis Semiconductors

Table 1: Closure

of trenches with

different aspect

ratios

Figure 1: SEM micrograph

of a 5 µm thick film

deposited at 10 uBar

and – 50 V bias



deposited at 10 uBar

and – 300 V bias



deposited at 2 uBar

and – 400 V bias

Condition AR = 0.9 AR = 1.2 AR = 1.5 AR = 2 AR = 3

10 uBar, –50 V open open closed closed closed

10 uBar, –300 V open open closed closed closed

2 uBar, –400 V open open open open N.A.

closed or open when a 5 µm thick film is deposited.

The deposited 2 uBar film clearly offers the best trench fill performance. For the 10 uBar films a higher biaswas not applied because of the superiorperformance of the low pressure process.

Low pressure operation for theCORONA® reactive alumina depositionprovides an improvement for fillapplications as compared to a highpressure (10 – 20 uBar) process.

Additional evaluation is under way to further determine the mechanical and dielectric properties under theseconditions.



Unaxis Chip | 35


It has been predicted micro-electro-mechanical (MEMS) devices will emerge asan enabling technology in many applicationareas. In many MEMS devices, high aspectratio features need to be fabricated on Sisubstrates. Unaxis Semiconductors nowoffers DSE™-III technology, the nextgeneration of faster, more capable, dryetching tools to meet the needs of theseapplications. Unaxis Semiconductorscontinues as a technology enabler forMEMS applications.

The DSE™-III provides three keyperformance benefits: high silicon (Si) etch rate, etch profile quality, andimproved SOI (silicon on insulator) etch performance. In this article, we report the performance results for the DSE™-III technology.

High etch rate: > 20 µm/min

High etch rate is often an essentialrequirement to ensure good productionthroughput when etching deep Si

structures, such as trenches and vias. For deep Si etching, the time divisionmultiplex (TDM) etch processes, so-called“Bosch” processes, are widely employed.The TDM process employs alternatingdeposition with octofluorocyclobutane(C4F8) and etching using sulfurhexafluoride(SF6). As shown schematically in Figure 1,during the etching cycles, fluorine (F)radicals from a SF6 discharge promotespontaneous and isotropic etching of Si.During the deposition cycles, a C4F8

discharge forms Teflon-like polymerpassivation on all surfaces. Duringsubsequent etching cycles, the passivationpolymer is removed preferentially from thebottom of etched trenches subject to ionbombardment, while passivation onsidewalls remains to inhibit lateral etching.This approach allows anisotropic highaspect ratio features to be defined intosilicon substrates at high etch rates.

In order to achieve high Si etch rates,high F radical concentrations in theplasma are needed. Fluorine radicalconcentrations are a function of theamount of available precursor (SF6 in thiscase) as well as the dissociation efficiencyin the plasma. Precursor availability is

determined by the process pressure andprecursor flow rate while the dissociationefficiency is a function of ICP power. WithDSE™-III, increased ICP (InductivelyCoupled Plasma) source power and SF6

flow rate have resulted in Si etch rates inexcess of 20 µm/min.

Figure 2 demonstrates the experimentalresults. The test wafer was 150 mm indiameter with an exposed area which was15% of the total wafer area. In 100 µm-wide trenches, an etch rate of 20.7 µm/min was achieved (Figure 2a);at 2.5 µm-wide trenches, the etch rate was 12.7 µm/min (Figure 2b).In comparison, the current TDM tools are capable of Si etch rates around 5 µm/min. Feature profiles shown abovedemonstrate high Si etch rates as the keyperformance parameter. The addition ofadvanced sidewall control is discussed.

Scallop minimization: < 0.5 µm

As illustrated in Figure 1, the TDM etchprocess results in sidewall roughness dueto “scallop” formation. This scallopformation is attributed to the isotropicnature of F etching of Si. The scallopamplitude, peak-to-peak distance and

Unaxis’ New Deep Silicon Etch Technology (DSE™-III)

Dr. Shouliang Lai, Senior Process Engineer

Russ Westerman, Principal Process Engineer

Mike Devre, Application Lab Manager

(a) (b)

(c) (d)

Figure 1:

(a) A Si wafer with

patterned mask,

(b) an etching cycle,

during which fluorine

radicals provide

isotropic etching,

(c) a passivation

cycle, during which

polymer forms

on all surfaces,

(d) a subsequent

etching cycle, during

which polymer at the

bottom is removed

allowing etching to

continue

Figure 2:

(a) 100 µm-wide

trenches, an etch

rate of 20.7 µm/min

was achieved;

(b) 2.5 µm-wide

trenches, the

etch rate was

12.7 µm/min

a b


36 | Chip Unaxis


peak-to-valley depth, are directlycorrelated to the etching depth duringeach single etch cycle. The TDM Si etchrate can be increased by either increasingthe time spent in each etch cycle orthrough increasing the efficiency of eachetch cycle. Both of these approaches lead to larger scallops and consequentlyrougher sidewalls. In other words, inconventional TDM Si etch processes, high etch rates are only achievable at the expense of rougher sidewalls.

Through the DSE™-III use of advancedtechnology, we have developed aproprietary fast gas switching technique to achieve scallop minimization whilemaintaining the high Si etch rates. Thisfast gas switching technique enablesprocess cycle times < 1 second in lengthin conjunction with smoother transitionsduring processing gas exchanges.

In comparison, conventional TDMprocesses require at least several secondsfor each process cycle. Consequently inDSE™-III, scallop length is reduced to < 0.5 µm while maintaining Si etch rates of ~10 µm/min.

Figure 3 shows the DSE™-III smoothedsidewall along with the Si sidewall of aconventional TDM etch process. For theconventional TDM process (Figure 3a),scallop length is > 0.5-1.0 µm while the Si etch rate is ~ 5 µm/min. In Figure 3b,significant scallop minimization hencesidewall smoothing is shown using thefast gas switching technique. Figure 3cprovides the close-up of the sidewallshown in Figure 3b. The longest scallop is 0.085 µm in depth and 0.12 µm inlength. The silicon etch rate in this case is 7.1 µm/min.

Silicon on insulator applications

Many MEMS applications only involve bulkSi wafers. However, certain applicationscall for SOI (silicon on insulator) structureswhere a “buried” oxide layer exists. This layer has several functions such assacrificial post-etch release or devicemembrane, and presents unique challengesto the deep silicon etch processes.

When etching Si, charged ions areconstantly reacting and recombining on the wafer surface. However, therecombination of charges is inhibited oncethe etching front reaches the insulatinglayer. This causes a redistribution andseparation of charges within the etchedfeatures in such a way that incident ionsare deflected toward silicon walls at the silicon/oxide interface, forcing the etch to proceed laterally, as illustrated in Figure 4a. This lateral etch results in notch formation at the Si /SiO2 interfaceparticularly if the cleared features aresubjected to an overetch. In most MEMSdevices, notching is undesirable. It shouldbe noted that notching is also linked to the aspect ratio dependent etching(ARDE) phenomenon in Si etching. ARDEis the tendency for the larger features tobe etched at higher rates. Consequently,when etched at the same time, widertrenches tend to clear before their smallercounterparts resulting in the largerfeatures being subjected to additionalprocess overetch until the smaller features clear. Prior to the availability ofDSE™-III, Unaxis Semiconductors haddeveloped a patented solution to the SOI notching problem. In the DSE™-IIIdevelopment, this solution has beenextended, enabling faster Si etching toproceed while minimizing notch formation at the Si/insulator interface. DSE™-IIItechnology performance result is shown in Figure 4b, As shown, the notchelimination performance is excellent with DSE™-III technology, while an etch rate of ~3 µm/min was obtained.


Figure 3: SEM images

showing sidewall

scallops with (a)

conventional TDM,

(b) gas switching

technique, and (c)

high resolution

close-up of the

silicon sidewall

shown in (b).

Figure 4:

(a) Schematic

diagram for SOI

notch formation,

and (b) DSE™-III

performance for

SOI wafer etching

a

c

b

Scallops Si

OxideBuried

Silicon

Mask

Silicon

b

a

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