Buses and Peripheral Device

download Buses and Peripheral Device

of 42

Transcript of Buses and Peripheral Device

  • 8/3/2019 Buses and Peripheral Device

    1/42

    8-1 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    Computer Architecture andOrganization

    Miles Murdocca and Vincent Heuring

    Chapter 8 Buses and

    Peripherals

  • 8/3/2019 Buses and Peripheral Device

    2/42

    8-2 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    Chapter Contents

    8.1 Parallel Bus Architectures

    8.2 Bridge-Based Bus Architectures

    8.3 Internal Communication Methodologies

    8.4 Case Study: Communication on the Intel Pentium Architecture

    8.5 Serial Bus Architectures8.6 Mass Storage

    8.7 RAID Redundant Arrays of Inexpensive Disks

    8.8 Input Devices

    8.9 Output Devices

    8.10 Case Study: Graphics Processing Unit8.11 Case Study: How a Virus Infects a Machine

  • 8/3/2019 Buses and Peripheral Device

    3/42

    8-3 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    Simple Bus Architecture

    A simplified motherboard of a personal computer (top view):

  • 8/3/2019 Buses and Peripheral Device

    4/42

    8-4 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    Simplified Illustration of a Bus

  • 8/3/2019 Buses and Peripheral Device

    5/42

    8-5 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    100 MHz Bus Clock

  • 8/3/2019 Buses and Peripheral Device

    6/42

    8-6 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    The Synchronous Bus

    Timing diagram for a synchronous memory read (adapted from[Tanenbaum, 1999]).

  • 8/3/2019 Buses and Peripheral Device

    7/42

    8-7 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    The Asynchronous Bus

    Timing diagram for asynchronous memory read (adapted from[Tanenbaum, 1999]).

  • 8/3/2019 Buses and Peripheral Device

    8/42

    8-8 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    Bus Arbitration

    (a) Simple centralized

    bus arbitration; (b)

    centralized arbitration

    with priority levels; (c)

    fully centralized busarbitration; (d)

    decentralized bus

    arbitration. (Source:

    adapted from

    [Tanenbaum, 1999].)

  • 8/3/2019 Buses and Peripheral Device

    9/42

    8-9 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    BridgeBased

    Bus Arch-itecture

    Bridging with dual

    Pentium processors.

    Source:

    http://www.intel.com.

  • 8/3/2019 Buses and Peripheral Device

    10/42

    8-10 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    Programmed I/OFlowchart for a

    Disk Transfer

  • 8/3/2019 Buses and Peripheral Device

    11/42

    8-11 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    InterruptDriven I/O

    Flowchart for

    a DiskTransfer

  • 8/3/2019 Buses and Peripheral Device

    12/42

    8-12 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    DMA Transfer from Disk to Memory

    Bypasses the CPU

  • 8/3/2019 Buses and Peripheral Device

    13/42

    8-13 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    DMA Flowchart for a Disk Transfer

  • 8/3/2019 Buses and Peripheral Device

    14/42

    8-14 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    Intel Memory and I/O Address Spaces

  • 8/3/2019 Buses and Peripheral Device

    15/42

    8-15 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    Standard Intel Pentium Read and

    Write Bus Cycles

  • 8/3/2019 Buses and Peripheral Device

    16/42

    8-16 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    Intel Pentium Burst Read Bus Cycle

  • 8/3/2019 Buses and Peripheral Device

    17/42

    8-17 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    IntelPentium

    Hold-HoldAcknow-ledge Bus

    Cycle

  • 8/3/2019 Buses and Peripheral Device

    18/42

    8-18 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    RS-232

    The RS-232 standard commonly uses 9-pin and 25-pin connectors, butuses others as well (see the figure).

    RS-232 is used for slow-bit-rate devices such as mice, keyboards, and

    non-graphics terminals.

  • 8/3/2019 Buses and Peripheral Device

    19/42

    8-19 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    USB and FirewireUniversal Serial Bus (USB) and IEEE 1394 (Firewire) are groups of

    standards for interconnecting peripheral devices. USB 2.0 supports data

    transfer rates up to 480 Mbps, with as many as 127 devices connected to

    a single host controller through special hub devices in a tree-like manner.

    Firewire is similar to USB but has traditionally been faster, up to 800 Mbps.

    A key advantage of Firewire is isochronous data transfer, in which acontinuous, guaranteed data transfer is supported at a predetermined rate.

    This makes Firewire attractive for digital video and digital audio.

    (left) USB hub; (middle) USB cable; (right) Firewire cable.

  • 8/3/2019 Buses and Peripheral Device

    20/42

    8-20 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    A Magnetic Disk with Three Platters

  • 8/3/2019 Buses and Peripheral Device

    21/42

    8-21 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    Manchester Encoding (a) Straight amplitude (NRZ) encoding of ASCII F; (b) Manchester

    encoding of ASCII F.

  • 8/3/2019 Buses and Peripheral Device

    22/42

    8-22 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    Organization of a Disk Platter with a

    1:2 Interleave Factor

  • 8/3/2019 Buses and Peripheral Device

    23/42

    8-23 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    Master

    ControlBlock

  • 8/3/2019 Buses and Peripheral Device

    24/42

    8-24 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    Magnetic Tape

    A portion of a magnetic tape.

  • 8/3/2019 Buses and Peripheral Device

    25/42

    8-25 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    Digital Audio Tape (DAT)

    Digital audio tape (DAT) formatting supports high densities, on the

    order of 72 GB for a small 73 mm 54 mm profile. The read / write

    head is placed at an angle to the tape as shown in the figure, allowing

    data to be criss-crossed over the same area, using opposite polarities

    which maintains separation of the bits.

  • 8/3/2019 Buses and Peripheral Device

    26/42

    8-26 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    Spiral Format for Compact Disk

    Unlike a magnetic disk in which all of the sectors on concentric tracksare lined up like a sliced pie (where the disk rotation uses constant

    angular velocity), a CD is arranged in a spiral format (using constant

    linear velocity). The speed of rotation is adjusted so that the disk

    moves more slowly when the head is at the edge than when it is at the

    center.

  • 8/3/2019 Buses and Peripheral Device

    27/42

    8-27 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    Redundant Arrays of InexpensiveDisks (RAID)

    RAID level 0 striped disk array without fault tolerance.

    RAID level 1 mirroring and duplexing.

  • 8/3/2019 Buses and Peripheral Device

    28/42

    8-28 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    RAID (Continued)

    RAID level 2 bit-level striping with Hamming Code ECC.

    RAID level 3 parallel transfer with parity.

  • 8/3/2019 Buses and Peripheral Device

    29/42

    8-29 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    RAID (Continued)

    RAID level 4 independent data disks with shared parity disk.

    RAID level 5 independent data disks with distributed parity blocks.

  • 8/3/2019 Buses and Peripheral Device

    30/42

    8-30 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    RAID (Continued)

    RAID level 6 independent data disks with two independentdistributed parity schemes.

    RAID level 7 asynchronous cached striping with dedicated parity.

  • 8/3/2019 Buses and Peripheral Device

    31/42

    8-31 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    RAID (Continued)

    RAID level 10 very high reliability combined with high performance.

    RAID level 53 high I/O rates and data transfer performance.

  • 8/3/2019 Buses and Peripheral Device

    32/42

    8-32 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    ECMA-23 Keyboard Layout

    Keyboard layout for the ECMA-23 Standard (2nd ed.). Shift keys are

    frequently placed in the B row.

  • 8/3/2019 Buses and Peripheral Device

    33/42

    8-33 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    The Dvorak Keyboard Layout

  • 8/3/2019 Buses and Peripheral Device

    34/42

    8-34 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    Tablet with Puck

  • 8/3/2019 Buses and Peripheral Device

    35/42

    8-35 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    Mouse and TrackballA mechanical mouse (left), a three-button trackball (center), and an

    optical mouse (right).

  • 8/3/2019 Buses and Peripheral Device

    36/42

    8-36 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    Touch Sensitive Pen-based Display Pen-based personal digital assistants (PDAs) use a passive matrix in

    which the pen can be anything that induces pressure on the screen.

    Two transparent

    conducting layers are

    placed on the screen,

    separated by spacer dots.

    When the user applies

    pressure to the top layer,

    as with a stylus or simply a

    finger, the top and bottom

    layers make contact. The

    induced voltage at theedges varies according to

    the position of the stylus.

  • 8/3/2019 Buses and Peripheral Device

    37/42

    8-37 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    Joystick

    A joystick with a selection button and a rotatable rod:

  • 8/3/2019 Buses and Peripheral Device

    38/42

    8-38 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    Laser Printer

    Schematic of a laser printer (adapted from [Tanenbaum, 1999]).

  • 8/3/2019 Buses and Peripheral Device

    39/42

    8-39 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    Cathode Ray Tube

    A CRT with a single electron gun:

  • 8/3/2019 Buses and Peripheral Device

    40/42

    8-40 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    Display Controller

    Display controllerfor a 1024768

    color monitor

    (adapted from

    [Hamacher et al.,

    1990]).

  • 8/3/2019 Buses and Peripheral Device

    41/42

    8-41 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    Active Matrix Color Liquid Crystal

    Display

  • 8/3/2019 Buses and Peripheral Device

    42/42

    8-42 Chapter 8 - Buses and Peripherals

    Computer Architecture and Organizationby M. Murdocca and V. Heuring 2007 M. Murdocca and V. Heuring

    Matrix Parhelia-512 GPU