Bus-Based Computer Systems
description
Transcript of Bus-Based Computer Systems
![Page 1: Bus-Based Computer Systems](https://reader035.fdocuments.net/reader035/viewer/2022062222/56815748550346895dc4eab9/html5/thumbnails/1.jpg)
© 2008 Wayne WolfOverheads for Computers as
Components 2nd ed.
Bus-Based Computer Systems
• Busses.• Memory devices.• I/O devices:
• serial links• timers and counters• keyboards• displays• analog I/O
1
![Page 2: Bus-Based Computer Systems](https://reader035.fdocuments.net/reader035/viewer/2022062222/56815748550346895dc4eab9/html5/thumbnails/2.jpg)
© 2008 Wayne WolfOverheads for Computers as
Components 2nd ed.
The CPU bus
• Bus allows CPU, memory, devices to communicate.• Shared communication medium.
• A bus is:• A set of wires.• A communications protocol.
2
![Page 3: Bus-Based Computer Systems](https://reader035.fdocuments.net/reader035/viewer/2022062222/56815748550346895dc4eab9/html5/thumbnails/3.jpg)
© 2008 Wayne WolfOverheads for Computers as
Components 2nd ed.
Bus protocols
• Bus protocol determines how devices communicate.
• Devices on the bus go through sequences of states.• Protocols are specified by state
machines, one state machine per actor in the protocol.
• May contain asynchronous logic behavior.
3
![Page 4: Bus-Based Computer Systems](https://reader035.fdocuments.net/reader035/viewer/2022062222/56815748550346895dc4eab9/html5/thumbnails/4.jpg)
© 2008 Wayne WolfOverheads for Computers as
Components 2nd ed.
Four-cycle handshake
device 1 device 2enq
ack
time
device 1
device 2
1 2 3 4
4
![Page 5: Bus-Based Computer Systems](https://reader035.fdocuments.net/reader035/viewer/2022062222/56815748550346895dc4eab9/html5/thumbnails/5.jpg)
© 2008 Wayne WolfOverheads for Computers as
Components 2nd ed.
Four-cycle handshake, cont’d.
1. Device 1 raises enq.2. Device 2 responds with ack.3. Device 2 lowers ack once it has
finished.4. Device 1 lowers enq.
5
![Page 6: Bus-Based Computer Systems](https://reader035.fdocuments.net/reader035/viewer/2022062222/56815748550346895dc4eab9/html5/thumbnails/6.jpg)
Microprocessor busses
• Clock provides synchronization.
• R/W is true when reading (R/W’ is false when reading).
• Address is a-bit bundle of address lines.
• Data is n-bit bundle of data lines.
• Data ready signals when n-bit data is ready.
© 2008 Wayne WolfOverheads for Computers as
Components 2nd ed. 6
![Page 7: Bus-Based Computer Systems](https://reader035.fdocuments.net/reader035/viewer/2022062222/56815748550346895dc4eab9/html5/thumbnails/7.jpg)
© 2008 Wayne WolfOverheads for Computers as
Components 2nd ed.
Timing diagrams
7
![Page 8: Bus-Based Computer Systems](https://reader035.fdocuments.net/reader035/viewer/2022062222/56815748550346895dc4eab9/html5/thumbnails/8.jpg)
© 2008 Wayne WolfOverheads for Computers as
Components 2nd ed.
Bus read
8
![Page 9: Bus-Based Computer Systems](https://reader035.fdocuments.net/reader035/viewer/2022062222/56815748550346895dc4eab9/html5/thumbnails/9.jpg)
© 2008 Wayne WolfOverheads for Computers as
Components 2nd ed.
State diagrams for bus read
CPU device
Get data
Done
Adrs
Wait
See ack
Senddata
Release ack
Adrs
Wait
Ack
start
9
![Page 10: Bus-Based Computer Systems](https://reader035.fdocuments.net/reader035/viewer/2022062222/56815748550346895dc4eab9/html5/thumbnails/10.jpg)
© 2008 Wayne WolfOverheads for Computers as
Components 2nd ed.
Bus wait state
10
![Page 11: Bus-Based Computer Systems](https://reader035.fdocuments.net/reader035/viewer/2022062222/56815748550346895dc4eab9/html5/thumbnails/11.jpg)
© 2008 Wayne WolfOverheads for Computers as
Components 2nd ed.
Bus burst read
11
![Page 12: Bus-Based Computer Systems](https://reader035.fdocuments.net/reader035/viewer/2022062222/56815748550346895dc4eab9/html5/thumbnails/12.jpg)
© 2008 Wayne WolfOverheads for Computers as
Components 2nd ed.
Bus multiplexing
CPU
adrs
device
data
adrs
data enable
Adrs enable
12
![Page 13: Bus-Based Computer Systems](https://reader035.fdocuments.net/reader035/viewer/2022062222/56815748550346895dc4eab9/html5/thumbnails/13.jpg)
DMA
• Direct memory access (DMA) performs data transfers without executing instructions.• CPU sets up transfer.• DMA engine fetches,
writes.
• DMA controller is a separate unit.
© 2008 Wayne WolfOverheads for Computers as
Components 2nd ed. 13
![Page 14: Bus-Based Computer Systems](https://reader035.fdocuments.net/reader035/viewer/2022062222/56815748550346895dc4eab9/html5/thumbnails/14.jpg)
Bus mastership
• By default, CPU is bus master and initiates transfers.
• DMA must become bus master to perform its work.• CPU can’t use bus while DMA operates.
• Bus mastership protocol:• Bus request.• Bus grant.
© 2008 Wayne WolfOverheads for Computers as
Components 2nd ed. 14
![Page 15: Bus-Based Computer Systems](https://reader035.fdocuments.net/reader035/viewer/2022062222/56815748550346895dc4eab9/html5/thumbnails/15.jpg)
DMA operation
• CPU sets DMA registers for start address, length.
• DMA status register controls the unit.
• Once DMA is bus master, it transfers automatically.• May run continuously
until complete.• May use every nth bus
cycle.
© 2008 Wayne WolfOverheads for Computers as
Components 2nd ed. 15
![Page 16: Bus-Based Computer Systems](https://reader035.fdocuments.net/reader035/viewer/2022062222/56815748550346895dc4eab9/html5/thumbnails/16.jpg)
© 2008 Wayne WolfOverheads for Computers as
Components 2nd ed.
Bus transfer sequence diagram
16
![Page 17: Bus-Based Computer Systems](https://reader035.fdocuments.net/reader035/viewer/2022062222/56815748550346895dc4eab9/html5/thumbnails/17.jpg)
System bus configurations
• Multiple busses allow parallelism:• Slow devices on
one bus.• Fast devices on
separate bus.
• A bridge connects two busses.
© 2008 Wayne WolfOverheads for Computers as
Components 2nd ed.
CPU slow device
memory
high-speeddevice
brid
ge
slow device
17
![Page 18: Bus-Based Computer Systems](https://reader035.fdocuments.net/reader035/viewer/2022062222/56815748550346895dc4eab9/html5/thumbnails/18.jpg)
© 2008 Wayne WolfOverheads for Computers as
Components 2nd ed.
Bridge state diagram
18
![Page 19: Bus-Based Computer Systems](https://reader035.fdocuments.net/reader035/viewer/2022062222/56815748550346895dc4eab9/html5/thumbnails/19.jpg)
ARM AMBA bus
• Two varieties:• AHB is high-
performance.• APB is lower-speed,
lower cost.
• AHB supports pipelining, burst transfers, split transactions, multiple bus masters.
• All devices are slaves on APB.
© 2008 Wayne WolfOverheads for Computers as
Components 2nd ed. 19
![Page 20: Bus-Based Computer Systems](https://reader035.fdocuments.net/reader035/viewer/2022062222/56815748550346895dc4eab9/html5/thumbnails/20.jpg)
Memory components
• Several different types of memory:• DRAM.• SRAM.• Flash.
• Each type of memory comes in varying:• Capacities.• Widths.
© 2008 Wayne WolfOverheads for Computers as
Components 2nd ed. 20
![Page 21: Bus-Based Computer Systems](https://reader035.fdocuments.net/reader035/viewer/2022062222/56815748550346895dc4eab9/html5/thumbnails/21.jpg)
© 2008 Wayne WolfOverheads for Computers as
Components 2nd ed.
Random-access memory
• Dynamic RAM is dense, requires refresh.• Synchronous DRAM is dominant type.• SDRAM uses clock to improve
performance, pipeline memory accesses.
• Static RAM is faster, less dense, consumes more power.
21
![Page 22: Bus-Based Computer Systems](https://reader035.fdocuments.net/reader035/viewer/2022062222/56815748550346895dc4eab9/html5/thumbnails/22.jpg)
© 2008 Wayne WolfOverheads for Computers as
Components 2nd ed.
SDRAM operation
22
![Page 23: Bus-Based Computer Systems](https://reader035.fdocuments.net/reader035/viewer/2022062222/56815748550346895dc4eab9/html5/thumbnails/23.jpg)
© 2008 Wayne WolfOverheads for Computers as
Components 2nd ed.
Read-only memory
• ROM may be programmed at factory.• Flash is dominant form of field-
programmable ROM.• Electrically erasable, must be block
erased.• Random access, but write/erase is much
slower than read.• NOR flash is more flexible.• NAND flash is more dense.
23
![Page 24: Bus-Based Computer Systems](https://reader035.fdocuments.net/reader035/viewer/2022062222/56815748550346895dc4eab9/html5/thumbnails/24.jpg)
© 2008 Wayne WolfOverheads for Computers as
Components 2nd ed.
Timers and counters
• Very similar:• a timer is incremented by a periodic
signal;• a counter is incremented by an
asynchronous, occasional signal.
• Rollover causes interrupt.
24
![Page 25: Bus-Based Computer Systems](https://reader035.fdocuments.net/reader035/viewer/2022062222/56815748550346895dc4eab9/html5/thumbnails/25.jpg)
© 2008 Wayne WolfOverheads for Computers as
Components 2nd ed.
Watchdog timer
• Watchdog timer is periodically reset by system timer.
• If watchdog is not reset, it generates an interrupt to reset the host.
host CPU watchdogtimer
interrupt
reset
25
![Page 26: Bus-Based Computer Systems](https://reader035.fdocuments.net/reader035/viewer/2022062222/56815748550346895dc4eab9/html5/thumbnails/26.jpg)
© 2008 Wayne WolfOverheads for Computers as
Components 2nd ed.
Switch debouncing
• A switch must be debounced to multiple contacts caused by eliminate mechanical bouncing:
26
![Page 27: Bus-Based Computer Systems](https://reader035.fdocuments.net/reader035/viewer/2022062222/56815748550346895dc4eab9/html5/thumbnails/27.jpg)
© 2008 Wayne WolfOverheads for Computers as
Components 2nd ed.
Encoded keyboard
• An array of switches is read by an encoder.
• N-key rollover remembers multiple key depressions.
row
27
![Page 28: Bus-Based Computer Systems](https://reader035.fdocuments.net/reader035/viewer/2022062222/56815748550346895dc4eab9/html5/thumbnails/28.jpg)
© 2008 Wayne WolfOverheads for Computers as
Components 2nd ed.
LED
• Must use resistor to limit current:
28
![Page 29: Bus-Based Computer Systems](https://reader035.fdocuments.net/reader035/viewer/2022062222/56815748550346895dc4eab9/html5/thumbnails/29.jpg)
© 2008 Wayne WolfOverheads for Computers as
Components 2nd ed.
7-segment LCD display
• May use parallel or multiplexed input.
29
![Page 30: Bus-Based Computer Systems](https://reader035.fdocuments.net/reader035/viewer/2022062222/56815748550346895dc4eab9/html5/thumbnails/30.jpg)
© 2008 Wayne WolfOverheads for Computers as
Components 2nd ed.
Types of high-resolution display
• Liquid crystal display (LCD) is dominant form.
• Plasma, OLED, etc.• Frame buffer holds current display
contents.• Written by processor.• Read by video.
30
![Page 31: Bus-Based Computer Systems](https://reader035.fdocuments.net/reader035/viewer/2022062222/56815748550346895dc4eab9/html5/thumbnails/31.jpg)
© 2008 Wayne WolfOverheads for Computers as
Components 2nd ed.
Touchscreen
• Includes input and output device.• Input device is a two-dimensional
voltmeter:
31
![Page 32: Bus-Based Computer Systems](https://reader035.fdocuments.net/reader035/viewer/2022062222/56815748550346895dc4eab9/html5/thumbnails/32.jpg)
© 2008 Wayne WolfOverheads for Computers as
Components 2nd ed.
Touchscreen position sensing
ADC
voltage
32
![Page 33: Bus-Based Computer Systems](https://reader035.fdocuments.net/reader035/viewer/2022062222/56815748550346895dc4eab9/html5/thumbnails/33.jpg)
© 2008 Wayne WolfOverheads for Computers as
Components 2nd ed.
Digital-to-analog conversion
• Use resistor tree:
R
2R
4R
8R
bn
bn-1
bn-2
bn-3
Vout
33
![Page 34: Bus-Based Computer Systems](https://reader035.fdocuments.net/reader035/viewer/2022062222/56815748550346895dc4eab9/html5/thumbnails/34.jpg)
© 2008 Wayne WolfOverheads for Computers as
Components 2nd ed.
Flash A/D conversion
• N-bit result requires 2n comparators:
encoder
Vin
...
34
![Page 35: Bus-Based Computer Systems](https://reader035.fdocuments.net/reader035/viewer/2022062222/56815748550346895dc4eab9/html5/thumbnails/35.jpg)
© 2008 Wayne WolfOverheads for Computers as
Components 2nd ed.
Dual-slope conversion
• Use counter to time required to charge/discharge capacitor.
• Charging, then discharging eliminates non-linearities.
Vintimer
35
![Page 36: Bus-Based Computer Systems](https://reader035.fdocuments.net/reader035/viewer/2022062222/56815748550346895dc4eab9/html5/thumbnails/36.jpg)
© 2008 Wayne WolfOverheads for Computers as
Components 2nd ed.
Sample-and-hold
• Samples data:
converterVin
36