Building a CPU - Swarthmore Collegebryce/cs31/f16/slides/w03b_CPU.pdf · Data Memory We’re...
Transcript of Building a CPU - Swarthmore Collegebryce/cs31/f16/slides/w03b_CPU.pdf · Data Memory We’re...
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BuildingaCPU9/15/16
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opcode
X
Y
XopY
flags
AbstractionofyourLab3ALU:
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InsideyourLab3ALU:
opcode
X
Y
XopY
flags
+
-
<<
…MUX
FlagLogic
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CircuitsinsidetheALU
• Arithmeticcircuits• Generallyonecircuitforeachpossibleoperation.
• Controlcircuits• Selecttherightoutput• Setappropriateflags
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CircuitsaroundtheALU
• Wheredotheinputscomefrom?• X,Y• opcode
• Wheredotheoutputsgo?• XopY• Flags
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Recallfromlasttime…ThreemainclassificationsofHWcircuits:1. ALU:implementarithmetic&logicfunctionality
(ex)addertoaddtwovaluestogether
2. Storage:tostorebinaryvalues(ex)RegisterFile:setofCPUregisters
3. Control:support/coordinateinstructionexecution(ex)fetchthenextinstructiontoexecute
CircuitsarebuiltfromLogicGateswhicharebuiltfromtransistors
HW CircuitsLogic GatesTransistor
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Recallfromlasttime…ThreemainclassificationsofHWcircuits:
2. Storage:tostorebinaryvalues(ex)RegisterFile:setofCPUregisters
HW CircuitsLogic GatesTransistor
GivetheCPUa“scratchspace”toperformcalculationsandkeeptrackofthestateitsin.
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MemoryCircuits:StartingSmall
• Storea0or1
• Retrievethe0or1valueondemand(read)
• Setthe0or1valueondemand(write)
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R-SLatch:StoresValueQWhenRanSareboth1:Storeavalue
RandSareneverbothsimultaneously0
• Towriteanewvalue:• SetSto0momentarily(Rstaysat1):towritea1• SetRto0momentarily(Sstaysat1):towritea0
Q (valuestored)
~Q
S
R
R-SLatch
a
b
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GatedDLatchControlsS-Rlatchwriting,ensuresS&Rneverboth0
D:datawewanttostoreWE:write-enable:allowdatatobestored
Latchesusedinregisters(upnext)andSRAM(caches,later)Fast,notverydense,expensive
DRAM:capacitor-based:
Q (valuestored)
~Q
S
R
R-SLatchD
WE
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WhatgetsstoredwhenWE=1?
A. Q=0B. Q=1C. Q=DD. Q=~DE. Somethingelse.
Q
~Q
S
R
D
WE
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Registers
• Fixed-sizestorage(8-bit,32-bit,etc.)
• GatedDlatchletsusstoreonebit• ConnectNofthemtothesamewrite-enablewire!
Write-enable:
N-bitinputwires(bus):
N-bitRegisterBit0
Bit1
BitN-1
…
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“Registerfile”• AsetofregistersfortheCPUtostoretemporaryvalues.
• You(theprogrammer)candirectlyinteractwiththeregisterfile.
• Instructionsofform:• “addR1+R2,storeresultinR3”
32-bitRegister#0WEDatain
32-bitRegister#1WEDatain
32-bitRegister#2WEDatain
32-bitRegister#3WEDatain
…
MUX
MUX
RegisterFile
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MemoryCircuitSummary
• Lotsofabstractiongoingonhere!• Gateshidethedetailsoftransistors.• BuildR-SLatchesoutofgatestostoreonebit.• CombiningmultiplelatchesgivesusN-bitregister.• GroupingN-bitregistersgivesusregisterfile.
• Registerfile’ssimpleinterface:• ReadRx’svalue,useforcalculation• WriteRy’svaluetostoreresult
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Recallagain…ThreemainclassificationsofHWcircuits:1. ALU:implementarithmetic&logicfunctionality
(ex)addertoaddtwovaluestogether
2. Storage:tostorebinaryvalues(ex)RegisterFile:setofCPUregisters
3. Control:support/coordinateinstructionexecution(ex)fetchthenextinstructiontoexecute
CircuitsarebuiltfromLogicGateswhicharebuiltfromtransistors
HW CircuitsLogic GatesTransistor
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Recallagain…ThreemainclassificationsofHWcircuits:
3. Control:support/coordinateinstructionexecution(ex)fetchthenextinstructiontoexecute
HW CircuitsLogic GatesTransistor
Keeptrackofwhereweareintheprogram.Executeinstruction,movetonext.
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CPUsofar…
32-bitRegister#0WEDatain
32-bitRegister#1WEDatain
32-bitRegister#2WEDatain
32-bitRegister#3WEDatain
…
MUX
MUX
RegisterFile
ALU
Weknowhowtostoredata(inregisterfile).Weknowhowtoperformarithmeticonit,byfeedingittoALU.Remainingquestions:
Whichregister(s)doweuseasinputtoALU?WhichoperationshouldtheALUperform?Towhichregistershouldwestoretheresult?
Allthisinfocomesfromourcompiledprogram:aseriesofinstructions.
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Recall:VonNeumannModel
CPU(ControlandArithmetic)
Input/Output
ProgramandData
Memory
We’rebuildingthis.Ourprogram(instructions)livehere.We’llassumefornowthatwecanaccessitlikeanarray.
0:
1:
2:
3:
4:
…
N-1:
Mem Addresses(buckets)
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CPUGamePlan
• Fetchinstructionfrommemory
• Decodewhattheinstructionistellingustodo• TelltheALUwhatitshouldbedoing• Findthecorrectoperands
• Executetheinstruction(arithmetic,etc.)
• Storetheresult
![Page 20: Building a CPU - Swarthmore Collegebryce/cs31/f16/slides/w03b_CPU.pdf · Data Memory We’re building this. Our program (instructions) live here. We’ll assume for now that ... Load](https://reader033.fdocuments.net/reader033/viewer/2022050310/5f71b921156f525f2944fde7/html5/thumbnails/20.jpg)
ProgramState
32-bitRegister#0WEDatain
32-bitRegister#1WEDatain
32-bitRegister#2WEDatain
32-bitRegister#3WEDatain
…
MUX
MUX
RegisterFile
ALU
Let’saddtwomorespecialregisters(notinregisterfile)tokeeptrackofprogram.
ProgramCounter(PC): Memoryaddressofnextinstr 0:
1:
2:
3:
4:
…
N-1:
(Memory)
InstructionRegister(IR): Instruction contents(bits)
![Page 21: Building a CPU - Swarthmore Collegebryce/cs31/f16/slides/w03b_CPU.pdf · Data Memory We’re building this. Our program (instructions) live here. We’ll assume for now that ... Load](https://reader033.fdocuments.net/reader033/viewer/2022050310/5f71b921156f525f2944fde7/html5/thumbnails/21.jpg)
Fetchinginstructions.
32-bitRegister#0WEDatain
32-bitRegister#1WEDatain
32-bitRegister#2WEDatain
32-bitRegister#3WEDatain
…
MUX
MUX
RegisterFile
ALU
LoadIRwiththecontentsofmemoryattheaddressstoredinthePC.
ProgramCounter(PC): Address0 0:
1:
2:
3:
4:
…
N-1:
(Memory)
InstructionRegister(IR): InstructionatAddress0
![Page 22: Building a CPU - Swarthmore Collegebryce/cs31/f16/slides/w03b_CPU.pdf · Data Memory We’re building this. Our program (instructions) live here. We’ll assume for now that ... Load](https://reader033.fdocuments.net/reader033/viewer/2022050310/5f71b921156f525f2944fde7/html5/thumbnails/22.jpg)
Decodinginstructions.
32-bitRegister#0WEDatain
32-bitRegister#1WEDatain
32-bitRegister#2WEDatain
32-bitRegister#3WEDatain
…
MUX
MUX
RegisterFile
ALU
Interprettheinstructionbits:Whatoperation?Whicharguments?
ProgramCounter(PC): Address0 0:
1:
2:
3:
4:
…
N-1:
(Memory)
InstructionRegister(IR): OPCode|Reg A|Reg B|Result
![Page 23: Building a CPU - Swarthmore Collegebryce/cs31/f16/slides/w03b_CPU.pdf · Data Memory We’re building this. Our program (instructions) live here. We’ll assume for now that ... Load](https://reader033.fdocuments.net/reader033/viewer/2022050310/5f71b921156f525f2944fde7/html5/thumbnails/23.jpg)
Decodinginstructions.
32-bitRegister#0WEDatain
32-bitRegister#1WEDatain
32-bitRegister#2WEDatain
32-bitRegister#3WEDatain
…
MUX
MUX
RegisterFile
ALU
Interprettheinstructionbits:Whatoperation?Whicharguments?
ProgramCounter(PC): Address0 0:
1:
2:
3:
4:
…
N-1:
(Memory)
InstructionRegister(IR): OPCode|Reg A|Reg B|Result
OPCodetellsALUwhichoperationtoperform.
![Page 24: Building a CPU - Swarthmore Collegebryce/cs31/f16/slides/w03b_CPU.pdf · Data Memory We’re building this. Our program (instructions) live here. We’ll assume for now that ... Load](https://reader033.fdocuments.net/reader033/viewer/2022050310/5f71b921156f525f2944fde7/html5/thumbnails/24.jpg)
Decodinginstructions.
32-bitRegister#0WEDatain
32-bitRegister#1WEDatain
32-bitRegister#2WEDatain
32-bitRegister#3WEDatain
…
MUX
MUX
RegisterFile
ALU
Interprettheinstructionbits:Whatoperation?Whicharguments?
ProgramCounter(PC): Address0 0:
1:
2:
3:
4:
…
N-1:
(Memory)
InstructionRegister(IR): OPCode|Reg A|Reg B|Result
RegisterID#’sspecifyinputarguments.
![Page 25: Building a CPU - Swarthmore Collegebryce/cs31/f16/slides/w03b_CPU.pdf · Data Memory We’re building this. Our program (instructions) live here. We’ll assume for now that ... Load](https://reader033.fdocuments.net/reader033/viewer/2022050310/5f71b921156f525f2944fde7/html5/thumbnails/25.jpg)
Executinginstructions.
32-bitRegister#0WEDatain
32-bitRegister#1WEDatain
32-bitRegister#2WEDatain
32-bitRegister#3WEDatain
…
MUX
MUX
RegisterFile
ALU
Interprettheinstructionbits:Whatoperation?Whicharguments?
ProgramCounter(PC): Address0 0:
1:
2:
3:
4:
…
N-1:
(Memory)
InstructionRegister(IR): OPCode|Reg A|Reg B|Result
LettheALUdoitsthing.(e.g.,Add)
![Page 26: Building a CPU - Swarthmore Collegebryce/cs31/f16/slides/w03b_CPU.pdf · Data Memory We’re building this. Our program (instructions) live here. We’ll assume for now that ... Load](https://reader033.fdocuments.net/reader033/viewer/2022050310/5f71b921156f525f2944fde7/html5/thumbnails/26.jpg)
Storingresults.
32-bitRegister#0WEDatain
32-bitRegister#1WEDatain
32-bitRegister#2WEDatain
32-bitRegister#3WEDatain
…
MUX
MUX
RegisterFile
ALU
We’vejustcomputedsomething.Wheredoweputit?
ProgramCounter(PC): Address0 0:
1:
2:
3:
4:
…
N-1:
(Memory)
InstructionRegister(IR): OPCode|Reg A|Reg B|Result
ResultlocationspecifieswheretostoreALUoutput.
![Page 27: Building a CPU - Swarthmore Collegebryce/cs31/f16/slides/w03b_CPU.pdf · Data Memory We’re building this. Our program (instructions) live here. We’ll assume for now that ... Load](https://reader033.fdocuments.net/reader033/viewer/2022050310/5f71b921156f525f2944fde7/html5/thumbnails/27.jpg)
Whydoweneedaprogramcounter?Can’twejuststartat0andcountuponeatatimefromthere?
A. Wedon’t,it’sthereforconvenience.
B. SomeinstructionsmightskipthePCforwardbymore
thanone.
C. SomeinstructionsmightadjustthePCbackwards.
D. WeneedthePCforsomeotherreason(s).
![Page 28: Building a CPU - Swarthmore Collegebryce/cs31/f16/slides/w03b_CPU.pdf · Data Memory We’re building this. Our program (instructions) live here. We’ll assume for now that ... Load](https://reader033.fdocuments.net/reader033/viewer/2022050310/5f71b921156f525f2944fde7/html5/thumbnails/28.jpg)
Storingresults.
32-bitRegister#0WEDatain
32-bitRegister#1WEDatain
32-bitRegister#2WEDatain
32-bitRegister#3WEDatain
…
MUX
MUX
RegisterFile
ALU
Interprettheinstructionbits:Whatoperation?Whicharguments?
ProgramCounter(PC): Address0 0:
1:
2:
3:
4:
…
N-1:
(Memory)
InstructionRegister(IR): OPCode|Reg A|Reg B|Result
Resultmightbe:MemoryRegisterPC
![Page 29: Building a CPU - Swarthmore Collegebryce/cs31/f16/slides/w03b_CPU.pdf · Data Memory We’re building this. Our program (instructions) live here. We’ll assume for now that ... Load](https://reader033.fdocuments.net/reader033/viewer/2022050310/5f71b921156f525f2944fde7/html5/thumbnails/29.jpg)
RecapCPUModel
32-bitRegister#0WEDatain
32-bitRegister#1WEDatain
32-bitRegister#2WEDatain
32-bitRegister#3WEDatain
…
MUX
MUX
RegisterFile
ALU
Fourstages:fetchinstruction,decodeinstruction,execute,storeresult
ProgramCounter(PC): Memoryaddressofnextinstr 0:
1:
2:
3:
4:
…
N-1:
(Memory)
InstructionRegister(IR): Instruction contents(bits)
![Page 30: Building a CPU - Swarthmore Collegebryce/cs31/f16/slides/w03b_CPU.pdf · Data Memory We’re building this. Our program (instructions) live here. We’ll assume for now that ... Load](https://reader033.fdocuments.net/reader033/viewer/2022050310/5f71b921156f525f2944fde7/html5/thumbnails/30.jpg)
Fetchinginstructions.
32-bitRegister#0WEDatain
32-bitRegister#1WEDatain
32-bitRegister#2WEDatain
32-bitRegister#3WEDatain
…
MUX
MUX
RegisterFile
ALU
LoadIRwiththecontentsofmemoryattheaddressstoredinthePC.
ProgramCounter(PC): Address0 0:
1:
2:
3:
4:
…
N-1:
(Memory)
InstructionRegister(IR): InstructionatAddress0
![Page 31: Building a CPU - Swarthmore Collegebryce/cs31/f16/slides/w03b_CPU.pdf · Data Memory We’re building this. Our program (instructions) live here. We’ll assume for now that ... Load](https://reader033.fdocuments.net/reader033/viewer/2022050310/5f71b921156f525f2944fde7/html5/thumbnails/31.jpg)
Decodinginstructions.
32-bitRegister#0WEDatain
32-bitRegister#1WEDatain
32-bitRegister#2WEDatain
32-bitRegister#3WEDatain
…
MUX
MUX
RegisterFile
ALU
Interprettheinstructionbits:Whatoperation?Whicharguments?
ProgramCounter(PC): Address0 0:
1:
2:
3:
4:
…
N-1:
(Memory)
InstructionRegister(IR): OPCode|Reg A|Reg B|Result
![Page 32: Building a CPU - Swarthmore Collegebryce/cs31/f16/slides/w03b_CPU.pdf · Data Memory We’re building this. Our program (instructions) live here. We’ll assume for now that ... Load](https://reader033.fdocuments.net/reader033/viewer/2022050310/5f71b921156f525f2944fde7/html5/thumbnails/32.jpg)
Decodinginstructions.
32-bitRegister#0WEDatain
32-bitRegister#1WEDatain
32-bitRegister#2WEDatain
32-bitRegister#3WEDatain
…
MUX
MUX
RegisterFile
ALU
Interprettheinstructionbits:Whatoperation?Whicharguments?
ProgramCounter(PC): Address0 0:
1:
2:
3:
4:
…
N-1:
(Memory)
InstructionRegister(IR): OPCode|Reg A|Reg B|Result
OPCodetellsALUwhichoperationtoperform.
![Page 33: Building a CPU - Swarthmore Collegebryce/cs31/f16/slides/w03b_CPU.pdf · Data Memory We’re building this. Our program (instructions) live here. We’ll assume for now that ... Load](https://reader033.fdocuments.net/reader033/viewer/2022050310/5f71b921156f525f2944fde7/html5/thumbnails/33.jpg)
Decodinginstructions.
32-bitRegister#0WEDatain
32-bitRegister#1WEDatain
32-bitRegister#2WEDatain
32-bitRegister#3WEDatain
…
MUX
MUX
RegisterFile
ALU
Interprettheinstructionbits:Whatoperation?Whicharguments?
ProgramCounter(PC): Address0 0:
1:
2:
3:
4:
…
N-1:
(Memory)
InstructionRegister(IR): OPCode|Reg A|Reg B|Result
RegisterID#’sspecifyinputarguments.
![Page 34: Building a CPU - Swarthmore Collegebryce/cs31/f16/slides/w03b_CPU.pdf · Data Memory We’re building this. Our program (instructions) live here. We’ll assume for now that ... Load](https://reader033.fdocuments.net/reader033/viewer/2022050310/5f71b921156f525f2944fde7/html5/thumbnails/34.jpg)
Executinginstructions.
32-bitRegister#0WEDatain
32-bitRegister#1WEDatain
32-bitRegister#2WEDatain
32-bitRegister#3WEDatain
…
MUX
MUX
RegisterFile
ALU
Interprettheinstructionbits:Whatoperation?Whicharguments?
ProgramCounter(PC): Address0 0:
1:
2:
3:
4:
…
N-1:
(Memory)
InstructionRegister(IR): OPCode|Reg A|Reg B|Result
LettheALUdoitsthing.(e.g.,Add)
![Page 35: Building a CPU - Swarthmore Collegebryce/cs31/f16/slides/w03b_CPU.pdf · Data Memory We’re building this. Our program (instructions) live here. We’ll assume for now that ... Load](https://reader033.fdocuments.net/reader033/viewer/2022050310/5f71b921156f525f2944fde7/html5/thumbnails/35.jpg)
Storingresults.
32-bitRegister#0WEDatain
32-bitRegister#1WEDatain
32-bitRegister#2WEDatain
32-bitRegister#3WEDatain
…
MUX
MUX
RegisterFile
ALU
Interprettheinstructionbits:Storeresultinregister,memory,PC.
ProgramCounter(PC): Address0 0:
1:
2:
3:
4:
…
N-1:
(Memory)
InstructionRegister(IR): OPCode|Reg A|Reg B|Result
Resultmightbe:MemoryRegisterPC
![Page 36: Building a CPU - Swarthmore Collegebryce/cs31/f16/slides/w03b_CPU.pdf · Data Memory We’re building this. Our program (instructions) live here. We’ll assume for now that ... Load](https://reader033.fdocuments.net/reader033/viewer/2022050310/5f71b921156f525f2944fde7/html5/thumbnails/36.jpg)
Clocking
• Needtoperiodicallytransitionfromoneinstructiontothenext.
• Ittakestimetofetchfrommemory,forsignaltopropagatethroughwires,etc.• Toofast:don’tfullycomputeresult• Tooslow:wastetime
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ClockDrivenSystem• Everythinginisdrivenbyadiscreteclock• clock:anoscillatorcircuit,generateshilowpulse• clockcycle:onehi-lowpair
• Clockdetermineshowfastsystemruns• Processorcanonlydoonethingperclockcycle
• Usuallyjustonepartofexecutinganinstruction• 1GHzprocessor:
1billioncycles/secondà 1cycleeverynanosecond
Clock
1cycle
1 0 1 0 1 0 1 0 1 0
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ClockandCircuitsClockEdgesTriggersevents• Circuitshavecontinuousvalues• RisingEdge:triggernewinputvalues• FallingEdge:consistentoutputreadytoread• Betweenrisingandfallingedgecanhaveinconsistentstateasnewinputvaluesflowthroughcircuit
^ newinput
^ outputready
^ newinput
Clock:
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Timeperinstruction:LaundryAnalogy
• Discretestages:fetch,decode,execute,store
• Analogy(laundry):washer,dryer,folding,dresser
W Dy F Dr
4 Hours
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LaundryW Dy F Dr
4 Hours
W Dy F Dr
4 Hours
W Dy F Dr
4 Hours
4-hourcycletime.
Finishesalaundryloadeverycycle.
(6laundryloadsperday)
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Pipelining(Laundry)
DyW
FDyW
DrFDyW
DrFDyW
W
1Hour
1st hour:
2nd hour:
3rd hour:
4th hour:
5th hour:
Steadystate:Oneloadfinisheseveryhour!(Noteveryfourhourslikebefore.)
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DF
EDF
SEDF
SEDF
F
1Nanosecond
1st nanosecond:
2nd nanosecond:
3rd nanosecond:
4th nanosecond:
5th nanosecond:
Steadystate:Oneinstructionfinisheseverynanosecond!(Clockratecanbefaster.)
CPUStages:fetch,decode,execute,storeresults
Pipelining(CPU)
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Pipelining
(Formoredetailsaboutthisandtheotherthingswetalkedabouthere,takearchitecture.)
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Comingupnextweek…
• TalkingtotheCPU:Assemblylanguage