BSc Thesis JBB

8/13/2019 BSc Thesis JBB

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Pipelined ADC

-Design of low-power, highspeed A/D converter in CMOS technology

s052435, Jonas Benjamin Borch

Bachelorproject, ElektroDTU, January 2009Technical University of Denmark


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Preface

This paper is written as part of the requirements for completing the bachelor study inscience (BScE) at the Technical University of Denmark (DTU).

This report represent 15 ECTS points.

It is assumed that the reader has a understanding of both analog and digital electronics.

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Abstract

There are many different types of ADC structures, one of these is the Pipelined ADC,which is characterised by having relative high speed, with a low area- and power consump-tion.The purpose of this project is to design a 10-bit 40 Msample/s Pipelined ADC down to gateand transistor level. The CAD tool Cadence is used to validate the design by simulation.This paper contains a short theoretical section, an analysis of the pipeline structure and ofthe individual components. With implementation and simulation of the essential compo-nents. It should be possible, with some additional work, to construct a fully simulateable

pipelined ADC. The paper therefore contains proposals to further analysis and developmentof the design.

Thanks to

Special thanks goes out to

Erik Bruun - Main project supervisor. Allan Jrgensen - Invaluable assistance with Cadence and other software. Jose Custodio - General help with project related problems.

Friends and family for keeping up with long periods of isolation and absence.

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Contents

1 Thesis Statement 7

2 Project description 9

3 Theory 11

3.1 Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.2 Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2.1 Flash converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143.2.2 Pipelined converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4 Design analysis 17

4.1 Overall structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174.1.1 Stage resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174.1.2 Design limitations and noise . . . . . . . . . . . . . . . . . . . . . . 184.1.3 General structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.2 Pipeline-stage structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194.2.1 1.5-bit subADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204.2.2 MDAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3 Delay structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254.4 Digital error correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254.5 Final design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5 Transistor analysis 295.1 NMOS threshold voltageVtn . . . . . . . . . . . . . . . . . . . . . . . . . . 295.2 NMOS nCox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295.3 PMOS Vtp and pCox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6 Implementation and results 33

6.0.1 General requirements . . . . . . . . . . . . . . . . . . . . . . . . . . 336.1 1.5-bit subADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.1.1 Differential pair comparator . . . . . . . . . . . . . . . . . . . . . . 346.1.2 Reference voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.1.3 Output logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

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CONTENTS

6.1.4 Final testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6.2 2-bit subADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386.3 MDAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.3.1 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426.3.2 Folded-Cascode Opamp . . . . . . . . . . . . . . . . . . . . . . . . 426.3.3 Common-Mode FeedBack . . . . . . . . . . . . . . . . . . . . . . . 466.3.4 Bit-logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466.3.5 Final testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

6.4 Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476.5 Digital error correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7 Further work 51

8 Conclusion 53

Bibliography 55

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List of Figures

3.1 The schematic symbols of the CMOS transistors . . . . . . . . . . . . . . . 11

3.2 Physical structure of a NMOS transistor . . . . . . . . . . . . . . . . . . . 123.3 Current iD versus vDSfor different vGS . . . . . . . . . . . . . . . . . . . . 133.4 Large signal equivalent of a NMOS transistor . . . . . . . . . . . . . . . . 133.5 General structure of a Flash ADC . . . . . . . . . . . . . . . . . . . . . . . 143.6 General structure of a Pipelined ADC . . . . . . . . . . . . . . . . . . . . . 153.7 Pipeline stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.1 Traditional structure of a 1.5-bit pipeline stage . . . . . . . . . . . . . . . . 194.2 New structure of a 1.5-bit pipeline stage . . . . . . . . . . . . . . . . . . . 204.3 Structure of a 1.5-bit flash converter . . . . . . . . . . . . . . . . . . . . . 214.4 Error generated by the comparator circuit . . . . . . . . . . . . . . . . . . 214.5 Structure of a switch cap. circuit . . . . . . . . . . . . . . . . . . . . . . . 234.6 Timing diagram for the MDAC circuit . . . . . . . . . . . . . . . . . . . . 234.7 Structure of the MDAC circuit . . . . . . . . . . . . . . . . . . . . . . . . . 244.8 The final structure of the pipeline . . . . . . . . . . . . . . . . . . . . . . . 26

5.1 Testbench for NMOS transistor analysis . . . . . . . . . . . . . . . . . . . 295.2 Graph ofVDSversusID, of a NMOS transistor . . . . . . . . . . . . . . . . 305.3 Graph ofVDSversus

ID, of a NMOS transistor . . . . . . . . . . . . . . . 31

5.4 Testbench for PMOS transistor analysis . . . . . . . . . . . . . . . . . . . . 31

6.1 The final structure of the 1.5-bit subADC . . . . . . . . . . . . . . . . . . 346.2 Differential pair comparator . . . . . . . . . . . . . . . . . . . . . . . . . . 356.3 Simulation with the high and low comparator output . . . . . . . . . . . . 366.4 Resistorstring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376.5 1.5-bit subADC output logic . . . . . . . . . . . . . . . . . . . . . . . . . . 386.6 1.5-bit simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396.7 The final structure of the 2-bit subADC . . . . . . . . . . . . . . . . . . . 406.8 Simulation with mid range comparatorC3 . . . . . . . . . . . . . . . . . . 406.9 Resistor values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416.10 Resistorstring diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.11 1.5-bit subADC output logic . . . . . . . . . . . . . . . . . . . . . . . . . . 42

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LIST OF FIGURES

6.12 Implementation of switches . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

6.13 Implementation of a fully differential opamp . . . . . . . . . . . . . . . . . 456.14 Magnitude and phase of the OTA with 50f F load . . . . . . . . . . . . . . 456.15 Switch cap. implementation of the CMFB circuit . . . . . . . . . . . . . . 466.16 The MDAC bit-logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476. 17 A D - ty pe Fl i p- Fl op . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476.19 A Full Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476.18 DFF implementation of the delay component . . . . . . . . . . . . . . . . . 486.20 Full adder implementation of the error correction algorithm . . . . . . . . . 49

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List of Tables

4.1 subADB output logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.2 DAC bit logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254.3 Example of digital error correction . . . . . . . . . . . . . . . . . . . . . . 264.4 A summary of the relation between the different signals in a pipeline stage 27

6.1 Summation of the general requirements . . . . . . . . . . . . . . . . . . . . 346.2 Differential pair comparator transistor dimensions . . . . . . . . . . . . . . 366.3 Fully differential subADB output logic . . . . . . . . . . . . . . . . . . . . 386.4 Fully differential subADB output logic . . . . . . . . . . . . . . . . . . . . 41

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LIST OF TABLES

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Chapter 1

Thesis Statement

This projects deals with the design of a low-power, high speed A/D converter in CMOStechnology. For the architecture, a pipeline converter may be selected since this archi-tectures provides a compromise between power and speed. The converter should have aconversion speed of about 40 Msamples/s and a resolution of 10 bits. Trade-offs betweenspeed, power consumption, resolution and area consumption should be investigated. Theconverter should be implemented in a standard submicron CMOS process, and the designshould comprise both an analytical investigation and a simulation using the Cadence de-sign system.

It is suggested that the converter design is preceded by the design of a simple opampin order to get familiar with the design system and the selected CMOS process.1

1

A separate paper has covered this, and will therefore not be part of this paper

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CHAPTER 1. THESIS STATEMENT

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Chapter 2

Project description

This chapter is a short introduction to how this paper will treat the given thesis statement.

To start with there will be a short introduction to the basic principles behind the CMOStransistors and the AD converters.Next will be the design analysis, which will include a overall technical analysis of the giventhesis statement and of its requirements. From here a in depth analysis of the individualsegments of the design will the treated. Several design options will be proposed anddiscussed.Next will be a short practical analysis of the transistor technology used in this paper. Here

after follows the implantation and simulation of the design. Lastly there will be a sectionon further work on the design. This will include what has been left out, not completedand further development of the initial design.An in depth analysis and implementation is outside the scope of this project. The focuswill be on the structure of the overall design and its components.

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CHAPTER 2. PROJECT DESCRIPTION

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Chapter 3

Theory

This chapter contains a short summation of the fundamental theories, used in this report.First general transistor theory, then the fundamentals behind Analog-to-Digital converters,along with a description of principles behind the Pipelined ADC, and lastly a descriptionof some of the designs restricting factors.

This chapter is optional reading, if the reader is familiar with integrated circuitry, sinceit mainly covers general theory.

3.1 TransistorA basic CMOS transistor is a three-terminal semiconductor device, which is able to changea voltage or current applied to a pair of terminals, by applying a change on the thirdterminal.

The NMOS transistor, seen in figure 3.1, has a Drain (D), Source (S) and Gate (G)terminal. The gate terminal is used to control the connection between the drain and source.With this structure, there ideally does not run any current between the drain-source con-

S

D

G

(a)NMOS

G

S

D

(b)PMOS

Figure 3.1: The schematic symbols of the CMOS transistors

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CHAPTER 3. THEORY

0000000000011111111111

S DG

ntype ntype

ptype

L

metal

ptype

W

D

metal ntype

S G D

Figure 3.2: Physical structure of a NMOS transistor

nection and the gate terminal.The dimensions of the transistor is largely described by the length (L) and width (W) ofthe gate metal. The overall structure is the same for PMOS transistors, though here thedrain and source wells are p-type regions in a n-type well, which changes the gate terminalseffect on the drain-source connection.

In circuit schematics, the CMOS transistors can look like figure 3.1, though there aremany variations of these symbols. The current running through the drain-source connec-tion iD depend greatly upon the relation between the drain-source vDS and gate-sourcevGS voltage. If vDS < vGS

Vt then the transistor is said to be in triode region. If

vDS> vGS Vt then the transistor is in saturation region.[8]

Triode region:

iD =1

2Cox

W

L

((vGS Vt)vDS

1

2v2DS) (3.1)

Saturation region:

iD =1

2Cox

W

L

(vGS Vt)2(1 + (vDS Veff)) (3.2)

WhereCox are technology specific constants, and vt is the threshold voltage. The actualrelation between the drain current iD and the drain-source voltage vDS at different vGSvalues, can be seen in figure 3.3.At high vDSvalues the short-channel effect starts to be significant and the expression forthe current becomes more complex.

To simplify the expression for iD, it can be assumed that the transistors are driven inthe lower part of saturation region, and therefore Veff = vDS so that the channel-lengthmodulation in the formula disappears and equation (3.2) becomes:

iD =

1

2CoxW

L

(vGS Vt)2

(3.3)

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CHAPTER 3. THEORY

Figure 3.3: Current iD versus vDSfor different vGS

Figure 3.4: Large signal equivalent of a NMOS transistor

(vGS Vt) is also called the overdrive voltage vOV. The transistor can also be representedin a circuit as a large-signal equivalent model, as seen in figure 3.4. Here the transistorhas been replaced by a voltage controlled current source and a resistor r0. gm is the

transconductrance and is defined as gm= 2Cox WL iD.

3.2 Analog-to-Digital Converter

This report will deal with two types of data converters, both Analog-to-Digital Converters(ADC) and Digital-to-Analog Converters (DAC). Where, as the title of the paper implies,the overall focus is on the pipelined ADC design.

ADCs are used in many different applications, and therefore the requirements will differa lot. Throughout the evolution of the transistor technology the design of the ADCs haschanged accordingly. In this report two different ADC structures will be applied, the Flash

structure and the Pipelined structure.

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CHAPTER 3. THEORY

N2

R

R

inV

Vref

ENCODER

Nbit signal

3R/2

R/2

1 comparators

+

+

+

Figure 3.5: General structure of a Flash ADC

3.2.1 Flash converter

The flash converter, also called a parallel converter, is the standard structure for realisinga very high speed converter. The structure, as seen in figure 3.5, is based upon a arrayof comparators with a reference voltage, which in this case derived is from a resistorchain. One of the major drawbacks of this structure is, that it with every additional bitof resolution doubles the number of comparators, and thereby its area consumption. A Nbit converter will, as a result of this, need N2 1 comparators. Though the latency of theconvert is close to constant with increasing resolution, the power and area consumption of

the design is largely the limiting factor of this type.

3.2.2 Pipelined converter

The pipelined converter is the main focus in this paper. Only the overall principle of theconverter will be summarised in this section.The pipelined ADC is a clocked converter, meaning that the input is sampled and thenconverted. It is comprised of a series of stages, where the sampled analog signal is clockedtrough and gradually converted, as seen in figure 3.6. Each stage produce a digital outputfrom a sub-ADC of low resolution, which in most cases is based on the flash structure.

This digital output is then stored in registers until the analog signal has passed through

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CHAPTER 3. THEORY

Analog input

Stage 1

Delay

Stage 2 Stage M

NBit NBit NBit

Digital output

Figure 3.6: General structure of a Pipelined ADC

S/HVN

X2

+

+inV

Nbit

subADC

Nbit

DAC

Nbit

out

Figure 3.7: Pipeline stages

all the stages.The functionality each individual stage is(as seen in figure 3.7), first sampling and holding(S/H) the input signal, then preforming a low resolution conversion into digital signals.Which is done by the small flash subADC. The digital signal is then stored in a delaycomponent and also sent into a DAC and converted back into a analog signal. This analogsignal is then subtracted from the original input signal, the resulting residue is lastlymultiplied and put on the output. The multiplication is determined by the number of bitsresolution of the subADC.

The advantages of the pipelined structure lies in the predefined latency and highthroughput. In most applications such as data transmission, the high latency is not aproblem. The pipelined structure will not be a suitable solution if an application needsnear realtime measurements.

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CHAPTER 3. THEORY

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Chapter 4

Design analysis

This chapter will cover the design analysis of the proposed pipelined ADC.First the overall design requirements from the thesis statement is analysed, so their impacton the overall design is clear. Then the different design-options and designs of the individualparts, in the ADC will be presented and analysed.

4.1 Overall structure

Form the thesis statement in chapter 1, the objective is given, to design a 10-bit 40 Msam-

ple/s pipelined ADC. The basic structure of the pipelined ADC is described in chapter3.2.2.The pipelined structure gives room for many design variations. It is therefore possible torealise an optimal implementation of the design, which meet the given requirements. Thedesign has to balance the tradeoff between speed, power and area consumption.

4.1.1 Stage resolution

The most obvious way to implement the 10-bit resolution, would be a two staged pipeline

with 5-bit resolution in each stage. This will result in a very low latency, since the signalonly has to pass through two stages. However since a predefined latency isnt a big concernin most applications, the advantage of low latency wouldnt compensate for the fact, thatthe gain bandwidth of the multiplier in each stage has to be very large, in order to realisea multiplication by 32 (25). Since it is generally hard to realise a high-gain high-speedamplifier, it would be more sensible to reduce the resolution of the stages.The most well know implementation of a pipelined ADC is with 3-bit stages [5]. Thiscould be done with three 3-bit stages and a small 1-bit ADC at the end. A improvementof this is the 5-bit design. This however still has the issue with the speed requirementsof the multiply by 8 (23), even though it is better than the multiply by 32. In relation

to area consumption the 5-bit realisation has a smaller overall area consumption, though

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CHAPTER 4. DESIGN ANALYSIS

the individual stage is significantly larger. This is mostly because of the increase in the

number of comparators in the subADC component. The overall power consumption willinadvertently be larger with more stages. It is therefore counterproductive in relation tothe implementation of a low power design, to have more stages. To gain more speed theresolution of the stages has to be reduced.A solution to the multiplier problem is to lower the resolution of each stage to 1.5-bit. Thenthe 1.5-bit stage is basically a 1-bit converter with some redundancy build into. Digitalerror correction is used in order to compensate for inaccuracies in the components, andgive a larger tolerance. This will be covered later.There is only need for a multiply-by-2 with this 1.5-bit structure. This will significantlylower the requirements for the amplifier, and thereby reducing the complexity of the im-

plementation. Each stage will not take up much area on the wafer. But with a minimumof 6 stages plus a small 1-bit converter at the end of the pipeline, the overall area con-sumption will be larger than with higher stage resolutions. Also with the higher tolerance,the precision requirements will be less significant.

4.1.2 Design limitations and noise

Though this paper does not directly deal with external noise, it cannot be ignored alto-gether in the overall design, especially when the limitations can end up effecting the finaldesign.

In the pipelined structure, the noise generated in each stage will end up being amplifiedand feed through to the next state, and thereby lowering the signal to noise ratio (SNR) ofthe original signal. In a worst case scenario the signal in the later stages will be so degraded,that it is no longer useful. This in turn puts higher requirement upon the linearity of theS/H and the multiplier in each stage and the fact that the amplifiers have finite gain.The most immediate limitation on this design is offset errors and unlinearity in the stages.In practical designs kT/C thermal-noise and noise from the power supply should also beconsidered.Charge injection is also something to consider, especially when dealing with transistorsimplemented as switches. Charge injection occurs when the parasitic capacitance of the

transistor is transferred to the ordinary circuits.

4.1.3 General structure

Since inaccuracies in the design is an undeniable reality, there is a need to make the struc-ture robust enough, to insure that these inaccuracies does not affect the functionality ofthe converter. There are several approaches that could solve most of the problems.This paper focuses on digital error correction and fully differential circuitry, as means ofcorrecting the inaccuracies.In order to incorporate the low power aspect of the requirements, the design implementa-

tion will be realised with minimal transistor dimensions and low current flow. Also the use

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B1

outMDAC

1.5bit

subADC

Vin

B0

V

Figure 4.2: New structure of a 1.5-bit pipeline stage

4.2.1 1.5-bit subADC

The 1.5-bit subADC is based upon the flash converter principle, as presented in chapter3.2.1. To realise a 1.5-bit flash converter there will be needed two comparators and somedigital logic, as seen in figure 4.3.

It is assumed that a reference voltage VREFexist. This could be the upper and lowerrange of the converter. From this two symmetrical analog comparison levels are defined,VHandVL. These must be within the range of +VREF/2 and VREF/2 respectively. Withdigital error correction these two comparison levels can be moved closer together.To represent this three step range, a two bit signal will be needed, where MSB is B1 andLSB is B0. The error generated by the comparator circuit is illustrated in figure 4.4.

Components

This design consists of three different general components.

Resistors, that are somewhat accurate, for the reference voltages VH and VL.

Comparators, these need to be fast and not necessarily that accurate.

Output logic, for generation of output bits.

Resistors The only design requirement to these are that they must be accurateenough, so that the reference voltage for the comparators are correct. Another less impor-

tant design consideration is the area consumption of the resistor.

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[!b]C1 C2 B1 B0

0 0 0 00 1 0 11 0 X X1 1 1 0

Table 4.1: subADB output logic

Comparators The main purpose of a comparator is to compare two signals, andthen indicate which is the larges, by outputting a logic high or logic low.With the digital error correction the requirements to the accuracy of the comparators can

safely be lowered. This means that the traditional switch capacitor structure, with its highaccuracy, is not necessary. Another important design aspect is the power consumption. Inthe traditional switch cap. structure this can be optimised a great deal, but this will stillbe significant in therms of the overall power consumption, since each stage will containtwo comparators.Another comparator structure is the dynamic Lewis-Gray comparator, which is based upondifferential sensing amplifier, as described in [2]. Further development of this structure hasresulted in a differential pair implementation, which is more robust, as described in [4]. Oneof the great advantages of this structure is, that it has near zero DC power consumption,which makes it most suitable for the pipeline implementation.

Output logic The purpose of the output logic, is to translate the output of thetwo comparators into a 2-bit binary code. Since it is a 1.5-bit converter, there is threedifferent output combinations, since 2-bit binary can represent 4 states, the logic designwill therefore end up with a unknown state. The needed translation can be seen in table4.1.

4.2.2 MDAC

As previously stated the MDAC is a product of a simplification of the traditional stages

S/H circuit, subtractor, multiplier and DAC. As a result of this, the MDAC must includethe functionality of all the four components.This is achieved by modifying a switch capacitor sample and hold circuit [1, p. 842],asseen in figure 4.5.

Since the MDAC is based upon a S/H circuit, the S/H functionality is given. The DACfunctionality is implemented by a series of switches, that will be controlled by the outputof the subADC. The multiply by 2 function is achieved by adding a second capacitor CHparallel to the original sample capacitor CS. The subtraction is done by offsetting thevoltage acrossCSwith the DAC output. This new structure can be seen in figure 4.7.

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Figure 4.5: Structure of a switch cap. circuit

S

3

2

1

S

S

Figure 4.6: Timing diagram for the MDAC circuit

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Figure 4.7: Structure of the MDAC circuit

The MDAC is clocked similar to the switch cap. S/H, the timing diagram can be seenin figure 4.6. It can roughly be split up into two modes, the sampling mode and the am-plification mode.

In the sampling mode the input voltage is set across the capacitors and charged.

In the amplification mode the voltage over CSminus the DAC input is transferredto CH. The voltage from the input over CHto the output of the amplifier is now 2times input voltage minus the DAC output.

Components

The MDAC design consists of four different general components.

Operational amplifier (OPAMP), as discussed in chapter 4.1.1, has to be fast.

Switches, these need to be fast and in most cases go rail to rail.

Bit logic, one-hot encode the subADC output bits.

Capacitors, need to be accurate in order to prevent distortion.

Operational amplifier In general therms this needs to be fast, in other words theunity gain frequency has to be high enough to drive the MDAC switch cap. circuits capac-itors. A single stage opamp for a high speed implementation is the most comment choice[10][9]. Though more complex two stage amplifier also are used in some high speed designs[6]. Since the OPAMP only sees capacitive loads it is obvious to chose a transconductance

amplifier, such as the folded cascode architecture, described in [3, p. 266] .

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B1 B0 D0 D1 D2

0 0 1 0 00 1 0 1 01 0 0 0 11 1 X X X

Table 4.2: DAC bit logic

Switches The requirements for the switches differ according to their applications.The most simple switch, is a single small transistor with its gate connected to the con-trol signal. In a sensitive circuit, where precession is the object, charge-injection from

the transistors parasitic capacitance may be a problem. To solve this, a short circuiteddummy transistor can be introduced, [1, p. 832]. Another problem is the threshold voltage(Vt) of the transistors. It will limit how high and low the NMOS and PMOS transistorsrespectively can drive the voltage. A transmission gate (TG) solves this, by parallel couplea NMOS with a PMOS transistors.

In order to control the switches in the DAC, it is necessary to one-hot encode the 2-bit signal from the subADC. This is achieved by logic gates, following the requirementsdescribed in table 4.2.

Capacitors In general the smaller the capacitance are, the faster the system can

drive them. Also the larger the capacitors are, the larger the area consumption. Thereforethe capacitors should be implemented with small sizes in mind. Though with smallercapacitors, comes the risk of loosing accuracy to parasitic capacitance and thermal noise.

4.3 Delay structure

The purpose of the delay, is to insure that the output of the different stages are stored, untilall of the stages has analysed the signal, and then deliver it to the digital error correctioncomponent.This can be achieved with digital logic, since the bit values either are logic high or logiclow. The implementation of this will be discussed in a later chapter.

4.4 Digital error correction

Digital error correction is a way to digitally compensate for the inaccuracies in the circuitry.This is done by reducing the 1.5-bit signal from each state to a 1-bit signal. This willgreatly improve the tolerance of the system. In general therms the range between thehigh reference VH and the low reference VL, will be used as undefined area. So when thesubADC finds the signal to be in mid-rang interval, the algorithm will then use the next

stage to definitely set it as 1 or 0.

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1 0

0 10 0

1 0 1 0

Table 4.3: Example of digital error correction

S/H

B1 B00B1BB1 B00B1BB1 B00B1BB1 B00B1B

Digital error correction

Delay

output10bit

B1 B0

V IN 2bitADCS8S7S6S5S4S3S2S1S/H

Figure 4.8: The final structure of the pipeline

The algorithm behind the digital error correction is quite simple. The LSB of the previousstage is added to the MSB of the current stage.An example of how this works can be seen in figure 4.3.

4.5 Final design

With digital error detection the final structure will contain 8 stages of 1.5-bit stages the9th stage will be a 2-bit subADC based upon the 1.5-bit architecture, presented in chapter4.2.1. Also before the first stage there will be a sample and hold component, as presentedin chapter 4.2.2.The final structure of the pipeline can be seen in figure 4.8.

A summary of the relation between the different signals in the individual pipeline stagesis shown in table 4.4.

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Stage input Vin Level B1 B0 DAC output Stage output VoutVin< VL Low 0 0 Vref 2Vin+ Vref

VL< Vin< VH Mid 0 1 0 2Vin

Vin> VH High 1 0 +Vref 2Vin VrefTable 4.4: A summary of the relation between the different signals in a pipeline stage

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Chapter 5

Transistor analysis

In the section the NMOS and PMOS transistors will be analysed, i order to have the es-sential data, from where the different circuits can be constructed. The analysis for the twotransistors are almost the same. The analysis of the PMOS transistor will therefore notbe explained in detail.

The design in this paper is based upon the AMS035 technology, which is a 0 .35CMOStechnology.

5.1 NMOS threshold voltage Vtn

It is necessary to construct a simple testbench, seen in figure 5.1, in order to find thethreshold voltage Vtn for the NMOS transistors. Here the gate and drain is connectedtogether to a voltage source VDD, while the source is connected to the ground. This willinsure that the transistor will be in saturation region, until VDD drops below triode region.In this test the transistor dimensions are W

L = 10m

0.35m.

V

S

G

D

DD

Figure 5.1: Test-bench for NMOStransistor analysis

In order to get the transistors DC characteristics, the volt-age VDD is swept between 0 and 2V, so the current ID can

be plotted against the voltage across, as seen in figure 5.2.Where the graph last time seem to touch the x-axis is thevalueVtn.

Vtn is found to be roughly 0.6V.

5.2 NMOS nCox

The two technology constants nCox is found by using the same anal-

ysis as with Vtn. From equation (3.3) the drain current is given.

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CHAPTER 5. TRANSISTOR ANALYSIS

Figure 5.2: Graph ofVDSversusID, of a NMOS transistor

iD =1

2Cox

W

L

(vGS Vt)2 (5.1)

iD =

1

2nCox

W

L

(vGS Vt) (5.2)

The drain current squared can be seen in figure 5.3. The slope of

the graph must therefore be a =

1

2nCox

WL

. From points of the

graph, the slope can be calculated.

a= 19.42 103 9.642 1031.057 0.785 = 0.0359

AV

(5.3)

From the expression for the slope, it now possible to find nCox.

nCox= 2a2

L

W

= 2

0.0359

A

V

20.35m

10m

= 90.5

A

V2 (5.4)

5.3 PMOS Vtp and pCox

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Figure 5.3: Graph ofVDSversus

ID, of a NMOS transistor

V

S

G

D

DD

Figure 5.4: Test-

bench for PMOStransistor analysis

The PMOS transistor parameters are found much like the NMOS pa-rameters. The only real difference is the construction of the testbench,which can be seen i figure 5.41, and the voltage is swept between -2 and0 V. The result of the analysis, is Vtp = 0.75V and pCox= 31.2AV2

1

Note: In this diagram the transistor is upside down

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Chapter 6

Implementation and results

This chapter will cover the actual implement of the pipelined ADC. This mean, all theanalog circuits will be implemented on transistor level, and the digital circuits will be im-plemented on logic gate level.To verify the design the CAD tool Cadencewill be used for practical implementation andsimulation. For the logic gates the CAD software have technology optimized libraries,which will be used to build the digital circuits.

As described in chapter 4.5, the pipeline contains 8 ordinary 1.5-bit stages, a S/H cir-

cuit, a 2-bit subADC, a delay component and a digital error correction component. Eachstage can be split op in 1.5-bit subADC part and a MDAC part.

The S/H will, as described in chapter 4.2.2, be implemented as a simplified version onthe MDAC circuitry. It will contain the same basic components like the opamp, switchesand capacitors, even the system clock will be the same. The implementation of the S/H,seen in figure 4.5, will not be described further, because of these strong similarities.

In this paper the focus will be on the actual digital-to-analog conversion functionality,as a result of this throughout the design, ideal current and voltage sources will be used

instead of larger and more complex bias circuits.

6.0.1 General requirements

From the thesis statement the speed of the pipeline is given to 40Msample/s, whichtranslates to 25nsbetween each sample.As described in chapter 4.1.3, the circuit is going to be fully differential. The supply voltageVDD is 3V, with a common-mode voltage of 1.5V, and a voltage swing of 1.6V[4] resultingin a input range between 0.7V and 2.3V.

A summation of the general requirements can be seen in table 6.1

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CHAPTER 6. IMPLEMENTATION AND RESULTS

General requirements

Sample frequency 40Msample/sSample speed 25ns

Supply voltage 3VCommon-mode voltage 1.5V

Voltage-swing 1.6VInput range 0.7V 2.3V

Table 6.1: Summation of the general requirements

R1

in+VVin

Vref

Vout2+

out2V

Vout1

out1+V

ref+

B0

B1ENCODER

DDV

R

R

2

3

gnd

LOGIC

V 1C

2C

+ref

ref

+ref

v

+v

+v

v

ref

Figure 6.1: The final structure of the 1.5-bit subADC

6.1 1.5-bit subADC

As described in chapter 4.2.1 the design of the 1.5-bit subADC will be a fully differentialflash converter, base upon the differential pair comparator structure with some digitallogic generating the bit output, as seen in figure 6.1. To create the reference voltage forthe comparators, a string of resister will be used.

6.1.1 Differential pair comparator

Differential pair comparator, seen in figure 6.2, is implemented as presented in [4]. Theresulting transistor dimentions can be seen in table 6.2.

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Figure 6.2: Differential pair comparator

The basic principle of the type of comparator is, that from a high and a low referencevoltage, Vref+ and Vref respectively, the comparator calculates the correct reference

points. In this case theC1 comparator gets Vref+ and Vref

on the positive and negativereference input, while it is the other way around. This results in the reference pointVHand VL, as described in equations (6.2) and (6.3)

VH=Vref++ Vref+

2 +

1

4 (Vref+ Vref) (6.1)

VH=2.3 + 0.7

2 +

1

4 (2.3 0.7) = 1.9V

VL =Vref+ Vref+

2 +

1

4(Vref

Vref+) (6.2)

VL=0.7 + 2.3

2 +

1

4 (0.7 2.3) = 1.1V

From these reference voltages, the comparator sets the point where to shift the out inrelation til the two signals in the differential input.The output of the comparator is latched with the signalVlatch. This is done in order to keepthe output signals either logic high or logic low. This latch signal has to be synchronisedwith the rest of the pipeline stage, in order to have the result the correct time.

In order to verify this implementation a testbench is build. The comparator is loaded

with a 20f Fcapacitor, driven at 166.6MHzand with both reference settings.

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Transistor W[m] [Lm]M1 15 1M2 15 1M3 5.2 1M4 5.2 1M5 16 1M6 4 1M7 4 0.5M8 4 0.5M9 5 0.5

M10 8 0.5M11 8 0.5M12 5 0.5

Table 6.2: Differential pair comparator transistor dimensions

(a) Comparator C1 (b) Comparator C2

Figure 6.3: Simulation with the high and low comparator output

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6.1.2 Reference voltages

In some applications resistive loading of the power supply s not desirable then the resis-tor string can be implemented as a switch capacitor circuit [1, p. 312]. This how evermay give a less precise reference voltage, which may be a problem for the accuracy of thecomparisons. Though in most applications resistive loading of the power supply is not aproblem.This design will therefore use the resistor string to generate the reference voltage,as seen in figure 6.4.

H

L

1R

gnd

3

2

R

R

VDD

V

V

Figure 6.4: Resis-torstring

It is known from chapter 6.1.1, that the need reference volt-ages are VH = 2.3 and VL = 0.7. These are achievedthrough resistive voltage division. The input of the compara-

tors are differential inputs and therefore are connected directlyto the gate of the input transistors. Since there theoreti-cally doesnt flow any current through the gate of transistors,there is no real need for large current flow through the tran-sistor series. Though some current is need to combat the par-asitic capacitance of the transistors and of the resistors. Acurrent of 20A is chosen. The voltage prop across R1 andR3 is 0.7V, while the voltage prop across R2 is 2.3 0.7 =1.6V.

R1= R3= 0.7V

20A= 35k (6.3)

R2= 1.6V

20A= 80k (6.4)

The resistor current can easily be lowered to improve the overallpower consumption, though with the added risk lowering the accuracyof the circuit.

6.1.3 Output logicAs described in chapter 4.2.1, the main purpose of the output logic isto translate the output values of the comparators into a two bit digitalsignal. Since NAND. NOR and NOT are the most basic building blocksof digital logic, a implementation using these gates is desired. Table 6.3 shows the inputoutput relations.Since the circuit is fully differential, the first thing required is to translating the positiveand negative input values into a single logical signal. This is done by inverting the positivevalue with a NOT gate and then into a NAND gate, hereby combining the two signals. Inorder to make the LSB correct the two signals are send through a NOR gate, as seen in

figure 6.5.

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+C1 C1 +C2 C2 B1 B20 1 0 1 0 00 1 1 0 0 11 0 0 1 1 01 0 1 0 X X

Table 6.3: Fully differential subADB output logic

+V

B0

B1

in2 V

Vin1

+Vin2

in1

Figure 6.5: 1.5-bit subADC output logic

6.1.4 Final testing

Simulation with a latching frequency of 250MHz, is chosen to insure that subADC can run

fast enough, and therefore wont be the limiting factor in the overall design. The resultsof the simulation can be seen in figure 6.6.

From the simulation it can be seen that the comparator C1 switch point is offset fromthe expected 1.9V to 1.658V, the same is seen with comparator C2 which is offset from1.1V to 1.276V. This however is not a critical mismatch since the offset is not crossing thecommon mode voltage. This offset can easily be reduced, by better adjusting the designto the AMS035 technology.

6.2 2-bit subADC

As the last stage in the pipeline the 2-bit subADC has to identify the two least significantbits. This is done with the same structure as the 1.5-bit subADC, though with a additionalcomparator, reference voltage and new output logic, as shown in figure 6.7. Because of thestrong similarities with the implementation of 1.5-bit subADC, this chapter will focus onthe differences between the two implementations.

The additional comparator C2 will need the common mode voltage Vcm on both refer-ence input. By doing so the switch point om the comparator will be Vcm.A simulation ofthis can be seen in figure 6.8.

To accommodate the extra reference voltage the resistor string has to be modified, as

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Figure 6.6: 1.5-bit simulation results

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out3+

out3V

out2+V

Vout2

in+VVin

Vref

Vout1

out1+VR1

cmV LOGIC

ENCODER

B0

B1

ref+V

2b

2a

R

DDV

R

gnd

3R

V

1

2

3C

C

C

ref

ref

v

+v

ref

+v

v

+ref

v

+v

+ref

+ref

Figure 6.7: The final structure of the 2-bit subADC

Figure 6.8: Simulation with mid range comparator C3

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Resistor name value [k ]R1 35

R2a 40R2b 40R1 35

Figure 6.9: Resistor values

R

LV

R3

gnd

R1

2b

2a

R

CMV

HV

DDV

Figure 6.10: Resistorstring diagram

+C1 C1 +C2 C2 +C3 C3 B1 B00 1 0 1 0 0 0 00 1 0 1 1 0 0 10 1 1 0 1 0 1 01 0 1 0 1 0 1 1

Table 6.4: Fully differential subADB output logic

seen in figure 6.10. The new resistor values can be seen in table 6.2.To handle the additional output generated by the comparators, the output logic needs

to be changed. The requirements for the new circuit is described by the truth table intable 6.4.

When designing larger digital circuits the brute force approach is not likely to give aoptimal result. This output logic will therefore be based upon a priority encoder, [11, p.337].The resulting circuit can be seen in figure 6.11.

6.3 MDAC

As described in chapter 4.2.2, the MDAC is the combination of the S/H circuit, subtrac-tor, multiplier and DAC. This mean that the MDAC has adopted all of the demands forfunctionality.The DAC functionality is implemented as shown in figure 4.7, by five switches. These willoffset the voltage in the amplification phase of the MDAC circuit with etherVref, 0 and+Vref. Since the system is fully differential the offset values ofV in be the opposite ofthe V in+, so that the offset will change the voltage ration between the two input signalswith the correct subtraction.The capacitors in this circuit must be small because of the high speeds need. The capaci-

tors are therefore chosen to be 20f F each.

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in3 V

B1

B0+Vin3

+Vin2

in2 V

Vin1

in1+V

Figure 6.11: 1.5-bit subADC output logic

In odder to implement the MDAC the following components needs to be constructed.

Switches.

Transconductance Operational amplifier (OTP).

Common-Mode FeadBack circuit (CMFB).

Bit logic.

6.3.1 Switches

Most switches can be implemented by a minimum size transistor, either a NMOS for sig-nals that must be able to go all the way down to gnd, or a PMOS for a switch that needsto be able to all the way up to VDD.In some applications that are very sensitive to charge injection and clock feedthrough, theuse of single transistor switches can be problematic. Also switches that drive output canneed a wider signal swing.To solve the problem with charge injection and clock feedthrough, the switch can be im-

plemented with dummy switches [1, p. 832], where two short circuited half size transistorsare placed on each side of the ordinary switch transistor[7], as seen in figure 6.12(a). Bydoing so the parasitic charge from the transistor will injected into the dummy switches,which is the reason for the half dimension of the shorted transistors. An other optionis the transmission gate, seen in figure 6.12(b), where a NMOS and PMOS are parallelcoupled. The PMOS is usually twice the size of the NMOS in order to match the currentflow. The switches in the overall design of the MDAC will be transmission gates i order toaccommodate the large signal swing.

6.3.2 Folded-Cascode Opamp

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(a) Dummy switch circuit (b) Transmission gate

switch

Figure 6.12: Implementation of switches

This chapter deals with implementation of the OTA circuit.The actual implementation is based upon[8, p. 883] and [3, p. 266].

Dimensions of OTA

The fully differential folded opamp is constructed as shown in figure .

As a general design choice the length of the transistors are set to L = 2m and theminimum overdrive voltage is set toVov = 0.1V. Since speed is one of the main objectivesof this design, the slew rate is therefore set to S R= 600106 V

s, since the full voltage range

is 3v and a speed of 200M hzover 3 volts is desirable.The opamp will be designed to drive a load ofCL= 50f F.The output current is then Io =S R CL = 30A. which mean that the maximal currentrunning through the input transistorsQ1 and Q2.The width of the transistors can be calculated from equation (3.3).

iD =1

2 CoxW

L

Vov2

(6.5)

W = 2 iD LnCox V2ov

(6.6)

Transistors widths for :Q1,Q2,Q12 and Q13

W1,2,12,13= 2 Io LnCox V2ov

= 133m (6.7)

Transistors widths for :Q3,Q4 and Q11

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W3,4,11= 2 Io LnCox V2ov

= 385m (6.8)

The minimum output voltage need to keep the transistors Q7, Q8, Q9 and Q10 insaturation is Vtn+ 2 Vov = 0.8. This voltage drop is across two transistor, which gives aoverdrive voltage of 0.4 v each.

W7,8,9,10= 2 Io LnCox

0.42

= 9m (6.9)

Vbias1 is found

Vgs6= Vov+ Vtp = .65 (6.10)Vs6= V DD V ov= 2.9 (6.11)

Vbias1=Vgs6+ Vs6= 2.25V (6.12)

Vbias2 is found

Vs7=Vov7+ Vov9= 0.8 (6.13)Vgs7=V ov+ Vtn = 0.7 (6.14)

Vbias2=V gs7 + Vs7= 1.50 (6.15)

There are several way to improve on the this implementation. But it will work for basictesting of the rest of the circuity.

Testing

The circuit is change from the differential configuration into a ordinary folded cascode.

This is done in order to test the opamp without the interference of the CMFB circuit. Thegoal of the test is to find the unity gain frequency ft [3, eq. 6.37].First the offset voltage is found by sweeping the input of the opamp, then find the pointwhere output voltage is equal the common-mode voltage. The offset voltage for this circuitis 20.405V. With the offset voltage know, it can be compensated for by adding a offsetvoltage source on one amplifier input.The frequency analysis is by adding a sinus signal to the input of the opamp. In orderfind the unity gain frequency the sinus is the swept between 10Hz and 100MHz. It can beseen from figure 6.14, that ft = 37.21MHzand a DC open loop amplification at 62.89db.The unity gain frequency is far below the required. This leaves room for improvement, see

chapter 7.

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Figure 6.13: Implementation of a fully differential opamp

Figure 6.14: Magnitude and phase of the OTA with 50f F load

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Figure 6.15: Switch cap. implementation of the CMFB circuit

6.3.3 Common-Mode FeedBackA common-mode feedback circuit is necessary in odder to control the common-mode voltageVcm, to keep the differential output of the OTA from drifting.There are several implementation possibilities, but since the pipeline circuit generally is ofswitch capacitor implementation, the input signal will therefore be discreet. The CMFBwill therefore also be switch capacitor implemented [3, p. 287][1], as seen in figure 6.15.

The basic idea behind this circuit, is that the capacitors Cc keeps the average of theoutput voltage, and sends this back to the OTA. The Cc voltage is determined by the Cswhich is switch between the Cc and the bias voltage. The bias current is matched to thebias current running in the OTA.

The sample capacitorsCs are set to 10f F, while the differencing and averaging capacitorsCcare set to 50f F, so that the change in the Vcntrlwont change too much each clock cycle.All switches are implemented by NMOS dummy switches, except with the output switches.These need to have the full voltage rage and must therefore be transmission gates.The bias circuit transistor is matched to the folded cascode transistors Q7 and Q9.

6.3.4 Bit-logic

A essential part of the DAC functionality of the MDAC is, to convert the digital outputof the subADC back into a analog signal again. To do this the 1.5-bit, digital signal has

to be converted into a three control signals D0,D1 and D2, which will control some ofthe switches in the overall MDAC design. I other words, the bit signal must be one-hotencoded into a three bit signal.The bit-logic is implemented by modifying a simple 2-4 bit MUX [11]. The result can beseen in figure 6.16. 6.16

6.3.5 Final testing

Beside the components described in this chapter, a clock control circuit needs to be designedand implemented in order to test the circuitry. This will be further addressed in chapter

7.

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D2

D1

D0

B1

B0

Figure 6.16: The MDAC bit-logic

6.4 Delay

Q

Q

D

Figure 6.17: A D-type Flip-Flop

The delay components function, as described in chapter 4.3, is tostore the digital signals from the different stages, and then de-liver them to the digital error correction when the input signal haspassed through all the stages. Since area consumption is a fac-tor, the implementation of actual memory is not an option. Thiswould also consume to much power. A more simple solution is alarge register array. This can be implemented with different com-ponents, but the most strait forward is to use D-type flip-flops(DFF).

The D flip-flop, seen in figure 6.17, is a clocked circuit that samplesa digital input signal on, typically, a raising edge on the clock. When adigital data signal has been sampled it gets put out on the output andheld there till the next raising edge. Most DFFs have a normal outputand a inverted output. In this application the inverted output will not be use. Since this isa digital circuit, there will be a technology optimised version in the CAD tool. This only

leave the actual implementation, which can be seen in figure 6.18.

6.5 Digital error correction

A

C C in

1bit

Full

Adder

S

B

out

Figure 6.19: AFull Adder

The main purpose of the digital error correction, as describedin chapter 4.4, to increase the accuracy of the each subADC. Itis done by sacrificing 0.5 bit as a buffer margin between logical1 and 0. This is implemented as a string of one bit fulladders.

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S 2

DFF DFF

DFFDFF DFFDFF

DFF DFFDFF DFF DFF DFF

DFFDFF DFFDFF DFF DFFDFF DFF

DFF DFFDFF DFF DFFDFF DFFDFF DFF DFF

DFF DFFDFF DFF DFFDFF DFFDFF DFF DFFDFF DFF

DFF DFFDFF DFF DFFDFF DFFDFF DFF DFFDFF DFF DFF DFF

DFF DFFDFF DFF DFFDFF DFFDFF DFF DFFDFF DFF DFFDFF DFFDFF

CLK

B0 B1 B0 B1 B0 B1 B0 B1 B0 B1 B0 B1 B0 B1 B0 B1 B0 B1

S 1 S 2bitS 8S 7S 6S 5S 4S 3

Figure 6.18: DFF implementation of the delay component

A full adder, seen in figure 6.19 has three inputs and two output.Two of the input A and B is the ordinary input, while Cin is the carryin. The outputCout is the carry out and Sis the ordinary output. It ispossible With this adder structure, to build a infinite bit size adder, byplacing single bit adders in a side by side. This is the basic principlebehind the structure of the digital error correction. The full adder ispart of the technology specific libraries in the CAD tool.The two bits from the last stage will not be passed trough the digital error correction. Theerror correction will therefore be comprised by 8 full adders, as shown in figure 6.20.

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S 5

Adder

Full Full

Adder Adder

Full Full

Adder Adder

Full Full

Adder

Full

Adder

LSB

B9 B8 B7 B6 B5 B4 B3 B2

B1 B1 B0B1 B0B1 B0B1 B0B1 B0B1 B0B1 B0B1 B0

S 1 S 2 S 3 S 4 S 6 S 8 S 2bit

B1 B0

Adder

Full

MSB

S 7

Figure 6.20: Full adder implementation of the error correction algorithm

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Chapter 7

Further work

Things to include in the next iteration of this pipeline project.

Final simulation of the design

The implementation of the fully simulateable pipelined ADC, designed in chapter 4, stillneeds some work. It is necessary to design and implement a clock and control signalgenerator, in order to get the developed design to work. The absence of this componenthas shown, to be a notable limiting factor on further analysis of the MDAC component,with its switch capacitor implementation, and indecently of the entire pipelined structure.

Optimization of subADC

Further analysis and simulation of the subADC circuit. In order to reduce offset error,which should easily done, by better adjusting the design to the AMS035 technology.

General

Increasing the unity gain frequency and amplification of the OTA, by improving theimplementation.

Further development of the initial design. Further simulation of the general structure, with respects to removal of offset errors

and other noise sources.

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CHAPTER 7. FURTHER WORK

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Chapter 8

Conclusion

The purpose of this project was to design a 10-bit pipelined ADC, capable of running 40Msample/s. This has in part been achieved, though some additional work need beforebeing fully functional.The pipelined ADC design was achieved by initially analysing the different options regard-ing the overall structure. The 1.5-bit stage resolution is chosen in order to accommodatethe speed requirements. The final overall structure is with 8 1.5-bit stages and one 2-bitstage, so that digital error correction can be applied. Further analysis of the structure ofthe stage structure concluded that an redesign of the traditional structure into a subAD-C/MDAC structure would be advantages. Generally the design is fully differential in order

to compensate for offset errors and other limitations.An analysis for the AMS035 technology, made the implementation and simulation of theessential design components possible.Since the pipelined structure leads the signals through the different stages discreet, thegeneral implementation of the circuits is chosen to be of switch capacitor type. The sub-ADC is implemented with fast differential pair comparators. The MDAC is implementedwith a fully differential folded cascode OTA. Though the essential components are imple-mented, the design need some more work, in order to fully simulate the entire pipelinedADC circuit. It is therefore not possible to finally verify the sampling speed of the design.

Jonas Benjamin Borch, s052435

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CHAPTER 8. CONCLUSION

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[9] Ching-Cheng Tien sung Hsien Lu, Chun-Kuei Chiu. A 10 bit 40-ms/s pipelined

analog-to-digital converter for ieee 802.11a wlan systems. Department of ElectricalEngineering, Chung-Hua University, No. 707, Sec.2, WuFu Rd., Hsinchu, Taiwan300.

[10] Ching-Cheng Tien and Tzu-Yen Hsu. A 10 bit 40-ms/s pipelined analog-to-digitalconverter for wlan systems. Chung Hua Journal of Science and Engineering,, 5:6370,2007.

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