Brief History

Brief History

• Early ‘80s, US Dept. of Defense project– VHSIC Hardware Description Language

• VHSIC = Very High Speed Integrated Circuit

– For documentation & specification of ASICs

• 1987, IEEE standard adopted• 1992, standard updated• ‘90s to date, highly popular in industry

– Main HDL competitor: Verilog, “simpler to learn”

– Commonly taught in CEng programs

Uses Evolved

• Documentation & specification

• Circuit simulation

• Circuit synthesis

Why a “language”?

• VHDL largely overlooked while schematic capture reigned

• Moore’s Law put schematic capture out of business

• Text-based modeling attractive → suitable input for CAD tools– Modeling, simulation, synthesis

Is it “like C”?

• Yes– There are statements, block structure, variables,

constants, operators, even “;”

• No– SW programmers follow sequential “Von Neumann”

computation model; but…

– HDL statements translate into logic gates, not instructions

– HW is always there, always “on”, operating concurrently → surprises SW people (example later)

Three ways to describe circuit

1. Structural– Instantiate specific library components and “wire”

them together

2. Dataflow (RTL)– Instantiate register components from library– Code combo logic with high-level operations; let

VHDL compiler synthesize logic gates

3. Behavioural– Code algorithm steps; let VHDL compiler infer

components, datapath, and controller

Basic Ingredients

• Structure– Entity/architecture

• Behaviour– Process– Timing

• Data– Signal– Variable– Logic values

Basic Logic Gatelibrary ieee;use ieee.std_logic_1164.all;

entity AND_ent isport( x: in std_logic;

y: in std_logic;F: out std_logic

);end AND_ent;

architecture behav2 of AND_ent isbegin F <= x and y;end behav2;

architecture behav1 of AND_ent isbegin process(x, y) begin -- compare to truth table if ((x='1') and (y='1')) then

F <= '1';else F <= '0';end if;

end process;end behav1;

What did we observe?

Fxy

Operation defined on std_logic

Signal assignment (a “wire”)

Comment

Library: Abstract Data Types

IEEE std_logic_1164 valuesU UninitializedX Unknown0 Zero1 OneZ High Impedance (tristate not driving output)W Weak UnknownL Weak Zero (low)H Weak One (high)- Don’t Care Why all these??

Entity/Architecture Pair

• Entity → circuit’s external interface– Ports function parameters– Strongly typed: std_logic– Mode: in, out, inout (tristate), buffer (“out”

that’s readable inside architecture)

• Architecture → internal implementation– Multiple implementations allowed

• Code block: thing begin…end thing ;

Process

• Wrapper for “sequential” statements– ( sensitivity list )

• Tells simulator to re-simulate the process when any member of list changes value

– Sequential-type statements can only appear inside a process:

<= If-Then-Elsif-Else Case-When

– Concurrent-type statements can appear anywhere

• Processes together become concurrent blocks of logic

Result of Description

• Like OO class definition, entity has to be instantiated in another architecture– One behaviour chosen upon instantiation– Libraries full of entity definitions

• If simulation is goal:– Both behaviours are identical

• If synthesis is goal (actual AND gate):– Should anticipate what circuit compiler will create– Different from SW where normally trust compiler

Combinational Logic DesignComponent Library “work”entity OR_GATE isport( X: in std_logic;

Y: in std_logic;F2: out std_logic

);end OR_GATE;

entity AND_GATE isport( A: in std_logic;

B: in std_logic;F1: out std_logic

);end AND_GATE;

use work.all;

entity comb_ckt isport( input1: in std_logic;

input2: in std_logic;input3: in std_logic;output: out std_logic

);end comb_ckt;

architecture follows →

outputinput2input3

input1

Combo Logic

architecture struct of comb_ckt is

component AND_GATE isport( A: in std_logic;

B: in std_logic; F1: out std_logic ); end component;

component OR_GATE isport( X: in std_logic;

Y: in std_logic; F2: out std_logic ); end component;

signal wire: std_logic; -- signal just like wire

begin

-- use sign "=>" to clarify the pin mapping

Gate1: AND_GATE port map (A=>input1, B=>input2, F1=>wire);

Gate2: OR_GATE port map (X=>wire, Y=>input3, F2=>output);

end struct;

F1A

B

X

Y

F2

wireinput2

input3

input1

output

Label for statement

Example of Programmer’s “Surprise”entity … port( a, b, c: in bit; X, Y: out bit );

…

signal s: bit:=‘0’;

Y <= s and a;

X <= a or c;

s <= b or c;

• What does Y output for (1,0,1) input?– As (bad) software, clearly 0

– As hardware, describes logic circuit structure• “b or c” isn’t “done after” Y<= assignment

• result → 1

a

b

X

Yc

s

Sequential Design

entity seq_design isport( a: in std_logic;

clock: in std_logic;reset: in std_logic;x: out std_logic

);end seq_design;

architecture FSM of seq_design is -- define the states of FSM model

type state_type is (S0, S1, S2, S3); signal next_state, current_state:

state_type;

begin -- concurrent process #1: -- advance state on clock going high state_reg: process(clock, reset) begin

if (reset='1') then current_state <= S0;

elsif (clock'event and clock='1') then current_state <= next_state;end if;

end process;more →Enumerated

data typeBecomes

state register

reseta

clock

xstate_r

eg

comb_logic

Sequential Design-- concurrent process #2: -- compute output and next statecomb_logic: process(current_state, a) begin

-- use case statement to show the -- state transition

case current_state is when S0 =>

x <= '0';if a='0' then next_state <= S0;elsif a ='1' then next_state <= S1;end if;

when S1 => x <= '0'; … when S2 => x <= '0'; … when S3 => x <= '1'; … when others =>

x <= '0';next_state <=

S0;end case;

end process;end FSM;

reseta

clock

xstate_r

eg

comb_logic

Many More Features

• Logic vectors & arraystype mem is array(0 to 127) of std_logic_vector(15 downto 0);

– Define registers, buses, memories

• Variables c := a xor b;

– Temporary value, not intended to generate hardware

• Timing statements wait for 10 ns;

– Used for simulation

– “Test bench” code connected to system-under-test can check if timing constraints met/violated

Still More Features• Libraries library ieee;

– Default library = “work”– Built-in packages in “std”

• Package use ieee.std_logic_1164.all;

– Binds constants, types, operations into set of “abstract data types”

• Configurationfor Gate1: AND_ent use entity work.AND_Ent(behav2);

– Selects alternative architectures when instantiating entity

• Generic like C++ template parameterization

VHDL• An acronym for Very high speed integrated circuit

Hardware Description Language

• VHDL enables hardware modelling from the gate to system level

• Allows various design methodologies• Provides technology independence• VHDL has been standardised:

– VHDL 87– VHDL 93

System Design; definition and use of its parts

• A system communicates via an interface• Interface is “entity” in VHDL• Cannot have any VHDL system without an entity• Example:

entity my_entity is

………………..

end entity my_entity;

Architecture

• The body of the system accomplishes some tasks on the data

• eg data transformation• In VHDL the body is called “architecture”• Example:

architecture my_architecture of my_entity is ………………. begin ……………… end architecture my_architecture ;

Types of Architecture

• Behavioural (Functional)– The system in terms of its functionality – It does not contain any information about the internal

system structure– It describes the expected behaviour: What a system will

do– Response of outputs to inputs– No clue as to HOW but describes WHAT a system has

to do

Types of Architecture

• Structural– HOW a system is composed– what components should be used– describes internal structure of system– how they should be connected– akin to a textual version of a schematic diagram

A behavioural architecture

if CLK'event and CLK='1' then

--CLK rising edge

DOUT <= DIN;DIN DOUT

CLK

D Flip Flop

A structural architecture

A Full Adder:

SUM<=A xor B xor C;

CARRY<= A and B or ((A or B) and C);

FullAdder

CARRY

SUM

A

B

C

A Structural Architecture

• --generate construct

• gen: for i in 0 to n-1 generate

• --component instantiation

• ins: full_adder port map (a(i), b(i), carry(i), sum(i), carry(i+1));

• end generate;

One Entity - Many Architectures

• More than one way to create a design

• Similarly, more than one architecture for a single entity (cf. More than one schematic to fulfil same specification)

• Same interface

• BUT only one entity for any architecture

Package

• External source of description

• Allow you to define items outside of VHDL standards

• Must be declared in advance using “library” and “use” keywords, usually before entity

Few Packages

• Standard (defined by the std library)• Std_logic_Textio (defined by the IEEE library)• Std_logic_1164 (defined by the IEEE library)• Plus vendor-specific

Communications• Signals: inside device or between devices• Single or multiple wire - (bus) or (vector)• Example

– bit for single signals– bit_vector for multiple signals– in both cases, each signal line can be either ‘1’ or ‘0’

• For bit_vector the width of the vector must be specified using two key words: downto and to

• Order important for vector– bit_vector(7 downto 0) ascending order of bits– bit_vector (0 to 7) descending order of bits

external signals • External signals connect the system to the outside:

they form the system’s interface• Each external signal is specified as port inside its

entity• Each external needs a unique name, a type and a

direction:– input - in– output - out– bi-directional - inout

Port Syntax

• port_name: port_direction port_type ;– example: port( result: inout bit_vector (0 to 7) );

• Multiple signals of different type separated by semicolons

• Same type separated by commas• optional initial value, preceded by :=

Example: entity ROM_MEMORY is

port ( A_ROM : in bit_vector (3 downto 0);

CS_ROM : in bit;

D_ROM : out bit_vector (7 downto 0) );

end entity ROM_MEMORY;

Example

Internal signals

• Internal signals declared inside an architecture

• The keyword signal is required to declare an internal signal

• Internal signals do not require a direction

• It is possible to specify an initial value for an internal signal

Generics• Method of providing constant values for different

parameters.• Must be in entity, before ports• Need the keyword ‘generic’, name, type, value,

optional commentexample generic (BusWidth : integer := 2; MaxDelay : time := 100 ns ) ;• Can be used anywhere a constant is needed

Generics• Can be used anywhere a constant is needed

• Parameters are typically specified by generics:– The size of some objects such as arrays or

buses– Timing parameters – Useful in structural and behavioral models

Standard Data Types• Enumeration types ( Boolean, bit, character)

• Integer type

• Real type

• Physical type (time)

• Standard array types ( string, bit_vector)

Enumeration types• Bit

– 0,1– not same as Boolean in VHDL

• Boolean – true, false

• Character– all characters in ISO 8859-1 (West European)

• eg ‘0’, ‘1’, ‘X’

Integer and real types• Integer

– implementation dependent– must include -2147483647 to +2147483647

• Real– implementation dependent– must include -1.0E308 to +1.0E308

Physical Types

• They specify the object values and the units they are expressed in.

• VHDL defines only one: time

• Note primary and secondary units

Predefined arrays• Arrays are collections of elements of the same

type• The number of elements is specified by a range• Predefined VHDL arrays are:

– bit_vector (first element is 0)

– and string (first element is 1)

– single element in single quotes ‘’, multiple element double quotes ””

– one-dimensional

User-defined Types• Use the keywords type or subtype• Example:

– type short is range -128 to 127;

– subtype natural is integer range 0 to 147483647;

( subtype of the integer type)

– type FSMstates is ( idle, decode, execute );

( a user defined enumerated type)

– type TYPE_NAME is array (0 to 31) of BIT;

( user defined array of element of type bit)

Signal Assignment

Uses <=Target on left

eg a <= b or carrow denotes flow of information

not, and , or, nand, nor, xor, xnornot has highest precedenceall others equal and are evaluated left to right

Example 2-Input ANDEntity And2 is

port (x,y : in bit; z : out bit);

end entity And2;

Architecture ex1 of And2 is

begin

z <= x and y;

end architecture ex1;

Logical operators• not, and , or, nand, nor, xor, xnor• They accept operands of type BIT, Boolean and bit_vector.• If the operands are of type bit_vector, they must be of the

same size • a sequence of logical operators requires parentheses.• Example:

– a and b or c and d; -- wrong

– (a and b) or (c and d); --correct

Arithmetic Operators• Addition ‘+’, subtraction ’-’,multiplication ‘*’,

division ‘/ ‘, modulus ‘mod’, remainder ‘rem’, exponentiation ‘**’ and absolute value ‘abs’

• Predefined for – integer– real ( except ‘mod’ and ‘rem’)– time

Not defined for bit_vector‘+’ and ‘- ‘ can also be used as unary operators ( sign operators)

Arithmetic Operators• Operands of same type (except exponentiation :

exponent always integer) • an operand of type time can be multiplied or divided

by an integer (result of type time)• order of precedence:

– exponentiation ‘**’– multiplication ‘*’, division ‘/’– unary sign operators ‘+’ and ‘-’– addition ‘+’ and subtraction ‘-’

• Example: 3+4*5=23, (3+4)*5=35

Relational operators

• The operators equal ‘=‘, not equal ‘/=‘, less than ‘<‘, greater than ‘>’, less than or equal ‘<=‘, greater than or equal ‘=>’, compare objects of the same type

• Result always BOOLEAN (true or false)

• Bit_vectors operands do not need to be of the same length: both operands are left justified

Shift Operators• Applied only on the one-dimensional array• with the elements of the type BIT or BOOLEAN

• srl, sll, ror, rol, sla, sra

• ‘0’ shifted in for type bit, false for type Boolean• Example: z_bus <=a_bus sll 2;

SRL

SRA

ROR

SLL

SLA

ROL

Concatenation• Allows creation of a new array from several

others• ‘&’ is the concatenation operator• Length of new array is sum of length of both

operands• Example: signal a, b: bit_vector (3 downto 0); signal z: bit_vector (7 downto 0); z <= a & b;

a(3) a(2) a(0)a(1) b(3) b(2) b(0)b(1)Z

Operators priority1. miscellaneous operators **, abs,not

2. multiplying operators *, /, mod, rem

3. sign operators +, -

4. adding operators +, -, &

5. shift operators sll, srl, sla, sra, rol, ror

6. relational operators =, \=, <, <=, >, >=

7. logical operators and, or, nand, nor, xor, xnor

• The expressions are evaluated form left to right

• operations with higher precedence are evaluated first

• If the order should be different from the one resulting from this rule, parentheses can be used

Assignment Delay• An assignment may be delayed - eg for simulation

purposes• The “ after” clause is used

– example: a<=b after 5 ns; --the assignment is delayed by 5 ns

• Inertial delay is default in VHDL - two subsequent changes ignored if time between them is less than delay - system cannot respond fast enough

Transport Delay

• Signals transported without changes

• Always propagates switch action to output

• Use “transport” keyword

• Typical of transmission lines

• Apply to signals of any type– example a<= transport b after 3 ns;

Process

• List of sequential operations

• A process is sensitive to a list of signals

• Any event on any of these signals causes the process to be executed once

• A process is an infinite loop

Process Syntax

name: process (sensitivity list)

declarations part

begin

sequential statements

……………………….

end process name;

Wait

• Process execution can be suspended by the statement “ wait ”

• Resuming the process depends on meting the condition(s) specified in the wait statement

• The wait statement can be located anywhere between begin and end process

• A process with a sensitivity list may not contain any wait statements

Syntax

• wait;

• wait on signal_list;

• wait until condition;

• wait for time;

Example 1 signal S1, S2 : Std_Logic;

. . .

process

begin

. . .

wait on S1, S2;

end process; • After executing all statements, the process will be

suspended on the wait statement and will be resumed when one of the S1 or S2 signals changes its value.

Example 2

• wait until Enable = '1';

In this example, the wait statement will resume the process when the Enable signal changes its value to '1'

• wait for 50 ns;

A process containing this statement will be suspended for 50 ns.

• wait;

the process is suspended forever

Example 3process

begin

wait on A, B until CLK = '1';

. . .

end process;

• The process is resumed after a change on either A or B signal, but only when the value of the signal CLK is equal to '1'.

Signals in Processes

• Signals cannot be declared in processes

• Assignments only occur when process suspended

• Multiple assignments meaningless

signal A, B, C, X, Y, Z : integer;

process (A, B, C)

begin

X <= A + 1;

Y <= A * B;

Z <= C – X;

B <= Z * C;

end process; • When the process is activated by an event on the signal C

this will cause change on the signal B inside the process, which will in turn reactivate the process because B is in its sensitivity list.

Example

signal A, B, C, X, Y, Z : integer;

process (A, B, C)

begin

X <= A + 1;

Y <= A * B;

Z <= Y – X;

Y <= B;

end process; • The second assignment (Y <= A * B) will never be executed

because only the last assignment to Y will be activated

• Only the previous value of X will be used as the A + 1 assignment will take place when the process suspends.

Example

Variables

• Similar to signals, but more flexible

• Provide instant storage of temporary data in a variable

• Must be declared in processes

• Use keyword “variable”

• Assignment via :=

• If same type, can assign variables to signals

Constants

similar to generics, but generics are parameters that can be used dynamicallyConstants cannot be changed without altering the codeHave to be declared before useSyntax

constant keyword, constant name, colon, type, :=, value, ; example: constant Loops : integer := 10;

Process flow

– if ---then– if ---then --- else– if ---then ---elseif– case statement– while ---do– for---do– loop

if---then

if condition then

sequential_statements

end if; • if rising-edge (CLK)

then Q<= D;

end if;

If ..then..else, if..then..elsifif condition then if condition then

sequential_statements sequential_statements

else elsif condition then

sequential_statements sequential_statements

end if; else

sequential_statements

end if;

Example

if reset = ‘1’

then

Q<= ‘0’;

elsif rising_edge (CLK)

then Q <= D;

end if;

CASE statementSyntax:

case expression iswhen choice => sequential statementswhen choice => sequential statements………………….. when others => sequential statementsend case;

• The case statement contains a list of alternatives starting with the when key word

• When key word is followed by one or more choices and a sequence of statements

• if all explicitly listed choices do not cover all the alternatives when others key word must be used

• The when others clause may appear only once and only as the very last choice

CASE statement

ExamplePort ( A, B, C, X : in integer range 0 to 15 Z : out integer range 0 to 15);…………...Process ( A, B, C, X)begincase X is when 0 => Z <= A ;when 7 | 9 => Z <= B;when 1 to 5 => Z <= C;when others => Z <= 0;end case;end process;

While Loop

• While loop– condition checked– statements executed if true– skipped if false– loop completed if false, control to next

statement after end of loop

Syntax

loop_label: while condition loop

sequence_of_statements

end loop loop_label;

loop_label: for loop_parameter in range loop

sequence_of_statements

end loop loop_label;

• The loop statement contains a sequence of statements, which are supposed to be repeated many times

• The statement also lists the conditions for repeating the sequence or

specifies the number of iterations.

Loopsignal Clock : BIT := '0';

...

Clk_1: process (Clock)

begin

L1: loop Clock <= not Clock after 5 ns;

end loop L1;

end process Clk_1;

• The process (which is a clocking signal generator) contains a loop without an iteration scheme, which will iterate indefinitely

For Loop

• Construct is “for count in range loop” and “ end loop;”

• Substitute range for width of loop

• Repeats a fixed number of times - range (as opposed to while loop)

• Loop executed as long as counter in range

• No need to declare count

Example

Signal a,b, c: std_logic_vector 9 7 downto 0);

process( a, b)

begin

for i in 7 downto 0 loop

c(i) <= a(i) and b(i);

end loop;

end process;

Next and Exit• Use “next” to jump to next iteration• Use “exit” to escape loop earlyExampleport (databus : in std_logic_vector( 3 downo 0);…………………………….for counter in 3 downto 0 loop statement 1; next when databus(counter) = ‘0’; statement 2;end loop;ExampleL2: loop A:= A+1;

exit L2 when A > 10;

end loop L2;

• The infinite loop becomes in practice a finite, as the iterations will terminate as soon as A becomes greater than 10.

Standard_logic

• Defined by IEEE 1164• Sub-type of standard_ulogic• Allows multiple drivers of a signal -

resolved• Enumerated type, Nine values • Prefix each entity declaration by

library ieee;use ieee.std_logic.1164.all;

Std_logic• U un-initialised• X unknown strong• 0 forcing 0• 1 forcing 1• Z high impedance• W weak unknown• L weak 0• H weak 1• - don’t care

Truth Table

A1 A0 Z3 Z2 Z1 Z0

0 0 0 0 0 1

0 1 0 0 1 0

1 0 0 1 0 0

1 1 1 0 0 0

• Example 3.2: a 2-4 decoder

library IEEE;use IEEE.std_logic_1164.all;

entity decoder2to4 isport (

output: out STD_LOGIC_VECTOR (3 downto 0);input: in STD_LOGIC_VECTOR (1 downto 0) );

end decoder2to4;architecture decoder2to4 of decoder2to4 isbegin

process ( input )

begin

case input is

when "00" => output <= "0001" ;

when "01" => output <= "0010" ;

when "10" => output <= "0100" ;

when "11" => output <= "1000" ;

when others => output <= "ZZZZ" ;

end case;

end process;

end decoder2to4;

Truth Table

A1 A0 Z3 Z2 Z1 Z0

0 0 0 0 0 1

0 1 0 0 1 0

1 0 0 1 0 0

1 1 1 0 0 0

• Example 3.2: a 2-4 decoder

library IEEE;use IEEE.std_logic_1164.all;

entity decoder2to4 isport (

output: out STD_LOGIC_VECTOR (3 downto 0);input: in STD_LOGIC_VECTOR (1 downto 0) );

end decoder2to4;architecture decoder2to4 of decoder2to4 isbegin

process ( input )

begin

case input is

when "00" => output <= "0001" ;

when "01" => output <= "0010" ;

when "10" => output <= "0100" ;

when "11" => output <= "1000" ;

when others => output <= "ZZZZ" ;

end case;

end process;

end decoder2to4;

Concurrent VHDL

• The world is not sequential• In VHDL all statements within architectures are

executed concurrently• Specify systems as “set of concurrently working

sub-systems” Use set of processes• concurrent statement or processes are executed at

same time• Independent of the order in which they appear

Model Styles

Three typesbehaviouralstructuraldataflow

Models written with concurrent signal assignments are called “dataflow” models

Behavioural VHDL - only used in processes or subprograms (procedures and functions)

Structural VHDL consist of component instantiations

Behavioural VHDL: Concurrent Processes

• All processes in an architecture execute concurrently with each other

• Statements in a process execute sequentially

• Remember assignments to signals occur only at suspension of a process

Suspension and Activation• A process executes when a signal changes state.• This rule applies to all processes• If as a result of a process suspending a signal is

changed, this may cause another process to re-start • Statements within re-started process executed

sequentially, independent of other processes

Transferring Information between Processes

• Only signals can be used to transfer information between processes

• Variables are local to a specific process - cannot be used for information transfer between processes

ExampleA multiplexer:entity multiplexer is Port ( in0,in1 ,sel : in bit; output : out bit);end entity multiplexer;architecture behavioural of multiplexer is begin process ( in0, in1, sel)begin if sel = '0' then output <= in0;else output <= in1;end if;end process;end architecture behavioural;

in0

in1

output

sel

If a process is used to model the behaviour of a 2 to 1 mux, then 3 processes are required for a 4 to 1 mux

in2

in3output1

sel0

in0

in1

output0

sel0

sel1

output

entity multiplexer is

Port ( in0,in1, in2, in3, sel0, sel1 : in bit; output : out bit);

end entity multiplexer;

architecture behavioural of multiplexer is

signal output0, output1 : bit;

begin

process ( in0, in1, sel0)

begin

if sel0 = '0' then output0 <= in0;

else output0 <= in1;

end if;end process;

process ( in2, in3, sel0)begin if sel0 = '0' then output1 <= in2;else output1 <= in3;end if;end process;

process ( output0, output1, sel1)begin if sel1 = '0' then output <= output0;else output <= output1;end if;end process;

end architecture behavioural;

Simple Processes • Sometimes process construct too complex

eg single basic gate• Overhead of three extra statements ie

process, begin and end• Use a “concurrent signal assignment “

instead• Special construct; executes in parallel with

other processes, but simpler

Concurrent Signal Assignments

• Simple signal assignmentInt1<= A or C;

• Activated when any signal on right changes ie A or C in this case

• you have actually seen this before eg 2-4 decoder, last lecture.

Selected Signal Assignment

• CASE statement cannot be used outside processes

• For multiple concurrent signal assignment use “selected signal assignment construct”

• Restricted to signal assignments only

• Cannot be used inside processes

Selected signal assignment: syntax

with expression select target <= value_1 when choice_1,value_2 when choice_2 | choice_3,value_3 when choice_4 to choice_5,…….value_n when others; • | means or • when others covers all remaining choices• Note commas between lines, colon at end.

Example of Selected Signal AssignmentPort ( a, b, c, ,x : in integer range 0 to 15;

z: out integer range 0 to 15);

……….. ………….

with x select process (a,b,c,x)

z <= a when 0, begin

b when 7 | 9, case x is

c when 1 to 5, when 0 => z <= a;

0 when others; when 7 | 9 => z <= b;

when 1 to 15 => z <= c;

when others => z<= 0;

end case;

end process;

Example of Selected Signal Assignment

entity multiplexer4_1 is Port ( in_d: in bit_vector ( 3 downto 0); control: in bit_vector ( 1 downto 0); output: out bit);end entity multiplexer;

architecture selected_assignment of multiplexer4_1 is beginwith control select

output<= in_d(0) when "00", in_d(1) when "01", in_d(2) when "10", in_d(3) when others;

end architecture selected_assignment;

Conditional signal assignment

• The signal assignment can be extended by the specification of condition

• condition is a boolean expression• the condition is introduced by the key word

“when”• The key word “else” is necessary after each

condition• The conditional assignment is equivalent to the

if..,elsif,…else.construct used within processes

Conditional Concurrent Signal Assignment

Conditional statement construct if ----else can only be used in a processUse conditional signal assignment statement insteadRestricted to signal assignments onlyRem: conditional statement ( as opposed to conditional signal assignments) can be used for any kind of sequential statement

Conditional signal assignment: syntax

Target <= value_1 when condition_1 else

value_2 when condition_2 else

……..

zalue_n-1 when condition_n-1 else

value_n ;

Exampleentity MUX isport ( in0, in1, sel : in bit; output : out bit);end entity;

architecture behavioural of MUX is architecture dataflow of MUX isbegin begin process ( in0, in1, sel) output <= in0 when sel = ‘0’ else begin in1;if sel = '0' then output <= in0; end architecture dataflow;else output <= in1;end if;end process;


Synchronous Sequential Systems

• All large digital systems have a concept of “state”

• “state” depends on present and past input values

• Thus “sequential” as opposed to “combinational”

A General model

Combinational Logic

Registers

Inputs Outputs

Next StatePresent State

Stores present state

Synchronous and Asychronous

• Present state held in registers => storage

• Present state updates as soon as next state change => asynchronous

• Present state updated on clock edge => synchronous

• Synchronous design easier; we will solely deal with synchronous systems at present

Moore and MealyRecall:

• Moore: outputs solely a function of present state

• Mealy: outputs a function of present state and inputs

• Both state machines

• ASM : formal; notation for design of state machines

A Traffic Light Problem

Major Road

Minor Road

Rules• Two States: G and R• Major road has priority: normally green• Minor road normally red• Car on minor road triggers a sensor, causes lights to

change to red• If lights change a timer is started• When time expires, a “timerdone” is asserted => causes

lights to go back to red on minor, green on major• Simple, but has deficiencies

ASM Chart

Major = GreenMinor = Red

Car?No

G

Yes

Start Timer

Major =RedMinor = Green

Timerdone?Yes

R

No

Describing Traffic Light Controller in VHDL

• Use concurrent VHDL constructs• Remember VHDL processes execute

concurrently• Process triggers when signal on sensitivity

list changes• State machine transition on clock edge• Present state musty be held in an internal

variable

Holding the State

• Use an enumerated type ie in architecture, before process

type state_type is (G, R);

• Automatic range checking

• Possible values in state names

Traffic.vhd: Entity

LIBRARY ieee;USE ieee.std_logic_1164.all;

ENTITY traffic ISPORT (CLK, timerdone, car: IN std_logic;

start_timer, major_green, minor_green: OUT std_logic);

END traffic;

Traffic.vhd: Process 1ARCHITECTURE two_process OF traffic IS

TYPE state_type IS (G, R); -- enumerate state type

SIGNAL present_state, next_state : state_type; -- declare two signals of type state_type

BEGIN

P1: PROCESS (CLK) -- this process models the next state -- decoder, triggers on clock

BEGINIF (rising_edge(CLK)) THEN -- note use of

-- "rising_edge" functionpresent_state <= next_state;END IF;

END PROCESS P1;

P2: PROCESS (car, timerdone, present_state)-- this process models the required logic

BEGIN start_timer <= '0'; -- assume major road has priority therefore timer not started

CASE present_state IS

WHEN G =>

major_green <= '1';

minor_green <= '0';

IF ( car = '1') THEN

start_timer <= '1';

next_state <= R;

ELSE

next_state <= G;

END IF;

WHEN R =>

major_green <= '0';

minor_green <= '1';

IF ( timerdone = '1') THEN

next_state <= G;

ELSE

next_state <= R;

END IF;

END CASE;

END PROCESS P2;

END two_process;

Two or Three Process

• Two process most common model for state machines

• Also possible to separate next state and output logic => a 3 process model

• See overleaf for a 3 process model of a state machine

Three Process Traffic Controller

BEGINP1: PROCESS (CLK)

-- this process models the --next state decoder, triggers on clock

BEGINIF (rising_edge(CLK)) THEN

-- note use of "rising_edge" functionpresent_state <= next_state;END IF;

END PROCESS P1;

• Entity and Process 1 as before

P2:PROCESS (car, timerdone, present_state)-- this process models the required next state logic

BEGINCASE present_state IS

WHEN G =>IF ( car = '1') THEN

next_state <= R; ELSE

next_state <= G;END IF;

WHEN R =>IF ( timerdone = '1') THEN

next_state <= G; ELSE

next_state <= R;END IF;

END CASE;END PROCESS P2;

P3:PROCESS (car, present_state)-- this process models the output logic

BEGIN

start_timer <= '0'; -- start_timer is an output

CASE present_state IS

WHEN G =>

major_green <= '1';

minor_green <= '0';

IF ( car = '1') THEN

start_timer <= '1';

END IF;

WHEN R =>

major_green <= '0';

minor_green <= '1';

END CASE;

END PROCESS P3;

END three_process;

Sequential Logic Blocks

• Build up collection of models

• Add new constructs as required

SR Latch

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY SRlatch2 IS

PORT (S,R : IN std_logic;

Q, Qbar: out std_logic); -- note of type "out"

END SRlatch2;

ARCHITECTURE dataflow of SRlatch2 IS

begin

P1: Process (S,R)

variable SR: std_logic_vector(1 downto 0);

begin

SR := std_logic_vector'(S,R) ; --form a vector

case SR is

when "00" =>

Q <= '1';

Qbar <= '1';

when "01" =>

Q <= '0';

Qbar <= '1';

when "10" =>

Q <= '1';

Qbar <= '0';

when others

=> null; -- no change, dummy statement

end case;

end process P1;

END dataflow;

D Latch

• Level, not edge sensitive

D Q

Enable


ENTITY Dlatch1 ISPORT (D, Enable : IN std_logic;Q: out std_logic);

END Dlatch1;ARCHITECTURE dataflow of Dlatch1 ISbegin

process (D, Enable)beginif (Enable ='1') then Q <= D;end if;end process;

END dataflow;

Edge Triggered D Flip-Flop

• Positive edge triggered

• Several Models possible

D Q

Clock


ENTITY DFF1 ISPORT (D, Clock : IN std_logic;

Q: out std_logic); END DFF1;ARCHITECTURE dataflow of DFF1 ISbegin

process begin

wait until (clock ='1');Q <= D;

end process;END dataflow;

LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY DFF1 IS

PORT (D, Clock : IN std_logic;Q: out std_logic);

END DFF1;

ARCHITECTURE algo1 of DFF1 ISbegin

process (clock)begin

if (clock = '1')and clock’event then Q <= D;end if;

end process;END algo1;

Edge Triggered D Flip-Flop

Set/ResetLIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY DFF1 IS

PORT (D, Clock, Reset : IN std_logic;Q: out std_logic);

END DFF1;ARCHITECTURE algo2 of DFF1 ISbegin

process (clock, Reset)begin

if (Reset = '0') then -- active low, asynchronous resetQ <= '0';elsif (clock = '1' and clock'event) then Q <= D;end if;

end process;END algo2;

Rising Edge and Falling edge

• Remember std_logic has nine values

• Thus elsif (clock = '1' and clock'event) then

• It could mean a transition from state other than 0

• Better to use pre-defined functions rising_edge and falling_edge

More on Styles of VHDL Descriptions

• Three essential styles– structural

• consists of component instantiation• netlist approach

– dataflow• concurrent signal assignments in an architecture• outside of processes

– behavioural• uses processes

Structural VHDL: example

• 2-4 decoder using inverter and and gates:

B1

A1D0

D3

D2

D1

Library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity inv1 is

port (A: in std_logic;

out1: out std_logic);

end inv1;

architecture structural of inv1 is

begin

out1 <= not a;

end structural;

Library IEEE;use ieee.std_logic_1164.all;entity and2 is

port (A, B: in std_logic;

out1: out std_logic);end and2; architecture structural of and2 is beginout1 <= a and b;end structural;

A Structural Description

-- 2-4 decoder using structural approach

-- Inputs are A1, B2; outputs are D0,D1.D2,D3

Library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity decoder2_4 is

port (A1, B1: in std_logic;

D0,D1,D2,D3: out std_logic);end decoder2_4;

2-4 contd.architecture structural of decoder2_4 is component Inv1

port(A: in std_logic; out1: out std_logic);

end component;component AND2

port(A,B: in std_logic; out1: out std_logic);

end component;signal A1_n , B1_n: std_logic;

2-4 contd.begin g1: Inv1 port map (A => A1, out1 => A1_n);-- invert Ag2: Inv1 port map (A => B1, out1 => B1_n);-- invert Bg3: AND2 port map (A =>A1_n, B => B1_n, out1 => D0);g4: AND2 port map (A =>A1_n, B => B1, out1 => D1);g5: AND2 port map (A =>A1, B => B1_n, out1 => D2);g6: AND2 port map (A =>A1, B => B1, out1 => D3);

end structural;

Structural VHDL• Specifies what is the system made of, what are the sub-

systems or component and how are they interconnected• structural description allows multiple levels of

hierarchy• the sub-systems may be specified in terms of more

primitive sub-sub-systems.. Etc• finally, each primitive component is specified in a

behavioural/ dataflow way• In VHDL, the use a component requires the declaration

and instantiation of this component

Component Declaration • A component declaration declares a virtual

design entity interface

• Simplified Syntax:

component component_name

generic (generic_list);

port (port_list);

end component component_name;

• A component represents an entity/architecture pair• It specifies a subsystem, which can be instantiated in

another architecture • A component must be declared before it is instantiated• The component declaration defines the virtual interface

of the instantiated design entity ("the socket") • it does not directly indicate the design entity• components are declared in the declarative part of an

architecture

Component Declaration

Example architecture structural of my_design is

component XOR_4

port (A,B: in BIT_VECTOR(0 to 3); C: out BIT_VECTOR(0 to 3));

end component XOR_4;

signal S1,S2 : BIT_VECTOR(0 to 3);

signal S3 : BIT_VECTOR(0 to 3);

begin

X1 : XOR_4 port map(S1,S2,S3);

end architecture structural;

Component Instantiation • An instantiation statement defines a component of

the design entity in which it appears

• It associates signals or values with the ports of that component

• It associates values with generics of that component.

• Component instantiation is like plugging a hardware component into a socket

Simplified Syntax --INSTANTIATION OF A COMPONENT

label1 : component_name

generic map ( generic_association_list )

port map ( port_association_list );

--INSTANTIATION OF A DESIGN ENTITY

label2 : entity entity_name [(architecture_identifier)]



--instantiation of a configuration

label3 : configuration configuration_name



INSTANTIATION OF A COMPONENT architecture Structural of ALU is

signal X,Y,S,C : bit;

component HalfAdder

port (In1, In2 : in bit; Sum, Carry : out bit);

end component HalfAdder;

begin

HA : HalfAdder port map (X,Y,S,C);

. . .

end architecture Structural;

INSTANTIATION OF A DESIGN ENTITY

entity XOR_4 is

port(IN1,IN2: in BIT_VECTOR(0 to 3);

OUT1 : out BIT_VECTOR(0 to 3));

end entity XOR_4;

architecture xor4gate of XOR_4 is

begin

OUT1 <= IN1 xor IN2;

end architecture xor4gate;

entity EXAMPLE is

--port of entity example

end entity EXAMPLE;

architecture STRUCTUREAL of EXAMPLE is

signal S1,S2 : BIT_VECTOR(0 to 3);

signal S3 : BIT_VECTOR(0 to 3);

begin

X1 : entity WORK.XOR_4(xor4gate)

port map (S1,S2,S3);

end architecture STRUCTURAL;

Port mapping

• Named association: each port is assigned a signal using the explicit port name– example:

port map (A => A1, out1 => A1_n);

• Positional association: signals in port mapping are listed in the same order as the port in the component’s entity declaration– example

port map (S1,S2,S3);

Configuration

• the configuration construct provides information that binds a component to an entity/architecture pair

• it specifies the entity and the architecture of the component

• more flexible than component/entity instantiations

Simplified Syntax:

configuration configuration_name of entity_name is

-- configuration declarations

for architecture_name

for instance_label:component_name

use entity library_name.entity_name(arch_name);

end for;

-- other for clauses

end for;

Example

entity and_e isport (x1,x2: in bit;y: out bit);end entity;

architecture behavioural of and_e is

begin y <= x1 and x2;


entity nand_e is port ( x1,x2:in bit; y: out bit);

end entity nand_e;

architecture behavioural of nand_e is begin

y <= x1 nand x2;end architecture behavioural;

Exampleentity gates is

port ( a,b: in bit; y : out bit);

end entity gates;architecture structural of gates iscomponent and_e

port(x1,x2: in bit;y: out bit);

end component;component nand_e

port(x1,x2:in bit; y: out bit);

end component;

signal s1,s2: bit;beginu1: and_e port map (a,b,s1);

u2: nand_e port map (a,b,s2);

u3: and_e port map (s1,s2,y);


Exampleconfiguration config of gates is

for structuralfor u1: and_e

use entity work.and_e(behavioural);end for;for u2: nand_e

use entity work.nand_e(behavioural);end for;for u3: and_e

use entity work.and_e(behavioural);end for;

end for;

end configuration config;

Parameterised Structures • The generate statement simplifies description of

regular design structures

• used to specify a group of identical components using just one component

• This component is replicated a certain number of times

• similar in appearance to the for…loop construct

Syntax

For…generate

label : for parameter in range generate

{ concurrent_statements }

end generate;

If...generate

label : if condition generate

{ concurrent_statements }

end generate;

For …generate

--4-bit adder

library ieee;

use ieee.std_logic_1164.all;

entity adder is

generic ( n: integer := 4);

port ( a, b: in std_logic_vector (0 to n-1);

r: out std_logic_vector (0 to n-1));

end entity adder;

FAFAFA FA

a 0a 1a 2a 3 b 1

r0r1r2r3

'0'

b 2b 3 b 0

For…generatearchitecture structural of adder is

component fulladder

port ( in0, in1, in2: in std_logic;

carry, sum: out std_logic);

end component;

signal carry: std_logic_vector (0 to n);begin

carry(0) <= '0';

loop1: for i in 0 to n-1

generate

label1: fulladder port map ( carry(i), a(i), b(i),carry(i+1), r(i) );

end generate;


Brief History

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