Bottom half – ch 0-5 placed & routed FE PS PROC FIFO TRIG OSC RX/SHAP ADC DAC VME.
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Transcript of Bottom half – ch 0-5 placed & routed FE PS PROC FIFO TRIG OSC RX/SHAP ADC DAC VME.
![Page 1: Bottom half – ch 0-5 placed & routed FE PS PROC FIFO TRIG OSC RX/SHAP ADC DAC VME.](https://reader037.fdocuments.net/reader037/viewer/2022083119/5a4d1aea7f8b9ab05997a795/html5/thumbnails/1.jpg)
Bottom half – ch 0-5 placed & routed
FEPS
PROC
FIFOTRIG
OSC
RX/SHAP
ADC
DAC
VME
![Page 2: Bottom half – ch 0-5 placed & routed FE PS PROC FIFO TRIG OSC RX/SHAP ADC DAC VME.](https://reader037.fdocuments.net/reader037/viewer/2022083119/5a4d1aea7f8b9ab05997a795/html5/thumbnails/2.jpg)
Top half
JTAG
PS
MAIN
FE
VME
FLASH
![Page 3: Bottom half – ch 0-5 placed & routed FE PS PROC FIFO TRIG OSC RX/SHAP ADC DAC VME.](https://reader037.fdocuments.net/reader037/viewer/2022083119/5a4d1aea7f8b9ab05997a795/html5/thumbnails/3.jpg)
Remaining board design work • Test pulser (sch+layout)• Input signal routing (goes around test pulser stuff, do that 1st)• +1.5V reference (sets ADC input common-mode)• A few more connections to define on main/vme FPGA• offset DAC control• switching regulator phase control• status LED’s
• sub new FET part for RX power supply (prototype ran too hot)• pcb mechanical – handle mounts, VXS connector placement• thermal vias for ADC chips• some bypass caps to be added still• local trigger (multiplicity sum line and trigger comparator)• +2.5V linear regulator (for VCCAUX & digital signals), Xpower estimate work to check 1st
Then:
• channel step & repeat• copy to mezzanine board• flip connectors to bottom for mezzanine board
Then:
• clean silkscreen• final DRC• review, review, review…• fabricate