PSU-Physics PH-315 Andrés La Rosa

Bipolar Junction and Field Effect

TRANSISTORS _______________________________________________________________________________

I. PURPOSE

To familiarize with the working principle and characteristics of transistors, including how to properly implement their DC bias. The bipolar junction transistor as well as the field effect transistor will be considered.

II. THEORETICAL CONSIDERATIONS

II.1 The pn junction II.1.1 Harnessing electrical conductivity in semiconductor materials

II.1.2 Formation of the depletion layer II.1.3 The Fermi Level

II.1.4 Effects of Forward and Reverse Bias Voltage on the Size of the Depletion Region

II.1.5 The diode

II.2 Bipolar Junction Transistor

II.3 Field Effect Transistor (FET)

II.3.1 Junction Field Effect Transistor (JFET)

II.3.2 Metal Oxide Semiconductor Field Effect Transistor (MOSFET)

II.3.2A Metal oxide semiconductor (MOS) capacitor

II.3.2B MOSFET

III. EXPERIMENTAL CONSIDERATIONS

III.1 The Bipolar Junction Transistor III.1.1 Transistor’s characteristic curves.

Current gain and the value III.1.2 DC bias circuit and the operating point III.1.3 Small signal amplifier (this section is not required in Winter 2016)

III.2 The Field Effect Transistor III.2.1 The Junction Field Effect Transistor (JFET) III.2.2 The Metal Oxide Semiconductor Field Effect Transistor (MOSFET)

References Ben G. Streetman, Solid Sate Electronic Devices, Prentice Hall

J.R. Cogdell, Foundations of Electronics, Prentice Hall.

Horowitz & Hill, The Art of Electronics, Cambridge University Press James Brophy, Basic Electronics for Scientists, McGraw-Hill.

2

II.1 The pn junction

II.1.1 Harnessing electrical conductivity in semiconductor materials

At T=0, conductivity = 0

A Silicon atom has 4 valence electrons. Joined by covalent bonds, Si atoms form a lattice structure.

At zero temperature Silicon is an insulator because all its valence electrons participate in the bonding. It lacks electrons that can wander free around the crystal structure.

Intrinsic conductivity at T ≠ 0

Here we consider a Si material without foreign atoms (just pure silicon atoms).

Thermal generation of conduction electrons At room temperature (kT~ 0.025 eV),

there is a non-vanishing prob ability (~ e-

Eg/2kT) that some electrons will be able to

break away from the (Eg=1.12 eV) bonding.

They set almost “free” and become conduction electrons.

These electrons are able to participate in the conductivity of silicon under the presence of an external electric field.

A typical value of the concentration of conduction electrons generated in this manner, at room temperature, is no ~1.4x1010 e-/cm3. Holes also contribute to the conductivity

Notice above that that the creation of a new conduction electron leaves their Si atoms with one bonding vacancy. This bonding vacancy is called a “hole”.

Under the presence of an external electric field, a bonded electron from a Si atom nearby will have a tendency to fill-in this bonding vacancy. When that happens a new hole (with its associated positive ion) is left behind, which triggers the creation of another hole and so on. The net result: a net positive charge is transported along the filling of holes.

Intrinsic conductivity Since a hole is created simultaneously with a conduction electron, the concentration of holes po equals the concentration of electrons: p0 – n0.

4 4

4 4

4

4

4

4

4 4 4 4

At T = 0 K Si: [Ne]3s23p

2

Fig.1. Si atoms arranged in a crystal network.

4 4

4

4

4

4

4

4 4 4 4

Hole

4

Free

(conduction)

electron

At T = 300 K

Fig. 2. Electrons and holes contribute to the electrical conductivity.

3

Extrinsic conductivity

n-type

Si crystal doped with donor atoms (5 e- in their valence shell). Four e- participate in the bonding with Si atoms, while the fifth becomes almost free of any bonding. With a little bit of energy this fifth e- becomes free to wander around the entire silicon material. Example of doping level: 1016 arsenic atoms/cm3. Notice the ability to doped Si with foreigner atoms with concentrations in excess of the intrinsic regime. p-type Si doped with acceptors atoms (3 valence e-). Boron atoms, for example. The three e- participate in the bonding with Si atoms, creating a bond vacancy to be filled-in. That is, acceptor atoms create holes, which also participate in the conductivity (as explained above).

Accordingly, the presence of donors and acceptors increases the electrical conductivity of the material.

4 4

4

4

4

4

4

4 4 4 4

Hole

3

Acceptors

Donors

4 4

5

4

4

4

4

4 4 4

4

4

Free

electron

Fig.3 Extrinsic conductivity. Harnessing electrical conductivity by inserting into the Si crystal matrix foreign impurities

4

II.1.2 Formation of the depletion layer

Characteristics of p and n semiconductor materials

p p-material

n-material

n

Electron energies

e-

acceptors atoms

Electrically neutral material

Electrically neutral material

x

+ + + + + +

Acceptor’s energy levels

donor’s energy levels

e-

Free electrons

donor atoms

+ + + + +

“Holes”

Fig. 4 In the p-material (n-material) the energy level of impurities, indicated by pink (green segments) are located near the valence (conduction) band. Left: Electrons from the valence band ‘jump’ to the acceptor impurities, thus creating a negatively charged impurity and leaving behind a free “hole”. The hole is equivalent to a “free” positive charge. Right: Electrons from the donor impurities ‘jump’ to the conduction band where they are free to move, and leaving behind a positively charged donor impurity.

5

The p and n materials are brought together

p

p-material

n-material n

Electron energy

Electrically neutral

material

Electrically neutral

material

x

+ + + + + +

NA acceptors /cm3

ND donors/cm

3

+ + + + +

Charged region

i = i (x)

p n

- - - - - -

- - - - - -

+

+

+

+

+

+

+

+

+

+

+

+

Case: NA > ND

W Depletion region

Built-in electric field

Practically no free carriers in this region

Cross section area A

Fig. 5 Upon forming a pn junction, free electrons from the n region diffuse into the p region, leaving behind a positively charged region. Similar situation occurs with the holes. This result into the formation of a charged depletion region formed at the pn junction. Notice the depletion region penetrates more in the lighter doped material.

6

+

-

qND

qNA

xno

-xpo

Q=AxnoND

Q=-AxpoNA

W

Fig. 6 An approximate mode assumes uniform charge distribution of charges in each section of the depletion layer.

+

W

xn0 -xp0

i

)(1

DqNdx

d

ε

)(1

AqNdx

d

ε

Built in Electric filed

Fig. 7 Electric field built in inside the depletion layer, corresponding to the charge distribution assumed in Fig. 3.

Voltage across the depletion layer

no

po

x

x

o dxxV )(

2

2

1W

NN

NNqV

DA

DAo

ε

Notice, the higher the potential difference across the depletion layer, the wider the thickness of the depletion layer.

7

p n

i

e Vo Vo

Electrostatic potential

Energy of e-

x

i

x

Fermi level EF

W

EF

p n

p n

Depletion layer

Fig. 8 Left: The charges inside the depletion layer establish an electric potential Vo across the depletion layer. Right: The presence of the electric potential change across the pn junction is reflected in a bending of the conduction and valence band energy levels.

II.1.3 The Fermi Level

The Fermi level EF coincides here with the chemical potential of the system. At equilibrium the chemical potential is the same throughout the heterogeneous sample (as indicated in Fig. 5). The value of EF depends on the temperature, and the particular energy levels distribution in the semiconductor system).

The Fermi level also gives an indication of the concentration of free-electrons in the conduction band, as well as the population of free-holes in the valence band. The closer the Fermi level is to a given band determines the type of majority charges in the material. Thus, for example in Fig. 5, in a n-region the majority of carrier is composed by electrons; this is in agreement with the Fermi level being closer to the conduction band. On the other hand, in the p-region the majority of charge-carriers are holes; hence, the Fermi level is located near the valence band. The Fermi Level in intrinsic semiconductor material When the semiconductor does not contain impurities (i.e. no donor nor acceptor atoms), the material is called intrinsic.

For intrinsic semiconductor material

electron concentration concentration of holes in the conduction band. = in the valence band. (1)

ne (electrons/cm3) nh (holes/cm3)

8

Eg e-

Fig. 9 Thermal generation of electron-hole pair carriers. Electrons are able to jump from the valence to the conduction band, leaving behind a free-hole.

The population of energy states by electrons follows quantum statistics (instead of the Boltzmann statistics). Electrons behave in the peculiar way that each allowed quantum state is occupied by only one electron. The probability that an energy state is occupied by an electron is given by the Fermi-Dirac distribution,

TkF BEE

Ef/)(

1 )(

e1 Fermi-Dirac distribution (2)

probability to find an electron in a level of energy E.

where we are using the EF (the Fermi level) indistinctly from the thermodynamic chemical potential of the (homogeneous or heterogeneous) semiconductor material. As mentioned above, EF depends on the temperature, and on whether the material is doped with impurities or not.

Notice: 1- f(E) is the probability that the level of energy E is empty.

In other words,

1- f(E) is the probability to find a hole at the energy level E. (3)

9

EF

Eg

T≠0

Energy E

f (E) Probability to find a hole E=EV

1/2

1

Probability to find an electron at E=EC

E

Carrier concentration

nh

EV EC

ne

EF

Ei

ne =nh ≡ni

Fig. 10 For an intrinsic material, the Fermi level EF is located very close to the middle of the band-gap. This level is also denoted by Ei.

At a given finite temperature T≠0, the intrinsic carrier population is given by,

TBkFEE

n/)(

eVC NNi (This is a fixed number for a (4)

given finite temperature)

where NC and NV are quantities that depend on the temperature and on the specific characteristics of the material.

10

The Fermi Level in extrinsic semiconductor material

EF

Eg

Energy E

f (E)

Probability to find

a hole at E=EV

1/2

1

Probability to find an

electron at E=EC

E

Carrier concentration

nh

EV EC

ne

EF

Ei

Intrinsic case

Donor impurities

Ei

ne ≠ n h

Fig. 11 The Fermi level in extrinsic material illustrated for the case of a semiconductor doped with donor atoms.

In the extrinsic case, ne (electrons/cm3) ≠ nh (holes/cm3)

There is a useful expression that gives the carriers population of the extrinsic case, in terms of

the intrinsic population ni given in (4),

TBkiEFEnn

/)(

eie (5)

TBkFEiEnn

/)(

eih

This expressions are very useful in the analysis of devices. The location of the Fermi level EF relative to the Fermi level Ei corresponding to the intrinsic case determines the population of free-electrons and free-holes in the conduction and valence bands, respectively.

11

II.1.4 Effects of Forward and Reverse Bias Voltage on the Size of the Depletion Region

i = i (x)

p n

- - - - - -

- - - - - -

+

+

+

+

+

+

+

+

+

+

+

+

Case: Vext=0 NA > ND

W Depletion region

Built-in electric field

Practically no free carriers in this region

Cross section area A

i = i (x)

p n

- - - - - -

Case: Vext > 0 NA > ND

W Depletion region W decreases

+

+

+

+

+

+

+

+

ext

External forward bias voltage

i = i (x)

p n

- - - - - -

Case: Vext < 0

NA > ND

W Depletion region W increases

+

+

+

+

+

+

+

+

- - - - - -

- - - - - -

+

+

+

+

+

+

+

+

External reverse bias voltage ext

Fig. 12

12

II.1.5 The diode

Forward bias

e- energy

x

n p n p

e-

ext )1

/(

kTeBE

o

VII e

Vpn Vth

I Vpn

Forward

bias

Fig. 13a

e- energy

x

n p n p

e-

ext )1

/(

kTeBE

o

VII e

Vpn

I Vpn

Reverse

bias

Fig. 13b

13

II.2 Bipolar Junction Transistor

Transistor modeled as a current amplifier Transistor is a 3-terminal device: emitter, base, collector. They are available in two flavors: npn and pnp.

npn pnp

base

collector

emitter

base

collector

emitter

Fig. 14

Diode model: An initial understanding of the transistor can be obtained considering the base-emitter and the base-collector as diodes.

C

E

B

0 Volts

p n

�V2 �> � V1�

n C

E

B 0 Volts

n p

p

+�V1�

|V2| |V1| |V2| > - |V2|

|V1|

Fig. 15

In that context, let’s analyze in more detail the npn transistor.

Consider first the emitter-base diode.

e- energy

B E

x

n p n p

e-

B E

ext C

E

B p n

e-

)1/

( kTe

BEo

VII e

VBE Vth

I

a) b) c) Fig. 16 Analysis of the base-emitter pn junction. a) The figure on the left shows the energy band diagram of the (base-emitter) pn junction under equilibrium conditions (no external voltage applied); a barrier exist for the electrons (solid circles in the figure) to cross from the n-region to the

14

p-region. The red line is the Fermi level. The figure on the right shows that under an external forward bias (voltage at p greater than the voltage at n), the barrier is lowered and a forward bias flow of electrons is established. b) The forward bias current depends critically on the base-emitter voltage. The current is significant when the VBE voltage is greater than a threshold voltage (~ 0.7 volt for the case of silicon). c) When the p-base is lightly doped the net bias current is mainly constituted by electrons from the n-doped emitter.

The p region is made lightly doped, thus the forward current is constituted mainly by electrons from the n-doped emitter. The few electrons arriving to the p-type base-region implicitly become minority carriers in the host region of majority holes population. Subsequently they move by diffusion. If the base region is made very thin (smaller than the diffusion length), then those minority carriers reach also the collector where they are swept by the reversed biased that exists at the base-collector boundary. The finite time taken by the minority carriers to cross the base-region limits the high-frequency

response of the transistor. Hence, the p region (base) is made narrow (~ 0.5 m) compared to the diffusion length. That way, out of a number of arriving to the base, only a few are lost by recombination with the host holes at the base and most diffuse to the depletion region of the base- collector junction (see Fig. 17).

The base-collector diode.

Since |V2 | > |V1 |, the latter being of the order of 0.7 V, this diode is reversed biased. Thus, the role of the VBC voltage is just to sweep the charges that, after arriving from the emitter to the base, diffuse to the collector.

For this reason, it is found that the collector current varies very little with the collector voltage.

C

E

B

p

n

e-

e-

e-

C

E

B

p

n

IE IB

IC

n

|V1|

|V2| |V2|

|V1|

n

|V2| >|V1|

Fig. 17 Transistor currents Left: Injection of majority carriers from the emitter. A relatively small numbers reaches the base but most are swept towards the collector. Right: Equivalent picture of the left diagram, but in terms of the more formal currents.

15

C E B

p

n

e-

e-

e-

C

E

B

p

n

IE

WB

IC

n

|V1| IE

|V2|

RL

n

n n p

A

IB e-

e-

IC

npn IC

VBC

Active region

Fig. 18 Transistor circuit configuration with the npn and depletion layer regions. The injection of electron from the emitter to the base is controlled by the VEB voltage. By making the width of the base WB very thin (smaller than the diffusion length), the electrons diffuse towards the BC junction. In the BC depletion region the electron are swept by the reversed bias. Notice, the collector current will be practically independent of the particular value of the sweeping VBC voltage, since any value of the reverse voltage would be enough to sweep the electrons (that is, the collector current will change little when changing the load resistor RL).

When the transistor is properly electrically biased, the net result is:

IC is roughly proportional to IB

IC = hFE IB = IB (1)

The current gain hFE (also called beta) is typically about 100.

( is not a good transistor parameter; its value can vary from 50 to 250. It also depends on the collector current, collector-to-emitter voltage, and temperature.)

This represents the usefulness of the transistor. A small current into the base controls a much larger current flowing into the collector. That is, the transistor is a current amplifier.

II.3 Field Effect Transistor ( FET )

A field effect transistor is a three-terminal device in which the current through two terminals is controlled at the third (similar to the bipolar junction transistor.)

Field effect devices are controlled by a voltage at the third gate terminal (rather than by a current like in the BJT.) The FET nonexistent gate current is its most important characteristics.

The resulting high input impedance (which can be greater than 1014 is essential in many applications.

FET is a unipolar device; that is, the current involves only majority carriers.

The field effect transistors come in different forms:

Junction FET (JFET) based on controlling the depletion width of reversed-biased p-n junctions.

16

Metal-semiconductor FET (MESFET) results when the p-n junction is replaced by a Schottky barrier (i.e. a metal-semiconductor junction.)

When the metal is separated from the semiconductor by an insulator, a MISFET results. When an oxide layer is used as the insulator the device is called a MOSFET.

The various types of FET are characterized by high input impedance, since the control voltage is applied to a reversed-biased junction, or Schottky barrier, or across an insulator.

FETs are well suited for controlling the switch between a conducting state and a nonconducting state. That is, they fit very well in digital circuits. In fact MOS transistors are used in semiconductor memory devices. MOSFETs dominate microprocessors, memory and most high-performance digital logic.

Similarities between BJTs and FETs

Both are charge-control devices

Both have 3 terminals, the conduction between two electrodes depend on the availability of charge carriers, the latter controlled by a voltage applied to a third control electrode.

Difference between BJTs and FETs

The BJT is basically a current amplifier. [For a npn transistor, connecting the emitter-base in ~ 0.7 V forward bias overcomes its contact potential barrier causing electrons to enter the base-region. Most of these electrons (minority carriers in a p-type host base) are swept by the field of the reversed biased base-collector. Since after the 0.7 V the flow of electrons to the base grows exponentially for small base-emitter voltage variations, we end up with a device in which the collector current is controlled by small base current.]

In a FET, conduction in a channel is controlled by an electric filed, produced by a voltage applied to the gate electrode.

In an FET there are not forward biased junctions, so the gate draws no current. A consequence

of this is its high input impedance (greater than 1014 ). For applications as analog switches and highinput impedance, FETs have no equals.

II.3.1 Junction Field Effect Transistor (JFET)

A n-channel JFET has three terminals: gain (G), drain (D) and source (S).

The input signal is the voltage applied between the gate and source.

The output signal is the current from drain to source (e- flow from source to drain.)

17

Depletion region

Source S

Drain D

n Gate

G p

Gate

G p p p n

e-

S

VD

- Input

voltage

VG VG

+

- Channel

Drain

Gate

Source

Fig. 19 n-channel JFET. Left: Terminals in a FET. Center: For proper operation the (gate-channel) pn junction must be reversed biased, so that a depletion region is formed as shown. The drain is operated at a positive voltage relative to the source, hence the gate-drain end is more strongly reversed biased (thicker depletion layer and thinner channel) than the gate-source end (thinner depletion layer and thicker channel.) The depletion region acts as a non-conductor; the remainder of the channel acts as a resistor with peculiar properties. Right: Symbol of the n-channel JFET. The arrow in the JFET symbol is to identify the source (S) (because, otherwise, the source and the drain are architecturally symmetric).

Input characteristics. Because the gate-channel pn junction is reversed biased, very little current flows into the gate.

Consequently, the input impedance of the device is extremely high, up to 1012, and very little

energy is required to control de device. The gate controls the current in the channel through an electric field that affects the depletion region.

Output characteristics. Let’s analyze the circuit for a given fixed value of the input voltage VGS (gate-source voltage.)

Let choose VGS = 0 V: For small increasing values of the drain-source voltage VDS the current also increases, similar to the case of a simple resistor (ohmic region.) As VDS increases further, the current begins to level off because the channel narrows at the drain end (see Fig. 19.) When the drain-source voltage reaches the value VDS = -VP (VP is called the pinchoff voltage) a region of the conducting channel reaches a minimum size at the drain end. The current remains constant upon further increases of the VDS. This is the saturation region. (The electrons in the channel are free to move out of the channel and then through the depletion region attracted by the VDS voltage. The depletion region is free of carriers and has a resistance similar to silicon. However, an increase of VDS (which would tend to increase the channel current) will also increase the distance from drain to the

18

pinch-off point thus increasing the channel resistance. As a result, these two trends compensate as to keep the channel current constant.) 1

In the saturation region (although it would be better to call it the “active region”) the drain current is controlled totally by the input signal.

S

iD

+10V

G D

ID

0 1 2 3 (V)

1 mA

2 mA

VGS = - 1.5V

VGS = - 1V

VGS = 0V

iG ≈ 0 3 mA

4 mA

Saturation region

Ohmic region

VGS = VP = – 2V

2k

VDS , drain-source voltage

VGS

VGS

Fig. 20 Output characteristics of a JFET. A pinch-off voltage equal to -2 volts has been

assumed; the particular JFET you are using may have a different pinch-off voltage. For lower (negative) values of VGS, the voltage VDS at which pinchoff occurs decreases. The maximum current also decreases.

For VGS < VP :

The FET is cut off; no current flows regardless of VDS. The blockage of current occurs for the same reason (the growth of the depletion region due to the reversed bias).

19

Fig. 21 Source: http://www.physics.csbsju.edu/trace/nFET.CC.html

20

II.3.2 Metal Oxide Semiconductor Field Effect Transistor (MOSFET)

II.3.2A Metal oxide semiconductor (MOS) capacitor

Metal Semiconductor p-type

EF

Ec

Ev

Ei

Conduction band of the oxide

EF

Oxide

Energy

of e-

+ + +

Ef

A c c u m u l a t i o n D e p l e t i o n I n v e r s i o n

Ef

Semiconductor p-type

Ef

EF

Ec

Ev

Q

-

Q Q

- -

Ei EF

Ec

E v

Ei EF

Ec

E v

Ei

- - - - - - - - - - - - - - - - - -

Metal

Fig. 22

21

Depletion TBkFEiE

nn/)(

eih

Since Ei-EF decreases as the bands bent, the electron hole population decreases near the interface. This decrease implies that holes are leaving the region, leaving behind acceptors negatively charged; that is, a depletion layer is created.

Inversion TBkiEFE

nn/)(

eie

As the bands bend, EF -Ei passes from being a negative value to become a positive value when the applied positive voltage reaches a threshold value. Further increases of the applied

volatage makes the value of ne (free electrons) to increase. That is, free-electrons are created at the p-type semiconductor, the charge located near the interface.

II.3.2B MOSFET

Top Down

VD small

VD = VD,sat

VD > VD,sat

M O S F E T

SiO2

CHANNEL

22

Fig. 23

II.3.2C Floating gate non-volatile memory

a) Top Down FLOATING GATE NON-

VOLATILE MEMORY

SiO2

Fig. 24

III. EXPERIMENTAL CONSIDERATIONS III.1 The Bipolar Junction Transistor

III.1.1 Transistor’s characteristic curves. Current gain and the value III.1.2 DC bias circuit and the operating point III.1.3 Small signal amplifier (this section is not required in Winter 2015)

III.2 The Field Effect Transistor III.2A The Junction Field Effect Transistor (JFET) III.2B The Metal Oxide Semiconductor Field Effect Transistor (MOSFET)

III.1.1 Transistor’s characteristic curves. Current gain and the value

We will use general purpose transistors: 2N 2222, 2N 3906, or the npn 2N 3904. Use a npn transistor and setup the circuit indicated in the figure below.

Select RB and RC such that IC fall in the range of mA, and IB in the order of 5A to 200 A.

The suggested use of variable resistors is for you to be able to do the proper changes as to keep

the IB constant while obtaining the trace of one of the current collector curves.

TASK: Obtain the characteristic curves of the transistor. Plot about 04 curves, corresponding to

different values of base current. Label each trace with the corresponding value of IB as well as the value of VBE.

23

Vin

(+10V) Ammeter E

VCC (+ 10 V)

npn RC

RB

B A VCE

IC (mA)

VCE

C

IB1 (A)

IB2 (A)

IB3 (A)

A IC

IB

Active region

Vin

(+10V) Ammeter E

VCC (+ 10 V)

npn RC

RB

B

V

VCE

C

V

IC

IB 50 k

400

Fig. 25 Grounded-emitter setup for obtaining the collector current characteristics. IB is

approximately constant across the active region.

TASK: Estimate the experimental value of the transistor current gain

E

C

ii

. (2)

Keep in mind that usually the current gain is described in terms of the value of the transistor,

the latter being defined as,

1CEB iii

ii CC

III.1. 2 DC bias circuit and the operating point Given the transistor curves characteristics, our objective is to bias the transistor properly as to

make it function around a given operating point inside the active region (point P in the diagram

below, for example.) The procedure will help us understand how the output voltage depends on

the input voltage.

24

IC

VCE

50 A

100 A

10 mA

20 mA

P

Active region

E

RC

RB

B VCE

C

IC

IB Vin

(+ 10 V)

VCC (+ 10 V)

Vout

Fig. 26 Given the collector current characteristics. RC and RB should be selected to have

the transistor operating around the point P in the active region.

How to choose RC? Load line analysis Even though we do not know IC neither VCE a relationship between them can be obtained through the Kirchhoff’s law applied to the right side branch of the circuit above (and reproduced below for convenience.);

15V - IC RC - VCE = 0,

which leads to,

ECC VICC RR

V

1 15 IC decreases linearly with VCE.)

npn

+ 10 V RC

B VCE

IC

IC

VCE

10 mA

20 mA

CR

15V

+ 15 V

Load line IB

+ 10 V

Fig. 27 Application of the Kirchhoff law to the right-side branch of the circuit gives a

relationships to be satisfied by IC and VCE.

If we want to work with, for example, a current base of 50 , many values of Rc are possible. Still, there is a restriction to be satisfied, which is not to exceed the transistor’s heat dissipation tolerance. For example, the data sheet may specify,

VCE; max ICE; max < 350 mWatts

25

Applying this condition to our case, one obtains

(10 V) ( 10 V/RC ) < 350 mWatts

Thus, in this case, a resistor RC > 0.5 K

would be good enough

How to choose RB? Since we want to operate the transistor

at the point P, that is a current base of 50 A, all we have to do is to choose an RB that allows delivering a current of that magnitude

μA 50

0.7V10V~RB

which takes into account that, when operating in the active region, the base voltage is about 0.7 V (for silicon transistors.) The operating point P results then from the intersection of the load line and the transistor

curve corresponding to 50 A.

TASK: Set up the transistor to work at one point of the active region.

(For example, make the transistor to operate at 50 A base current and VCE= 5 Volts).

How the output voltage depends on the input voltage

Instead of using a fixed Vin voltage, vary its value a bit as to produce slightly different base currents. Check what happens with VCE . The diagram in Fig. 29 illustrates the expected variation of the VCE voltage.

IC

VCE

100 A

20 mA

CR

10V

+ 10 V

P

VCE

IC IB=50 A IB

B

E

RC

RB

B VCE

C

IC

IB Vin

VCC (+ 10 V)

Vout

Fig. 29 Small variations of IB moves the operating point P along the load line, causing a

variation of VCE (and, correspondingly, a variation in IC.)

TASKS:

Make a plot of Vout vs Vin Notice, in this case, Vout = VCE

IC

VCE

50 A

100 A

10 mA

20 mA

P

CR

10V

+ 10 V Fig. 28 Load line superimposed with the transistor characteristic curves.

26

For Vin use an independent voltage source (vary the voltage from 0 to 10 volts).

Verify that the plot looks like the graph shown in figure 30.

From this experimentally obtained graph, evaluate the voltage gain: Vout/ Vin

Vout

Vin

Transistor

OFF Transistor

(saturated)

ON

VCC

Fig. 30 The greater Vin, the greater IB, the greater IC and greater drop of

voltage across RC, the lower VCE voltage.

NOTE: Notice in figures 29 and 30, that the greater Vin, the greater IB, the greater IC and greater drop of voltage across RC, the lower VCE (output voltage.) Thus, small variations of the input voltage around a given value will be 180o out of phase with the output voltage.

III.1.3 Small signal amplifier (Not required in 2016) Jump to section III.2

A large signal amplifier operates the transistor in its full range of operation, from near cutoff to near saturation (from small IC currents to large currents). Such an operation mode is quite suitable for digital electronics application, where LOW and HIGH signal levels determine the “0” and “1” binary information.

Other applications require small-signal amplifiers. For a given configuration, where the transistor operates at a given point of the active region, an small modulation of the base-current translate into a modulation of the collector current (picture a small audio signal being amplified by the transistor). If high amplifications are required, several small-signal amplifiers can be cascaded in series. In this laboratory session we will construct and analyze just one small-signal amplifier stage. A small-signal amplifiers must have:

a dc bias circuit for placing the transistor in its amplifying region (VERY IMPORTANT).

a mean for introducing the input signal

a mean for supplying its output signal to the next stage.

The circuits used in the previous section deal with the first two aspects. But, as it turns out, such circuits are very sensitive to temperature variation. For that reason, we will be modify it a bit, but their equivalence with our older circuit will become transparent in the course of the

discussion. Once the circuit is properly DC biased, we will proceed to input a small AC signal.

R1

5.6 K

npn E

VCC = + 10 V

RC

1 K

R2

50K

B

Vout

C

IC

Vin

Fig. 31 DC bias circuit (accomplished by the resistance R1 and R2).

27

(The coupling of a circuit stage to another will be addressed in Lab #4, when we study the concept of input and output impedance).

III.1.3.A Modified DC-bias Circuit. Placing the transistor in its amplifying region. The simple bias circuit in Fig. 29 above is generally not satisfactory because the operating point shifts drastically with temperature.) A more satisfactory transistor bias is obtained when using a voltage divider, as shown in Fig. 31.

TASK: Construct the circuit shown in Fig. 31.

Thevenin equivalent circuit analysis

We can use the Thevenin’s theorem to show the equivalence between the circuits in Fig. 29 and Fig. 31. This is made more evident by re-drawing Fig. 31 as shown in Fig. 32 below.

Through the Thevenin theorem one can claim that both circuits, the ones at the left and right sides of Fig. 32 are equivalent. Analyzing the shaded area one obtains:

The Thevenin voltage VBB is the open-circuit voltage (voltage across XY in the circuit

when no external load is applied) 121

RRR

VV CC

BB

. (VBB = (10V/55 k )(5 k ) =1V.)

RB designates the Thevenin equivalent series resistance. The short circuit currents (i.e. the currents when X and Y are shorted) are VCC/R2 and VBB /RB respectively. Since the

circuits are equivalent these two current must be equal. Hence, BBCC

B VV

RR 2 ; using the

value for VBB obtained above, results 21

12

RR

RRRB

(RB = (5 k x 5 k ) / (55 k ) =5 k ).

npn E

X

RC R2

50K

B

Vout C

R1

5.6 K

VCC =

+10V

npn E

RB B

Vout C

VBB

VCC =

+10V

Y

X

Y

VCC

=+10V

RC

1 K

Fig. 32 DC bias circuit and its Thevenin equivalent. The latter helps to calculate the different parameters associated to the intended operating point of the transistor (using the analysis described in the previous section) based on the values of R1 and R2.

TASKS: For the final values that you use for R1 and R2 calculate the Thevening values for VBB and RB.

Select the proper value of RC such that the transistor work in the active region. THIS IS VERY IMPORTANT. More specifically, choose RC such that VCE is ~ 4 Volts.

28

(An RC ~ 1 k should work).

R1

5.6 K

npn E

VCC = + 10 V

RC

1 K

R2

50K

B

Vout

C

IC

Vin

npn E

RC RB

B

Vout C

VBB VCC = +10V

IB IC

Fig. 33 Equivalent representation of the circuits in Fig. 32.

III.1.3.B Connecting to an oscillator Once the transistor is properly DC biased (VCE ~ 4 volts), proceed to connect the voltage

from a signal generator. See Figure 14. If the oscillator is connected directly at the Vin, unwanted DC voltage offset from the oscillator may change the bias level and/or draw some current away from Ib., and thus potentially spoil the operation point designed in the previous section. As a precaution, it is normally convenient to put a capacitor in series with the oscillator

to block the flow of DC current. (You could try C1 =1f but be aware of the frequency range of operation. Since the impedance of the capacitor is frequency dependent, make sure the capacitive reactance is small with respect to the other resistance you use at the input; i.e. you need a resistance to limit the base current).

TASK: Couple a small sinusoidal signal (start using ~0.03 V amplitude) into the circuit shown in Fig. 14 (Left diagram).

Monitor the input and output signals in the oscilloscope.

It is convenient to first monitor the output voltage vout with the oscilloscope set to DC mode, so you can be track whether its value is saturate or not.

Measure the AC voltage amplification, as well as the relative phase between the input and output voltage. (For this measurement, you may want to switch monitoring the output voltage with the oscilloscope in ac-mode).

For the coupling capacitance C1 that you choose (C1 = 1 F for example) find out the range of frequencies for which the circuit works properly. Find out also the range of input-voltages amplitude tolerated by the circuit.

Make the circuit to work in the low frequency (tens of hertz) and high frequency range (tens of kHz or higher). You may need a different capacitor for each of these two cases.

Notice:

Your circuit may not allow putting an ac-signal input signal vin of amplitude greater than ~ 0.3 V

29

(actually the exact value depends on the value you select for Rs), otherwise you would drive the transistor out of its operation range (this will be reflected in the clipping of the output signal).

npn E

VCC = + 10 V

RC

1 K

R2

50K

B vout C

IC

R1

5.6 K

vin Rs

Try Rs = 1 Kork

C1

C2

npn E

RC RB

B C

VBB

VCC = +10V

IB

IC

iB

vin vout Rs

C2

C1

Fig. 34 Left: Small signal amplifier circuit. Right: Equivalent circuit, which helps to differentiate the additional (AC) base current injected by the signal generator from the DC base current established by the bias circuit.

Evaluate the maximum amplitude of the input ac-signal that your circuit tolerates (i.e. avoiding

clipping in the output signal). Check whether a Rs= 1 k or Rs= 10 k works better in this regard.

Monitor the voltage vB at the base of the transistor all the time (with a multi-meter or, better,

with the oscilloscope); the value should be ~ 0.7 volts. Whenever you observe the output signal

“clipping” it may be because VB is deviating very much from this value (If vB is too high the

transistor lead to saturation; if vB is too low the transistor is off).

Eventually, you may need to change the value of RC to have the voltage vout in the proper range

(i.e. vout has to be greater than 0.7 volt, so it can allow ac variation without turning off the

transistor.)

It is convenient to first monitor the output voltage vout without the capacitor, so it can be tracked

whether its value is saturate or not. For that purpose monitor vout with the oscilloscope set to

DC mode. After you find your circuit working properly, insert the capacitor C2 (Fig. 35).

30

npn E

VCC = + 10 V

RC

1 K

R2

50K

B vout C

IC

R1

5.6 K

vin Rs

Try Rs = 1 Kork

C1

C2

npn E

RC RB

B C

VBB

VCC = +10V

IB

IC

iB

vin vout Rs

C2

C1

Fig. 35 Circuit is exactly the same in Fig. 34, except using an out coupling capacitor.

III.2A The Junction Field Effect Transistor JFET We will use the general purpose JFET 2N5457

TASK: Implement the JFET in the circuit outlined in Fig. 20. Determine the characteristics curves, as well as the pinch-off voltage VP.

Note: Alternative to using a fixed voltage source and a potentiometer, you may try using a fixed

resistor (maybe ~ 400 ) and a variable input voltage.

III.2B The Metal Oxide Semiconductor Field Effect Transistor (MOSFET)

1 http://en.wikipedia.org/wiki/Field-effect_transistor “Even though the conductive channel formed

by gate-to-source voltage no longer connects source to drain during saturation mode, carriers are not

blocked from flowing. Considering again an n-channel device, a depletion region exists in the p-type

body, surrounding the conductive channel and drain and source regions. The electrons which comprise

the channel are free to move out of the channel through the depletion region if attracted to the drain by

drain-to-source voltage. The depletion region is free of carriers and has a resistance similar to silicon.

Any increase of the drain-to-source voltage will increase the distance from drain to the pinch-off point,

increasing resistance due to the depletion region proportionally to the applied drain-to-source voltage.

This proportional change causes the drain-to-source current to remain relatively fixed independent of

changes to the drain-to-source voltage and quite unlike the linear mode operation. Thus in saturation

mode, the FET behaves as a constant-current source rather than as a resistor and can be used most

effectively as a voltage amplifier. In this case, the gate-to-source voltage determines the level of

constant current through the channel.”

31