Binary-Decision-Diagram (BDD) Application on Pass-Transistor Logic Design Tao Lin School of EECS,...
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Binary-Decision-Diagram (BDD) Application on Pass-Transistor Logic Design Tao Lin School of EECS, Ohio University March 12, 1998
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Transcript of Binary-Decision-Diagram (BDD) Application on Pass-Transistor Logic Design Tao Lin School of EECS,...
Binary-Decision-Diagram (BDD) Application on
Pass-Transistor Logic Design
Tao LinSchool of EECS, Ohio University
March 12, 1998
Content:
How to build the BDD for a certain How to build the BDD for a certain function;function;
Properties of BDD;Properties of BDD; Manipulation of BDD;Manipulation of BDD; Application of BDD to the Pass-Transistor Application of BDD to the Pass-Transistor
design.design.
Build a BDD for F:F=abc+b’d+c’d
F
a
bc+b’d+c’d b’d+c’d
T EF=aFa+a’Fa’
Build a BDD for F:F=abc+b’d+c’d
F
aT E
b b
c+c’d d c’d d
T E T EF=a(bFab+b’Fab’)+a’(bFa’b+b’Fa’b’)
F=aFa+a’Fa’
Build a BDD for F:F=abc+b’d+c’d
F
aT E
b b
1 0
T E TEF=a(bFab+b’Fab’)+a’(bFa’b+b’Fa’b’)
F=aFa+a’Fa’
.
.
.
c
d
c
E
E E
TT T
Order: a<b<c<d
Re-ordered-BDD (optimal):F=abc+b’d+c’d
F
a
Tb
1 0
T
E
E
c
dT T
E
E
Order: b<c<a<d
Properties of BDD:
The Reduced Ordered BDD (ROBDD) The Reduced Ordered BDD (ROBDD) is a canonical form;is a canonical form;
The size of the BDD (the number of The size of the BDD (the number of nodes is exponential in the number of nodes is exponential in the number of variables in the worst case; however, variables in the worst case; however, BDDs are well-behaved for many BDDs are well-behaved for many functions that are not amenable to two-functions that are not amenable to two-level representations (e.g., XOR);level representations (e.g., XOR);
Properties of BDD:
The logical AND and OR of BDDs have The logical AND and OR of BDDs have the same complexity. Complementation the same complexity. Complementation is inexpensive;is inexpensive;
Tautology can be solved in constant Tautology can be solved in constant time. Indeed, F is a tautology if and only time. Indeed, F is a tautology if and only if its BDD consists of the terminal node if its BDD consists of the terminal node 1;1;
Properties of BDD:
Covering problems can be solved in Covering problems can be solved in time linear in the size of the BDD time linear in the size of the BDD representing the constrains;representing the constrains;
On the other hand:
BDD sizes depend on the ordering. BDD sizes depend on the ordering. Finding a good ordering is not always Finding a good ordering is not always simple;simple;
There are functions for which the SOP There are functions for which the SOP of POS representations are more of POS representations are more compact than BDD;compact than BDD;
On the other hand:
In some cases SOP/POS forms are In some cases SOP/POS forms are closer to the final implementation of a closer to the final implementation of a circuit. For instance, if we want to circuit. For instance, if we want to implement a PLA.implement a PLA.
Manipulation of BDD:a
a
a
1 0
T Ea
T E
a’
10
Manipulation of BDD:a
a
a
1 0
T Ea
T
ab
1 0
b EE
T
Manipulation of BDD:a
a
a
1 0
T Ea
a+b
1 0
b
E
ET T
Manipulation of BDD:a
a
a
1 0
T Ea
ab
1 0
b
E
E
TTb
E
T
Minimization of BDD:
Identification of isomorphic sub-graphs;Identification of isomorphic sub-graphs; Removal of redundant nodes.Removal of redundant nodes.
Minimization of BDD:F
a
T b
1 0
T
E
E
c
d
T
T
E
E
c
d d d
a
1 0
1 0 1 0 1 0
T
T
T
E
E ET
T
F=abc+b’d+c’d
E
E
Minimization of BDD:F
a
T b
1 0
E
E
c
d
TE
c
d
a
1 0
1 0
T
T
T
E
ET
T
F=abc+b’d+c’d
TT Ed d
1 0 1 0
E
E
E
Minimization of BDD:F
a
T b
1 0
E
E
c
d
TE
c
d
a
1 0
1 0
T
T
T
E
ET
F=abc+b’d+c’d
TE
d
1 0
ETE
Minimization of BDD:F
T b
c c
d
T
E
F=abc+b’d+c’d
a
1 0
E
E
d
TEa
1 0
1 0
T
T
ET
TE
d
1 0
ETE
Minimization of BDD:F
T b
c
F=abc+b’d+c’d1 0
ETa
d
1 0
ET
ET
E
Realization of the BDD by the pass-transistor design:
F=abc+b’d+c’d
1 0
ETa
VDD
a a’
Realization of the BDD by the pass-transistor design:
F=abc+b’d+c’d
F
Tb
c
T
1 0
ETa
E
d
1 0
ET
E
a a’VDD
d d’VDD
c c’
b b’
F
Realization of the BDD by the pass-transistor design:
F=abc+b’d+c’d
F
Tb
c
T
1 0
ETa
E
d
1 0
ET
E
a a’VDD
d d’VDD
c c’
b b’
F
Conclusion
Pass-Transistor logic design has an Pass-Transistor logic design has an extremely simple cell library - just one extremely simple cell library - just one multiplexer;multiplexer;
BDD representation gives pass-transistor BDD representation gives pass-transistor design a powerful synthesis tool;design a powerful synthesis tool;
BDD also provides a rule to judge in which BDD also provides a rule to judge in which situation we should use pass-transistor logic situation we should use pass-transistor logic design and in the other case we should use design and in the other case we should use CMOS.CMOS.
