#BHE A0 DATA ACCESSED 0 0 Word From Even Address 0 1 Byte ...

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10. Explain why program/data aligned at even address in 8086 run faster. (4M) (Jan 10)(O) 11. Explain the physical memory organisation with diagrams. ANS: Physical Memory Organisation of 8086 The total address space 1 MB of 8086 is divided into 2 banks of memory—each bank of maximum size 512 KB. One is called the odd bank (or high bank) and the other even bank (or low bank). Even bank, Odd bank or both banks can be accessed by utilizing two signals BHE and A0. Table 12.1 shows the three possible references to memory. #BHE A0 DATA ACCESSED 0 0 Word From Even Address 0 1 Byte from or to odd address 1 0 Byte from or to even address 1 1 None The odd or high bank is selected for A0=1 and #BHE=0 and is connected to D15–D8 The even or low bank is selected for A0=0 and #BHE =1. Neither low bank nor high bank would selected for A0=1 and #BHE =1. The CS (chip select) of the memory is connected to A0 and BHE for EVEN bank and ODD bank respectively. Byte data with even address is transferred on D 7 D 0 and byte data with odd address is transferred on D 15 D 8 . 1. Byte operation from even address: A0=0, #BHE = 1 => even bank activated and odd bank deactivated Byte A accessed by D0-D7
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Transcript of #BHE A0 DATA ACCESSED 0 0 Word From Even Address 0 1 Byte ...

10. Explain why program/data aligned at even address in 8086 run faster. (4M) (Jan 10)(O)
11. Explain the physical memory organisation with diagrams.
ANS: Physical Memory Organisation of 8086
The total address space 1 MB of 8086 is divided into 2 banks of memory—each bank of maximum size 512 KB.
One is called the odd bank (or high bank) and the other even bank (or low bank).
Even bank, Odd bank or both banks can be accessed by utilizing two signals BHE and A0.
Table 12.1 shows the three possible references to memory.
#BHE A0 DATA ACCESSED 0 0 Word From Even Address 0 1 Byte from or to odd address 1 0 Byte from or to even address 1 1 None
The odd or high bank is selected for A0=1 and #BHE=0 and is connected to D15–D8 The even or low bank is selected for A0=0 and #BHE =1. Neither low bank nor high bank would selected for A0=1 and #BHE =1.
The CS (chip select) of the memory is connected to A0 and BHE for EVEN bank and ODD bank respectively.
Byte data with even address is transferred on D7 D0 and byte data with odd address
is transferred on D15 D8 .
1. Byte operation from even address: A0=0, #BHE = 1 => even bank activated and odd bank deactivated Byte A accessed by D0-D7
2. Byte operation from odd address: A0=1, #BHE = 0 => even bank deactivated and odd bank activated Byte A+1 accessed by D8-D15
3. Word operation from even address: A0=0, #BHE = 0 => even bank activated and odd bank activated Word (A, A+1) accessed by D0-D15
4. Word operation from odd address: Requires two cycles.
a) First cycle – A0=1, #BHE = 0 => even bank deactivated and odd bank activated Byte A+1 accessed by D8-D15
b) Second cycle –
A0=0, #BHE = 1 => even bank activated and odd bank deactivated
Byte A+2 accessed by D0-D7
So, accessing word from even address takes one cycle and from odd address takes two cycles. Due to this reason, for faster execution of program, programs are aligned at even address.
25. What is flash memory? Explain how a flash memory is interfaced to 8086. (6M) (DEC 2012)
ANS
Introduction to types of memory: • Simple or complex, every microprocessor-based system has a memory system.
• Almost all systems contain two main types of memory: read-only memory (ROM) and random access memory (RAM) or read/write memory.
There are four common types of memory used now: Read only memory (ROM)
Flash memory (EEPROM)
Pin connections common to all memory devices are:
Address connections: All memory devices have address inputs that select a memory location within
the memory device. Address inputs are labelled from A0 to An.
Data connections: All memory devices have a set of data outputs or input/outputs. Today many
of them have bi-directional common I/O pins.
Selection connections: Each memory device has an input that selects or enables the memory device. This kind of input is most often called a chip select (CS), chip enable (CE) or simply select (S) input
1. Control lines:
For ROM: 1. CS – Chip select- input signal – usually active low
Also known as CE(chip enable), S(select)
If the CE, CS, S input is active the memory devices performs the read.
If more than one CS connection is present, all the signals have to be active to perform read.
Usually activated by the address decoder
2. OE- output enable – input signal – usually low Also known as G (ground)
This allows data to flow out of the output data pins of the ROM.
Usually connected to #RD signal of 8086.
To read data from ROM both CS and OE need to be activated.
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UNIT 6
For RAM: 1. CS – Chip select- input signal – usually active low
Also known as CE(chip enable), S(select)
If the CE, CS, S input is active the memory devices performs the read.
If more than one CS connection is present, all the signals have to be active to perform read.
If it is inactive the memory device cannot perform read or write operation.
Usually activated by the address decoder
2. OE- output enable – input signal – usually low Also known as G (ground)
This allows data to flow out of the output data pins of the ROM.
Usually connected to #RD signal of 8086.
3. WE- write enable- input signal – usually low Also known as W(write)
This must be active to perform a write operation.
Usually connected to #WR signal of 8086.
To read data from RAM both CS and OE need to be activated.
To write data to RAM both CS and WE need to be activated.
If RAM has read and write as same control line as R/W then it should be activated properly for read and writes operations.
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2. Address lines: Input lines from 8086
These input lines select a memory location within the memory device. Decoders are used, inside the memory chip, to select a specific location.
The number of address pins on a memory chip specifies the number of memory locations.
3. Data lines:
A ROM device has data line as output lines and RAM devices as data lines as bidirectional lines (input/output pins).
Most memory devices have 1, 8 or 16 data lines. Number of lines = width of data storage, usually a byte D0-D7 Processor with wider data buses use multiple of such byte-wide memory devices ( in Parallel), e.g. 64-bit ⇒8 x 8-bit devices
For example:
1. If a memory chip has 13 address pins (A0 - A12) and 8 data lines (D0-D7) then it has:
213 = 23 x 210 = 8K locations.
Size of memory= 8K x 8 = 8K bytes
2. If a memory chip has 4K x 16, then it should have:
2N = 4K = 22 x 210 = 212 N=12
Address lines= 12= (A0 - A11)
Data lines = 16 = (D0- D15)
210= 1 Kilo bytes 220 = 1 Mega bytes 230 = 1 Giga bytes 211= 2 K bytes 221 = 2 M bytes 231 = 2 G bytes 212= 4 K bytes 222 = 4 M bytes 232 = 4 G bytes 213= 8 K bytes 223 = 8 M bytes 233 = 8 G bytes 214= 16 K bytes 224 = 16 M bytes 234 = 16 G bytes 215= 32 K bytes 225 = 32 M bytes 235 = 32 G bytes 216= 64 K bytes 226 = 64 M bytes 236 = 64 G bytes 217= 128 K bytes 227 = 128 M bytes 237 = 128 G bytes 218= 256 K bytes 228 = 256 M bytes 238 = 256 G bytes 219= 512 K bytes 229 = 512 M bytes 239 = 512 G bytes
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Types of Memory Basically two types:
1. ROM • Read Only Memory • Non Volatile data storage (remains valid after power off) • For permanent storage of system software and data • Can be PROM, EPROM or EEPROM (Flash) memory

Read Only Memory (ROM) Random Access Memory (RAM)
A memory device that maintains its data A memory device that can be read and permanently (or until the device is written. reprogrammed).
Non-volatile: It maintains its data even Volatile: It loses its data when the power without power supply. supply is switched-off
When the supply is switched-on it contains random data
Used to store Programs such as the BIOS and Used to store User programs that are loaded Data such as look tables from a secondary memory (disk) and e.g. the bit pattern of the characters in a dot Temporary data used by programs such as matrix printer. variables and arrays.
A ROM device can be A RAM device can be Masked ROM (Programmed by the Static
manufacturer) dynamic Programmable ROM (can be
program-erased-reprogrammed many times
Types of ROM (read only memory):
1. ROM o Device permanently programmed in factory by manufacturer o Must be large number (≈10,000 pieces) to justify cost o Once manufactured, cannot be erased or reprogrammed
2. PROM o Programmable ROM (Programmed once) o When number of devices required is too small to justify high factory
programming cost o Once programmed, cannot be erased for reprogramming.
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3. EPROM Erasable Programmable ROM (Programmed many)
Used when contents need to be changed, e.g. during the development phase of a product
Erased and reprogrammed in an EPROM programmer (i.e. not in situ)
Erasing is by exposure to UV light for say 20 minutes
4. Flash Memory-
The flash memory is also called as an EEPROM (electrically erasable programmable ROM), EAROM (electrically alterable ROM ), or a NOVROM ( nonvolatile ROM ) or RMM ( read mostly memory ).
These memory devices are electrically erasable in the system, but require more time to erase than a normal RAM.
Erasing and reprogramming is made so easy (and in situ) that it can be thought of as writing (hence RAM, but with data not volatile)
Erasing/writing takes longer time than writing into a RAM, but this is OK since it is done less frequent
Types of RAM (Random Access Memory):
1. SRAM 2. DRAM Static RAM (SRAM) Dynamic RAM (DRAM)
1. The basic element of a static RAM cell DRAM stores data in the form of is the D-Latch. electric charges in capacitors.
2. Data remains stored in the cell until it is Charges leak out, thus need to intentionally modified. refresh data every few ms.
3. SRAM is fast (Access time: 1ns). DRAM is slow (Access time: 60ns).
4. SRAM needs more space on the DRAM needs less space on the semiconductor chip than DRAM. semiconductor chip than SRAM.
5. SRAM more expensive than DRAM DRAM less expensive than SRAM
6. SRAM consumes power only when DRAM needs to be refreshed accessed.
7. SRAM is used as a Cache DRAM is used as the main memory
8. Bit SelectBit Select
Data In D Q Data Out Data In Data Out
Write En DRAM CellRAM Cell

UNIT 6
EPROM MEMORY
EPROM contains the series of 27XXX contains the following part numbers:
Where XXX gives kilobits.
To convert to Kbytes= XXX kilobits / 8= YY K x 8
For Example: 1. 2704 = 4 kilobits / 8 =512 x 8 2. 2716 = 16 kilobits / 8 = 2K x 8 3. 27128 = 128 kilobits / 8 = 16K x 8
2716 EPROM
Memory capacity = 16 kilobits / 8 = 2K x 8
Address line = 2K = 211 = 11 lines = A0 –A10 Data lines = 8 = D0 – D7 So, this device contains 11 address inputs and 8 data outputs.
When both control lines CS and OE are at logic 0, data will appear on the output connection.
If both the pins are not at logic 0, the data output connections remain at their high impedance or off state.
To read data from the EEPROM Vpp pin must be placed at logic 1. Requires One Wait cycle for interfacing with 8086/8088.
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Static RAM Interfacing:
TMS4016 SRAM • 2K x 8 RAM (same size as the 2716) • Memory capacity = 16 kilobits / 8 = 2K x 8 • Address line = 2K = 211 = 11 lines = A0 –A10 • Data lines = 8 = D0 – D7 (Data in / Data out) • So, this memory device has 11 address lines and 8-bit data lines (DQ1-DQ8) • Also produced with the numbers 2016 and 4116 • #S (select ) as Chip select • #G as Output Enable • #W as Write Enable • Range of speeds: access times in the range 120 ns to 250 ns (various chip versions,
e.g. TMS4016-25has 250 ns access time) • All can be interfaced with the 8088/8086 without wait states (ta< 420ns)
DYNAMIC RAM
TMS4464 DRAM 64 K x 4 DRAM ( 216 x 4) Charge of capacitor leaks with time, and data needs to be refreshed (re-written) every
say 2-4 ms So, DRAM always has address lines split into rows and columns. 16 address lines split into row and column as 8-bit parts.
Most Significant 8-bit row address is first latched in using the #RAS input (Row Address Select) (Diagram A)
Then 8-bit column address is latched in using the #CAS input (Column Address Select)
This loads the 16-bit address into a latch on the chip #CAS also acts as Chip select #G as output enable #W as write enable Access time: Fastest version is 100 ns.
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