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Project - Behavioral Model

Homework 2 - April 24, 2005

Jason Nemeth

I. IntroductionThe purpose of this assignment was toimplement a working mock-up of themicroprocessor using a behavioral VHDLmodel.

II. RequirementsThe microprocessor must have the

following capabilities:1.

Direct access to internalmemory with at least 256words.

2.

An instruction set capable ofexecuting at least thefollowing two benchmarks:

a.

Output 10 signed integers insorted (largest first) orderwhere the numbers areinput in random order.

b.

Output the mean (to thenearest integer) of 16signed integers read intothe processor.

3.

One 8-bit input port, and one 8-bit output port.

4.

Optional one single-bit Inputenable line, and one single-bit Output ready line

The overall layout of the

microprocessor is shown below inFigure 1. The behavioral modelwas created such that all thesecharacteristics were met. Themodel is capable of modeling bothprovided benchmarks.

Figure 1. Layout of the Microprocessor

III. Design DecisionsOpcodesThe first major design decision made wasregarding the opcodes required. Theaveraging and sorting operations havebeen implemented in psuedocode, andthe necessary operations have beenidentified. However, due to possibleoptimizations made prior to the

implementation of the structural model,the required opcodes may change. Sofar Add, Shift Right 4 bits, Move (fromone memory location to another), andJump (code execution) have beenidentified as necessary instructions. Asnoted, more may be needed asoptimizations increase.

ALU ImplementationThe ALU will be memory-mapped, and

one of its two inputs will be designated asdirectly mapped to the input port (location254 as noted in previous report). This willallow the addition operation to take placeas the numbers are entered. Then, onlya single clock-cycle will be required forthe shift operation before the result canbe presented on the output lines.

Output8

Input8

Microprocessor

Input Enable Output Ready

Clock

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Behavioral ModelThe behavioral model was developedwith the above requirements anddecisions in mind. The model makes anumber of assumptions regarding the

delay times of operations, and in generalassumes synchronous operation in allcases. The model accurately models anaverage and sort operation, producingthe output along the output lines andsetting the Output Ready bit highwhenever an operation completes.

Room for ImprovementSince memory can generally be written toin approximately 2 ns, and a clock cycle

may be closer to 30 ns, it may beadvantageous to asynchronously performmemory operations as it would greatlyincrease the speed of the sortingoperation, which requires three memorywrites per swap. This could provide asignificant improvement if it can beimplemented.

IV. ResultsThe results of the behavioral model are

what one would expect from a simplebehavioral system. The model producesthe correct averaged or sorted output inall tested cases. The model estimates anaveraging operation will takeapproximately two clock cycles on top of16 clock cycles taken to input the

numbers. The model also estimates asort operation will take approximately 128clock cycles on top of the 10 clock cyclesneeded in read in the numbers. Theresults are shown in Table 1, with the

values representing the number clockcycles beyond the data input. In thisbehavioral model the clock cycle was setto 30 ns, a speed derived from the speedof the adder created in Homework 1.This obviously leaves lots of room forimprovement, and shows that the mostcomplicated portion of this project will becoordinating how information flows intoand out of main memory.

Average Sort2.1 128.3

Table 1. The results of the behavioral simulation

V. ConclusionsThe results of the behavioral model willbe used to test for the proper operation ofthe structural and RTL models, as theywere in the first Homework of the quarter.As such, the behavioral model will remainuseful as a benchmark of the future

implementations. In addition to provingthe proper functionality of the system, themodel provides a pretty good indicationthat the majority of the work optimizingthe system needs to be directed atreducing the computation time of thesorting benchmark.