BD9528AMUV PCB Layout that Uses Only 1ch -...

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Switching Regulator Series

BD9528AMUV PCB Layout that Uses Only 1ch

This application note illustrates example of PCB layouts when only 1-ch is being used, for the 2-ch buck DC/DC controller IC

BD9528AMUV. It also explains the pin-connections for the unused functions and the PCB layout guidelines. All characteristics

have to be verified separately, and not guaranteed by the PCB layout shown here.

Setting Conditions

1. Electric characteristics:

VIN = 24V, VO1 = 3.3V, IO = 4A max, OCP = 6.0A、Switching frequency = 320kHz, VREG1 = 5V, VREG2 = 3.3V.

2. PCB specification:

Two-layers FR4, Minimum line width 0.15mm, Minimum gap 0.15mm, Minimum hole-diameter 0.3mm.

3. External switching transistor(s):

- In example-1 of PCB layout, use dual type N-ch MOSFET SH8K15 for the switching transistor.

- In example-2 of PCB layout, use dual type N-ch MOSFET RQ3E150GN and RQ3E180GN for the switching transistor.

Circuit Diagram

CONTROL MODE MCTL1 MCTL2

PWM fixed mode High High Low

SLLM mode (Light-load pulse skip）

Low Low

QLLM mode (Silent pulse skip)

Low High

No.13027EAY06

Figure 1. Circuit diagram

VIN

CTL

EN1

EN2

REG1

REG2

REF

SS1

FS1

BOOT1

HG1

SW1

LG1

PGND1

FB1

BOOT2

HG2

SW2

LG2

PGND2

VIN

C1

CTL

EN1

REG1 5V C2

C4

C5

Q2

Q1C7

VIN

C30 C9

30

9

21

4

29

28

12

19

6

15

22

23

24

26

25

14

3

2

1

31

32

BD9528AMUV

L1

R17

VO1 C14 C13

FS2 10

MCTL

AGND

FB2

PGOOD1

PGOOD2

PGOOD1

18

13

MCTL1

11

20

5

SS2

Vo1

Vo2

ILIM2 8

ILIM1 17

27

7

R5

R7

R18

MCTL2 MCTL16

Open

Open

Open

REG2 3.3V C3

Application Note



U1 IC - Buck DC/DC Converter BD9528AMUV ROHM VQFN032V5050

C1, C9 Ceramic Capacitor 10µF50V, X5R, ±10%35V, X5R, ±10%

GRM55DR61H106KA88GRM32ER6YA106KA12

MURATA57503225

C2, C13 Ceramic Capacitor 10µF 10V, X5R, ±10% GRM31CR61A106KA01 MURATA 3216

C3 Ceramic Capacitor 10µF 6.3V, X7R, ±10% GRM21BR70J106KE76 MURATA 2012

C4 Ceramic Capacitor 0.1µF 10V, X5R, ±10% GRM155R61A104KA01 MURATA 1005

C5 Ceramic Capacitor 2200pF 25V, X5R, ±10% GRM155R61E222KA07 MURATA 1005

C7 Ceramic Capacitor 0.47µF 10V, X5R, ±10% GRM188R61A474KA61 MURATA 1608

C14 POSCAP 220µF 6.3V, ±20%, ESR 25mΩmax 6TPE220MAP SANYO 7343

C30 Ceramic Capacitor 0.1µF 50V, X7R, ±10% GRM188R71H104KA93 MURATA 1608

L1 Inductor 6.8µH ±30%, 5.2A(L=-30%), DCR=27.6mΩ max 1217AS-H-6R8N (DEM8045C) TOKO 8080

Q1 MOSFET - N-ch, Vdss 30V, Id 15A, Ron 4.7mΩ RQ3E150GN ROHM 3333

Q2 MOSFET - N-ch, Vdss 30V, Id 18A, Ron 3.3mΩ RQ3E180GN ROHM 3333

R5, R7 Resistor 75kΩ 1/16W, 50V, 5% MCR01MZPJ753 ROHM 1005

R17 Resistor 56kΩ 1/16W, 50V, 1% MCR01MZPF5602 ROHM 1005

R18 Resistor 15kΩ 1/16W, 50V, 1% MCR01MZPF1502 ROHM 1005

ReferenceDesignator

ManufacturerPart Number

ManufacturerConfiguration

(mm)Type Value Description

Bill of Materials

Application Note



Example-1 of PCB Layout ・Dual type N-ch MOSFET SH8K15 is used for switching transistors Q1 and Q2.

・MCTL1 and MCTL2 pins are connected to the Low-Level, and set to SLLM (light-load pulse skip) mode.

Figure 2. Example-1 of PCB Layout Top Layer + Bottom Layer (Top View)

Application Note



Example-1 of PCB Layout (Continuation)

Figure 3. Example-1 of PCB Layout Top Layer (Top View)

Application Note




Figure 4. Example-1 of PCB Layout Bottom Layer (Top View)

Application Note



Example-2 of PCB Layout ・Dual type N-ch MOSFET RQ3E150GN and RQ3E180GN are used for switching transistors Q1 and Q2.

・MCTL1 and MCTL2 pins are connected to the Low-Level, and set to SLLM (light-load pulse skip) mode.

Figure 5. Example-2 of PCB Layout Top Layer + Bottom Layer (Top View)

Application Note




Figure 6. Example-2 of PCB Layout Top Layer (Top View)

Application Note




Figure 7. Example-2 of PCB Layout Bottom Layer (Top View)

Application Note



Notes for PCB Layout

1. Arrange input decoupling capacitor C30 on the same side as the switching transistors Q1 and Q2, and place it as near as

possible to the power supply and the ground terminal of the switching transistor(s). Try to shorten this distance even by 1mm. The

switching noise increases when input decoupling capacitor C30 is far away, or if arranged by the via-hole on the reverse side.

There is no problem when the decoupling capacitor C30 for high frequency is near the switching transistor(s), and even if the input

bulk capacitor C9 is somewhat away.

2. In order to minimize the radiation noise by the inductor L1 from the switching node, arrange it near to switching transistor(s)

Q1 and Q2, although it is not a requirement for input capacitor C30. Do not widen the copper pattern area more than it is needed.

3. Arrange output capacitors C13 and C14 near to inductor L1, and their ground to be separated from the ground of input

capacitors C9 and C30. A lot of high-frequency switching noises are included in the ground of the input capacitor, which can be

propagated to the output ground if they are near.

4. Wire the ground of switching transistor Q2 to the terminal pins PGND1 and PGND2 of the IC. Make sure not to cause the

potential difference between the two, due to voltage drop caused by the wiring.

5. Wire the ground of output capacitor C14 to the terminal pin AGND of the IC. Minimum influence by switching noise is made by

wiring to a clean ground.

Figure 8. Notes for PCB layout

1

2

3

3

4

5

7

8

Application Note



6. Wiring for the feedback path to IC is taken from the load side, and not to arrange it from output capacitor C14 side or in

parallel with the noise source of switching transistors Q1, Q2 and the inductor L1.

7. Connect the decoupling capacitor C1 to the VIN terminal of IC and is placed near to the IC terminal pin, and ground to PGND.

8. Connect the decoupling capacitors C2 and C3 to the VREG1 and VREG2 of the IC, and is placed near to the IC terminal pin,

and ground to AGND.

Figure 9. Notes for PCB layout (Continuation)

6

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