Basic Digital Electronics - Unit 3
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At the end of the lesson, students should be able to:
1. Describe the operation of the INVERTER, AND, OR, NAND and NOR gate.2. Describe the operation of exclusive-OR and exclusive-NOR gate.3. Recognize and use both the distinctive shape logic gate symbols and the
rectangular outline logic gate symbols of the ANSI/IEEE standard.
4. Construct timing diagrams showing the proper time relationship of inputs andoutputs for the various logic gates.
5. Make basic comparison between the two major IC technologies, TTL andCMOS.
6. Define propagation delay time, power dissipation, speed-power product, andfan out.
7. Troubleshoot logic gates for opens and shorts by using the test equipmentavailable in the lab.
3 LOGIC GATES
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InverterThe purpose of the inverter (NOT circuit) is to perform the operation called
inversionor complementation. The inverter changes one logic level to the opposite
level. In terms of bits, it changes a 1 to 0 and a 0 to 1.
Symbol
(a) Distinctive shape symbols (b) Rectangular outline symbol
Figure 3.1: Inverter symbols (ANSI/IEE Std.91-1984)
Truth Table
Table 3.1: Inverter truth table
Boolean Expression
INPUT
A
OUTPUT
AX
11
3.1 INVERTER, OR, NAND AND NOR GATE
1
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Inverter OperationWhen the input is LOW, the output is HIGH; when the input is HIGH, the
output is LOW, thereby producing an inverter output pulse.
Timing Diagram.i. Timing diagram is basically a graph that accurately displays the
relationship of two or more waveform with respect to each other on a time
basis.
ii. For example, the time relationship of the output pulse to the input pulse inFigure 3.2 can be shown with a simple timing diagram.
Figure 3.2: Timing diagram for the inverter.
Input A1
0
Output X1
0
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AND GateThe AND gate is one of the basic gate that can be combined to form any logic
function. An AND gate can have two or more inputs and performs what is know as
logical multiplication.
Symbol
(a) Distinctive shape symbols (b) Rectangular outline symbol
Figure 3.3: AND gate two input symbols (ANSI/IEE Std.91-1984)
Truth TableINPUTS OUTPUT
XA B
111 1 1
Table 3.2: truth table for 2-input AND gate
The total number of possible combinations of binary inputs to a gate is
determined by the following formula:
N =2n
Where N is the number of possible input combinations and nis the number of
input variables.
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Example 1:
Develop the truth table for a 3-input AND gate.
Solution;For 3 input variables: N = 23= 8 combinations
INPUTS OUTPUT
A B C X
111 1
11 11 11 1 1 1
Table 3.3
Boolean Expression
Operation of an AND gateFor a 2-input AND gate, output X is HIGH if inputs A and B are HIGH; X is
LOW if either A or B is LOW, or if both A and B are LOW.
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Timing Diagram
Figure 3.4: Example of pulsed AND gate operation with a timing diagram showing input
and output relationships.
OR GateThe OR gate is another of the basic gates from which all logic functions areconstructed. An OR gate can have two or more inputs and performs what is known
as logical addition.
Symbol
(a) Distinctive shape symbols (b) Rectangular outline symbol
Figure 3.5: OR gate two input symbols (ANSI/IEE Std.91-1984)
Input A 1
0
Input B1
0
Output X1
0
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Truth TableINPUTS OUTPUT
XA B
1 11 11 1 1
Table 3.4: Truth table for 2-input OR gate
Boolean Expression
Operation of an OR gateFor a 2 input OR gate, output X is HIGH if either input A or input B is
HIGH, or if both A and B are HIGH; X is LOW if both A and B are LOW.
Timing Diagram.For example, look at the operation of an OR gate with pulsed inputs. In
figure 2, input A and B are both HIGH during time interval t1, making the
output HIGH. During time interval t2, input A is LOW but because input B is
HIGH, the output is HIGH. Both inputs are LOW during time interval t3, so
there is a LOW output during this time. During time interval t4, the output
is HIGH because input A is HIGH.
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Figure 3.6: Example of pulsed OR gate operation with a timing diagram showing input and
output time relationships.
NAND GateThe NAND gate is a popular logic element because it can be used as a universal
gate; that is, NAND gates can be used in combination to perform the AND, OR and
inverter operations.
Symbol
(a) Distinctive shape symbols (b) Rectangular outline symbol
Figure 3.7: Standard NAND gate logic symbols (ANSI/IEEE Std. 91-1984)
Input A1
0
Input B1
0
Output X1
0
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Truth Table
Table 3.4: truth table for a 2-input NAND gate
Boolean Expression
Operation of a NAND gateFor a 2-input NAND gate, output X is LOW if inputs A and B are HIGH; X is
HIGH if either A and B is LOW, or if both A and B are LOW.
Timing Diagram.
Figure 3.8 : Timing diagram for NAND gate
INPUTS OUTPUT
XA B
11 1
1 11 1
Input A1
0
Input B1
0
Output X1
0
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NOR GateThe NOR gate, like the NAND gate is a useful logic element because it can also be
used as a universal gate; that is, NOR gates can be used in combination to perform
the AND, OR and inverter operations
Symbol
(a) Distinctive shape symbols (b) Rectangular outline symbol
Figure 3.9: Standard NOR gate logic symbols (ANSI/IEEE Std. 91-1984)
Truth Table
Table 3.5: Truth table for a 2-input NOR gate
Boolean Expression
INPUTS OUTPUT
XA B
11
11 1
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Operation of a NOR GateFor a 2-input NOR gate, output X is LOW if either input A or B is HIGH, or
if both A and B are HIGH; X is HIGH if both A and B are LOW.
Timing DiagramExample in Figure 3.10 illustrate the operation of a NOR gate with pulsed
inputs.
Figure 3.10 : Example of timing diagram
Input A
1
0
Input B1
0
Output X1
0
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Exclusive-ORExclusive-OR gate are formed by a combination of other gates. However, because
of their fundamental importance in many applications, this gate is often treated as
basic logic element with their own unique symbols.
SymbolThe XOR gate has only two inputs.
(a) Distinctive shape symbols (b) Rectangular outline symbol
Figure 3.11: Standard logic symbol for the exclusive-OR gate
Truth TableINPUTS OUTPUT
XA B
1 11 11 1
Table 3.6: Truth table for an exclusive-OR gate
3.2 EXCLUSIVE-OR AND EXCLUSIVE-NOR GATE
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Boolean ExpressionThe Boolean expression for the output of an exclusive-OR gate: -
Operation of a Exclusive-OR GateFor an exclusive-OR gate, output X is HIGH if input A is LOW and input B is
HIGH, or if input A is HIGH and input B is LOW; X is LOW if A and B are
both HIGH or both LOW.
Timing Diagram
Figure 3.12 : Example of timing diagram
Input A1
0
Input B1
0
Output X1
0
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Exclusive-NORExclusive-NOR gate are formed by a combination of other gates. However, because of
their fundamental importance in many applications, this gate is often treated as basic logic
element with their own unique symbols.
SymbolStandard symbol for an exclusive-NOR (XNOR for short) gate are shown in
figure 1. The XNOR gate has only two inputs.
(a) Distinctive shape symbols (b) Rectangular outline symbol
Figure 3.13: Standard logic symbol for the exclusive-NOR gate
Truth TableINPUTS OUTPUT
XA B
11
11 1 1
Table 3.7: Truth table for an exclusive-NOR gate.
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Boolean ExpressionThe Boolean expression for the output of a 2-input NAND gate is: -
Operation of a Exclusive-OR GateFor an exclusive-NOR gate, output X is LOW if input A is LOW and input B is
HIGH, or if input A is HIGH and input B is LOW; X is HIGH if A and B are
both HIGH or both LOW.
Timing DiagramThe example of the operation of XNOR gate under pulsed input conditions is
illustrated in Figure 3.14 below.
Figure 3.14 : Timing diagram
Input A1
0
Input B1
0
Output X1
0
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This sheet will explain to you technologies used to produce IC like CMOS and TTL. Alsoyou can identify series in CMOS and TTL and you can define what terms like propagation
delay time, power dissipation, fan out and speed power product.
Digital ICs are a collection of resistors, diodes and transistors fabricated on a single piece
of semiconductor material (usually silicon) called a substrate, which commonly referred to
as a chip. The chip is enclosed in a protective plastic or ceramic package from which pins
extend for connecting the IC to other devices. There are three digital integrated circuit
(IC) technologies that are used to implement the basic logic gates and they are CMOS,
TTL and ECL.
TTL (Transistor-transistor Logic)TTL is implemented with bipolar junction transistors. TTL has been and still a
popular digital IC technology. One disadvantage of TTL is that it is not sensitive to
electrostatic discharge as CMOS is and, therefore, is more practical in most
laboratory experimentation and prototyping because we do not have to worry about
handling precautions.
TTL series operate from a 5V dc supply. These series within the TTL family differ
in their performance characteristics and are designated by the prefix 74 or 54
followed by a letter or letters that indicate the series and a number that indicates
the type of logic device within the series. A TTL IC can be distinguished from
CMOS by the letters that follow the 74 or 54 prefix.
The basic TTL series and their designations are as follow: -
TTL Series Prefix
Standard TTL 74
Schottky TTL 74S
Low-power schottky TTL 74LS
Advanced schottky TTL 74AS
Advanced low-power schottky TTL 74ALS
Fast TTL 74F
3.3 IC TECHNOLOGIES (TTL and CMOS)
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CMOS (Complementary Metal-Oxide Semiconductor)CMOS stands for Complementary Metal-Oxide Semiconductor and is implemented
with a type of a field-effect transistor.
The two categories of CMOS in terms of the dc supply voltage are the 5V CMOS
and the 3.3V CMOS. Within each supply voltage category, several series of CMOS
logic gates are available. These series within the CMOS family differ in their
performance characteristics and are designated by the prefix 74 or 54 followed by
letter or letters that indicate the series and then a number that indicates the
type of logic device. The prefix 74 indicate commercial grade for general use, and
the prefix 54 indicates military grade for more severe environments.
The basic series for the 5V categoryand their designations are as follows: -
CMOS Series Prefix
High-speed CMOS 74HC and 74HCT
Advanced CMOS 74AC and 74ACT
Advanced High-speed CMOS 74AHC and 74AHCT
The basic CMOS series for the 3.3V categoryand their designation are as follows:
-
CMOS series PrefixLow-voltage CMOS 74LV
Low-voltage CMOS 74LVC
Advanced Low-voltage CMOS 74ALVC
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Propagation Delay TimeThis parameter is a result of the limitation on switching speed or frequency at
which a logic circuit can operate. The shorter the propagation delay, the higher the
speed of the circuit and the higher the frequency at which it can operate.
Propagation delay time, tp, of a logic gate is the time interval between the
application of an input pulse and the occurrence of the resulting output pulse. There
are two different measurements of propagation delay time associated with a logic
gate: -
i. tPLHdelay time in going from logical 0 to logical 1 state (LOW to HIGH)ii. tPHL delay time in going from logical 1 to logical 0 state (HIGH to LOW)
Figure 3.15 shows the example of propagation delay time for an inverter. The
propagation delay times, tPHL and tPLH, are indicated in part (b). In this case,
the delays are measured between 50% points of the corresponding edges of the
input an output pulses. The values of tPHLand tPLHare not necessarily equal but in
many cases they are the same.
Figure 3.15 : propagation delay time
3.4CHARACTERISTIC OF IC ( PROPAGATION DELAY TIME, POWER
DISSIPATION SPEED POWER PRODUCT, AND FAN OUT)
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Power DissipationPower dissipation, PD, a logic gate is the product of the dc supply voltage and the
average supply current. Normally, the supply current when the gate output is LOW
is greater than when the gate output is HIGH. Supply current for the LOW statedesignated as ICCL, and for the HIGH state designated as ICCH. The average supply
current is determined based on 50% duty cycle operation of the gate (output LOW
half time and HIGH half time).
Fan-OutThe fan-out of a logic gate is the maximum number of inputs of the same series in
an IC family that can be connected to a gates output and still maintain the outputvoltage levels within specified limits.
Figure 3.16 shows LS logic gates driving a number of other gates of the same
circuit technology, where the number of gates depends on the particular circuit
technology. For example the maximum number of gate inputs that a standard 74
series TTL can drive is 10. Most of the other TTL series, such as the LS can drive
20.
Figure 3.16: The LS TTL NAND gate output fans out to a maximum of
20 LS TTL gate inputs.
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Speed-Power ProductThis parameter can be used as a measure of the performance of a logic circuit
taking into account the propagation delay time and the power dissipation. It is
especially useful for comparing the various logic gate series within the CMOS orTTL family. The speed-power product of a logic circuit is the product of the
propagation delay time and the power dissipation and is expressed in joules (J),
which is the unit of energy.
Logic Probei. A device that uses LEDs to indicate the condition of the signal on the line.ii. A logic probe will show whether power is reaching a logic IC. It will also
indicate if there is any pulse activity on a particular line. It can be used to
check the operation of a logic gate. The LED is on for a logic 1 (High) and off
for a logic 0 (Low) level.
iii. A logic high state at a test point is usually indicated on a probe by an LEDlabeled HIGH lighting up.
iv. A logic low state at a test point is usually indicated on a probe by an LEDlabeled LOW lighting up.
v. A pulsing signal at a test point is usually indicated on a probe by an LEDlabeled PULSE slowly flashing on and off.
Figure 3.17: Logic Probe
3.5TROUBLESHOOT WITH LOGIC PROBE, LOGIC PULSE AND IC
TESTER
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Logic Pulseri. Similar to a digital signal generator. The pulser injects a pulse or series of
pulses into the circuit at point of contact.
ii. The logic probe is then used to trace this pulse or pulse train through thecircuit.
iii. When a fault occurs in a system, the troubleshooter will first try to identifythe functional unit that is faulty. A visual inspection of the circuits may
accomplish this. But, it usually dose not. A study of the systems logic circuit
diagram coupled with a complete analysis of the symptoms of the faults may
determine the fault unit. The logic circuit diagram will show you
All electrical connections All pin numbers All IC number Signal identifications Supply voltage level Each gate input and output Ground connections
iv. However, in most cases you will have to inject a signal into the system andtrace it through until it is lost. By using logic pulser to inject pulses and the
logic probe to check the output.
Figure 3.18: Logic Pulser
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Figure 3.19: Combination between Logic Probe and Logic Pulser
Troubleshooting short circuits in a logic circuit.Figure 3.20 below show a simple logic circuit with a short to ground. The effect is
to apply a permanent 0 V on the input to the gate. The output at C will be stuck at 0
V. If both A and B are at logic 1, the output C should be logic 1 also. Both X and Y
are normal. If Y or Z were stuck at 1, the other input would have an effect on the
output at B. The condition on B would be observed if either Y, Z, or B is shorted to
ground. Voltage measurements will isolate the fault to line B.
Figure 3.20 : A simple logic circuit
Short
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Troubleshooting Open circuits in a logic circuitsThe open in Figure 3.18 below show disables gate 2 from circuit operation. If Y and
Z are brought high (logic 1) and the output of gate 2 is found to be at logic 1, gate 2
is good. However, since the input to gate 3 on line B is stuck low, this means that
line B is open somewhere. Voltage measurements will locate the open point.
Figure 3.21 : Disables gate 2 from circuit operation
This figure shows the simple signal-tracing method applied to an AND gate. Note
that in some case, you must apply a 1 (+V) to some lines in order to enable the gate
and allow the pulse to pass. If you tie point B to +5V and inject pulse at point A, the
probe should detect the pulse at point C. If not the gate is bad.
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In this topic, we have learn about the operation of the basic logic gate like the INVERTER
or NOT, AND, OR, NAND and NOR gate. Student also should be understand about the
operation of the exclusive-OR gate and exclusive-NOR gate. Student should be able to
identify the shape of logic gate symbols according to the ANSI/IEEE (American National
Standard Institute/ International Electrical Electronic Engineering) standard 91 1984.
To understand more about digital signal input and output, student must be constructs
timing diagrams that showing the proper time relationships of inputs and outputs for the
various logic gates. Student also learned about the characteristic of ICCMOS(Complimentary Metal Oxide Semiconductor) and TTL(Transistor-Transistor Logic)
families to know the differ from each other in propagation delay time, power dissipation,
speed-power product and fan-out, They also learned how to troubleshoot the logic gates
for opens and shorts by using the oscilloscope.
1. Draw the rectangular outline symbol for an inverter.
2. A waveform is applied to an inverter in figure 2. Determine the output waveformcorresponding to the input and show the timing diagram.
Input
Output
SUMMARY
EXERCISE
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3. When is the output of an AND gate HIGH?______________________________________________________________
4. Describe the truth table for a 5-input AND gate.______________________________________________________________
5. When is the output of an OR gate HIGH?______________________________________________________________
6. When is the output of an OR gate LOW?______________________________________________________________
7. If two waveforms A and B are applied to the AND gate inputs as in Figure a Whatis the resulting output waveform?
Figure 3.22
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8. When is the output of an OR gate HIGH?______________________________________________________________
9. Describe the truth table for 3-input OR gate.______________________________________________________________
10.When is the output of an OR gate LOW?______________________________________________________________
11. Describe the truth table for 3-input OR gate.______________________________________________________________
12.If the two input waveforms A and B in Figure b are applied to the OR gate, what isthe resulting output waveform?
Figure 3.23
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13.When is the output of a NAND gate HIGH?______________________________________________________________
14.Write the output expression for a NAND gate with inputs A, B and C.______________________________________________________________
15.When is the output of a NOR gate LOW?______________________________________________________________
16.Write the output expression for a 3-input NOR gate with input variables A, B and C.
17.When is the output of an XOR gate HIGH?______________________________________________________________
18.How can you use an XOR gate to detect when two bits are different?______________________________________________________________
19.Write the Boolean expression of an exclusive-OR gate.______________________________________________________________
20.When is the output of an XNOR gate HIGH?______________________________________________________________
21.How can you use an XNOR gate to detect when two bits are same?______________________________________________________________
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1. Digital System Principle And Applications, Tocci, R.J, Prentice Hall international.2. Digital Fundamentals, Floyd T.L, Merrill Publishing.3. BPL(K) Module TFV 2033 Digital Electronics 1.4. Digital Electronics (Teaching Module), KUITHO.
REFERENCE