B. Alizadeh Advanced Logic Design (2008) 1 / 55 Decision Diagrams.

55
B. Alizadeh Advanced Logic Design (2008) 1 / 55 Decision Diagrams

Transcript of B. Alizadeh Advanced Logic Design (2008) 1 / 55 Decision Diagrams.

B. Alizadeh Advanced Logic Design (2008)

1 / 55

Decision Diagrams

B. Alizadeh Advanced Logic Design (2008)

2 / 55

Binary Decision Diagrams

Classical representation of logic functions: Truth Table, Karnaugh Maps, Sum- of- Products, critical complexes, etc.

• Critical drawbacks:- May not be a canonical form or is too large (exponential) for “useful” functions. Equivalence and tautology checking is hard- Operations like complementation may yield a representation of exponential size

B. Alizadeh Advanced Logic Design (2008)

3 / 55

Binary Decision Diagrams

Reduced Ordered Binary Decision Diagrams (ROBDDs)• A canonical form for Boolean functions• Often substantially more compact than traditional normal forms• Can be efficiently manipulated• Introduced mainly by R. E. Bryant (1986).• Various extensions exist that can be adapted to the situation at

hand (e. g., the type of circuit to be verified)

B. Alizadeh Advanced Logic Design (2008)

4 / 55

Binary Decision Trees

• A Binary decision Tree (BDT) is a rooted, directed graph with terminal and nonterminal vertices

• Each nonterminal vertex v is labeled by a variable var( v) and has two successors:

- low( v) corresponds to the case where the variable v is assigned 0

- high( v) corresponds to the case where the variable v is assigned 1

• Each terminal vertex v is labeled by value( v) {0, 1}

B. Alizadeh Advanced Logic Design (2008)

5 / 55

Binary Decision Trees

Example: BDT for a two- bit comparator, f( a1 ,a2 ,b1 ,b2 ) = (a1 b1 ) (a2 b2 )

B. Alizadeh Advanced Logic Design (2008)

6 / 55

Binary Decision Trees

We can decide if a truth assignment x = (x 1 , ..., x n ) satisfies a formula in BDT in linear time in the number of variables by traversing the tree from the root to a terminal vertex:

- If var( v) x is 0, the next vertex on the path is low( v) - If var( v) x is 1, the next vertex on the path is high( v) - If v is a terminal vertex then f( x ) = f v (x1 , ..., xn ) = value( v) - If v is a nonterminal vertex with var( v)= xi , then the structure of the tree is obtained

by Shanon’s expansionfv (x1 , ..., xn ) =

xi flow(v) (x 1 , ..., x n )] [xi fhigh(v) (x1 , ..., xn )]For the comparator, (a1 1, a2 0, b1 1, b2 1) leads to a terminal vertex labeled by 0, i. e., f( 1, 0, 1, 1) = 0Binary decision trees are redundant:

- In the comparator, there are 6 subtrees with roots labeled by b2 , but not all are distinctMerge isomorphic subtrees:

- Results in a directed acyclic graph (DAG), a binary decision diagram (BDD)

B. Alizadeh Advanced Logic Design (2008)

7 / 55

(Canonical Form Property)Reduced Ordered BDD

two Boolean functions are logically equivalent iff they have isomorphic representationsThis simplifies checking equivalence of two formulas and deciding if a formula is satisfiableTwo BDDs are isomorphic if there exists a correspondence between the graphs such that- Terminals are mapped to terminals and nonterminals are mapped to nonterminals- For every terminal vertex v there exists a terminal vertex v’ , value( v) = value( v’) , and- For every nonterminal vertex v there exists a terminal vertex v’ :var( v) = var( v’) , low( v) = low( v’) , and high(v) = high(v’)Bryant (1986) showed that BDDs are a canonical representation for Booleanfunctions under two restrictions:(1) the variables appear in the same order along each path from the root to a terminal(2) there are no isomorphic subtrees or redundant vertices

Reduced Ordered Binary Decision Diagrams (ROBDDs)

B. Alizadeh Advanced Logic Design (2008)

8 / 55

Canonical Form Property

Requirement (1): Apply total order “<” on the variables in the formula: if vertex u has a nonterminal successor v , then var( u) <

var( v)Requirement (2): repeatedly apply three transformation rules

1. Remove duplicate terminals: eliminate all but one terminal vertex with a given label and redirect all arcs to the eliminated vertices to the remaining one

B. Alizadeh Advanced Logic Design (2008)

9 / 55

Canonical Form Property

2. Remove duplicate nonterminals: if nonterminals u and v have var( u) = var( v) , low( u) = low( v) and high( u) = high( v) , eliminate one of the two vertices and redirect all incoming arcs to the other vertex

3. Remove redundant tests: if nonterminal vertex v has low( v) = high( v) ,

eliminate v and redirect all incoming arcs to low( v)

B. Alizadeh Advanced Logic Design (2008)

10 / 55

Canonical Form Property

A canonical form is obtained by applying the transformation rules until no further application is possibleApplications:

-checking equivalence : verify isomorphism between ROBDDs -non- satisfiability : verify if ROBDD has only one terminal node,

labeled by 0 -tautology : verify if ROBDD has only one terminal node, labeled by 1Example:

ROBDD of 2- bit Comparator with variable order a1 < b1 < a2 < b2 :

B. Alizadeh Advanced Logic Design (2008)

11 / 55

Variable Ordering Problem

The size of an ROBDD depends critically on the variable order

For order a 1 < a 2 < b 1 < b 2 , the comparator ROBDD becomes:

For an n- bit comparator:

a1 < b1 < ... < an < bn gives 3n + 2 vertices (linear complexity)

a1 < ... < an < b1 ... < bn , gives 3*2n 1 vertices (exponential complexity!)

B. Alizadeh Advanced Logic Design (2008)

12 / 55

Variable Ordering Problem

The problem of finding the optimal variable order is NP- completeSome Boolean functions have exponential size ROBDDs for any order (e. g., multiplier)Heuristics for Variable Ordering

Heuristics developed for finding a good variable order (if it exists)ROBDDs tend to be smaller when related variables are close together in the order (e. g., ripple- carry adder)Variables appearing in a subcircuit are related: they determine the subcircuit’s output should usually be close together in the order

Dynamic Variable OrderingUseful if no obvious static ordering heuristic appliesDuring verification operations (e. g., reachability analysis) functions change, hence initial order is not good laterGood ROBDD packages periodically internally reorder variables to reduce ROBDD sizeBasic approach based on neighboring variable exchange ... < a < b < ... ...< b < a < ...

B. Alizadeh Advanced Logic Design (2008)

13 / 55

Logic Operations on ROBDDs

Residual function (cofactor): b {0, 1}f (x1,..., xn ) |xi b = f( x1 , ..., xi-1 , b, xi+1 , ..., xn )ROBDD of f |xi b computed by a depth- first traversal of the ROBDD of f:(1) For any vertex v which has a pointer to a vertex w such that var( w) = xi , replace the pointer by low(w) if b is 0 and by high(w) if b is 1.(2) If not in canonical form, apply Reduce to obtain ROBDD of f |xi b.All 16 two- argument logic operations on Boolean function implemented efficiently on ROBDDs in linear time in the size of the argument ROBDDs.

B. Alizadeh Advanced Logic Design (2008)

14 / 55

Logic Operations on ROBDDs

Based on Shannon’s expansionf = [ x f |x ] [x f |x ]

Bryant (1986) gave a uniform algorithm, Apply, for computing all 16 operations:f * f’ : an arbitrary logic operation on Boolean functions f and f’v and v’: the roots of the ROBDDs for f and f’ , x = var( v) and x’ = var( v’)Consider several cases depending on v and v’(1) v and v’ are both terminal vertices: f * f’ = value( v) * value( v’)(2) x = x’ : use Shannon’s expansion

f * f’= [ x (f |x * f’ |x )] x (f |x * f’ |x )]to break the problem into two sub-problems, each is solved

recursivelyThe root is v with var( v) = x

Low( v) is (f| x 0 * f’| x 0 )High( v) is (f| x 1 * f’| x 1 )

B. Alizadeh Advanced Logic Design (2008)

15 / 55

Logic Operations on ROBDDs

(3) x < x’ : f’| x 0 = f’| x 1 = f’ since f’ does not depend on xIn this case the Shannon’s expansion simplifies tof * f’= [ x (f| x 0 * f’)] x (f | x 1 * f’)], similar to (2)and compute subproblems recursively,(4) x’ < x : similar to the case above

Improvement using the if- then- else (ITE) operator:ITE( F, G, H) = F . G + F’ . H where F, G and H are functions

Recursive algorithm based on the following, v is the top variable (lowest index):ITE( F, G, H) = v.( F. G + F’. H)v + v’.( F. G + F’. H)v’

= v.( Fv .Gv + F’v .Hv ) + v’.( Fv’ .Gv’ + F’v’ .Hv’ )= (v, ITE( Fv , Gv , Hv ), ITE( Fv’ , Gv’ , Hv’ ))With terminal cases being: F = ITE( 1, F, G) = ITE( 0, G, F) = ITE( F, 1, 0) ITE( G, F, F)

we define NOT( F) = ITE( F, 0, 1) AND( F, G) = ITE( F, G, 0) OR( F, G) = ITE( F, 1, G) XOR( F, G) = ITE( F, G, G) etc.

B. Alizadeh Advanced Logic Design (2008)

16 / 55

Logic Operations on ROBDDs

By using dynamic programming, it is possible to make the ITE algorithm polynomial:(1) The result must be reduced to ensure that it is in canonical form;- record constructed nodes ( unique table );- before creating a new node, check if it already exists in this unique hash table

Var Index(i)

Then(G)

Else(H)

... ... ...

HashFunction

..

Linked List

Linked List

Linked List

B. Alizadeh Advanced Logic Design (2008)

17 / 55

Logic Operations on ROBDDs

(2) Record all previously computed functions in a hash table ( computed table );- must be implemented efficiently as it may grow very quickly in size;- before computing any function, check table for solution already obtained

Var Index(i)

Then(G)

Else(H)

... ... ...

HashFunction

Result

...

B. Alizadeh Advanced Logic Design (2008)

18 / 55

Logic Operations on ROBDDs

Return Build’ (t,1)  function Build’ (t,i) if i n then

if t is false then return 0 else return 1 else

Build’ (t[0/ ], i+1) Build’ (t[1/ ], i+1)return MK(i , , )

end Build’

 

MK[T, H](i, l, h) if l = h then return l else if member(H, i, l, h)

thenreturn lookup(H, i, l, h)

elseu add(T,i,l,h)insert(H, i, l, h, u)return u

unique Table

ix

ix0v

0v

1v

1v

B. Alizadeh Advanced Logic Design (2008)

19 / 55

Example

BUILD( (x1+x2)x3 , 1)

( (0+x2)x3 , 2) ( (1+x2)x3 , 2)

( (0+0)x3 , 3) ( (0+1)x3 , 3) ( (1+0)x3 , 3) ( (1+1)x3 , 3)

( (0+0)0 , 4)

( (0+0)1 , 4)

( (0+1)0 , 4)

( (0+1)1 , 4)

( (1+0)0 , 4)

( (1+0)1 , 4)

( (1+1)0 , 4)

( (1+1)1 , 4)

F = (x1 + x2) x3

B. Alizadeh Advanced Logic Design (2008)

20 / 55Example

u Var Low High

0 4

1 4

2 3 0 1

3 2 0 2

4 1 3 2

T: u (i,l,h)

Var Low High u

3 0 1 2

2 0 2 3

1 3 2 4

H: (i,l,h) u MK[T, H](i, l, h) if l = h then return l else if member(H, i, l, h) then

return lookup(H, i, l, h) else

u add(T,i,l,h)insert(H, i, l, h, u)return u

Return Build’ (t,1)  function Build’ (t,i) if i n then

if t is false then return 0 else return 1 else

Build’ (t[0/ ], i+1) Build’ (t[1/ ], i+1)return MK(i , , )

end Build’

ix

ix0v

0v1v

1v

B. Alizadeh Advanced Logic Design (2008)

21 / 55

Example

u Var Low High

0 4

1 4

2 3 0 1

3 2 0 2

4 1 3 2

T: u (i,l,h)

B. Alizadeh Advanced Logic Design (2008)

22 / 55Operations on ROBDD

Construct the ROBDD resulting from applying op on u1 and u2Apply[T,H](op,u1,u2) init(G) //Computed Table return APP(u1,u2)function APP(u1,u2) = if G(u1,u2) empty then return G(u1,u2) else if u1 {0,1} and u2 {0,1} then u op(u1,u2) else if var(u1) = var(u2) then

u MK( var(u1) , APP( low(u1) , low(u2) ) , APP( high(u1) , high(u2) ) )

else if var(u1) var(u2) thenu MK( var(u1) , APP( low(u1) , u2 ) , APP( high(u1) , u2 ) )

else //var(u1) var(u2)u MK( var(u2) , APP( u1 , low(u2) ) , APP( u1 , high(u2) ) )

G(u1,u2) u return uend APP

B. Alizadeh Advanced Logic Design (2008)

23 / 55Example of Apply

Compute AND of two ROBDDs

1x

2x

3x

4x

5

1

2

4 3

05x

4

3

2

01

4,5

4,3

0,0 0,1

4,4

3,2

2,2 1,2

1,0 0,1 1,0 1,1

3,2

B. Alizadeh Advanced Logic Design (2008)

24 / 55Example of Apply

4 4

4 will bereturned

(2,0,3) isfound in H

0&0 will beadded to G

0 3

(2,0,3) willbe added to

T & H

0 3

(3,0,2) willbe added to

T & H0 2

0 will bereturned up

0 0

(4,0,1) willbe added to

T & H

0 1

1&0 isfound in G

3,2 is foundin G

1&0 will beadded to G

0&1 will beadded to G

1&1 will beadded to G

0&1 isfound in G

B. Alizadeh Advanced Logic Design (2008)

25 / 55Example of Apply

u Var Low High

0 5

1 5

2 4 0 1

3 3 0 2

4 2 0 3

T: u (i,l,h)

Var Low High u

4 0 1 2

3 0 2 3

2 0 3 4

H: (i,l,h) u

u1 u2 APP(u1,u2)

0 0 0

1 0 0

0 1 0

2 2 0

1 1 1

1 2 2

3 2 3

4 4 4

4 5 4

G(u1,u2) APP(u1,u2)

B. Alizadeh Advanced Logic Design (2008)

26 / 55Example of Apply

u Var Low High

0 5

1 5

2 4 0 1

3 3 0 2

4 2 0 3

T: u (i,l,h)

1x

2x

3x

4x

1

3

4

2

0

B. Alizadeh Advanced Logic Design (2008)

27 / 55Operations on ROBDD

Restrict the ROBDD u according to the truth assignment [b/xj]

RESTRICT[T,H](u,j,b) return res(u)function res(u) = if var(u) j then return u else if var(u) j then return

MK( var(u), res( low(u) ), res( high(u) ) ) else ( * var(u) = j * ) if b = 0 then return

res( low(u) ) else ( * var(u) = j, b = 1 * ) return

res( high(u) )end res

B. Alizadeh Advanced Logic Design (2008)

28 / 55

Example of RESTRICT

F = (x1 x2) + x3 x2=0 => j=2; b=0

u Var Low High

0 4

1 4

2 3 0 1

3 2 2 1

4 2 1 2

5 1 3 4

T: u (i,l,h)

Var Low High u

3 0 1 2

2 2 1 3

2 1 2 4

1 3 4 5

H: (i,l,h) u

B. Alizadeh Advanced Logic Design (2008)

29 / 55

Example of RESTRICT

1x

2x

3x

4x

5

1

2

3 4

0

Before applying RESTRICT algorithm

B. Alizadeh Advanced Logic Design (2008)

30 / 55

Example of RESTRICT

Reconstruction phase

1x

2x

3x

4x

1

1

2

2

0

(1,2,1)will beadded to T & H

1

2

0

6 1x

2x

3x

B. Alizadeh Advanced Logic Design (2008)

31 / 55Example of RESTRICT

u Var Low High

0 4

1 4

2 3 0 1

3 2 2 1

4 2 1 2

5 1 3 4

6 1 2 1

T: u (i,l,h)

Var Low High u

3 0 1 2

2 2 1 3

2 1 2 4

1 3 4 5

1 2 1 6

H: (i,l,h) u

B. Alizadeh Advanced Logic Design (2008)

32 / 55Operations on ROBDD

SatCount[T](u): Return number of valid truth assignments of u

SatCount[T](u) return 2var(u)-1 * count(u)function count(u) = if u=0 then res 0 else if u=1 then res 1else

res 2var(low(u))-var(u)-1 * count(low(u)) + 2var(high(u))-var(u)-1 * count(high(u))

Return resend count

B. Alizadeh Advanced Logic Design (2008)

33 / 55Operations on ROBDD

AnySat(u): Return a satisfying truth assignment for u

AnySat(u)if u=0 then Error

else if u=1 then []else if low(u)=0 then return [xvar(u) 1, AnySat(high(u))]else return [xvar(u) 0, AnySat(low(u))]

B. Alizadeh Advanced Logic Design (2008)

34 / 55Operations on ROBDD

AllSat(u): Return all satisfying truth assignment for u

AllSat(u)if u=0 then <>

else if u=1 then <[]>else return

<add [xvar(u) 0] in front of all truth-assignment in AllSat(low(u)),

add [xvar(u) 1] in front of all truth-assignment in

AllSat(high(u))>

B. Alizadeh Advanced Logic Design (2008)

35 / 55

Derived Operations

Compose: Given F(x) and G(y), return F(G(y))

))(())(())((

)()()(

xx

xx

FyGFyGyGF

FxFxxF

Compose is reduced to two operations Restrict and three operations Apply

B. Alizadeh Advanced Logic Design (2008)

36 / 55

Derived Operations

QuantificationsGiven a function F(x1, x2, x3)

Existential Quantification x1:F(x1, x2, x3) = F(0, x2, x3) OR F(1, x2, x3)

Universal Quantification x1:F(x1, x2, x3) = F(0, x2, x3) AND F(1, x2, x3)

Unique Quantification !x1:F(x1, x2, x3) = F(0, x2, x3) XOR F(1, x2, x3)

B. Alizadeh Advanced Logic Design (2008)

37 / 55

Logic Operations on ROBDDs

Complement edges can reduce the size of an ROBDD by a factor of 2- Only one terminal node is labeled 1- Edges have an attribute (dot) to indicate if they are inverting or not- To maintain canonicity, a dot can appear only on low( v) edges- Complementation achieved in O( 1) time by placing a dot on the function edge- F and F’ can share entry in computed table- Adaptation of ITE easy

B. Alizadeh Advanced Logic Design (2008)

38 / 55

Variable Ordering

1. Window Permutation Algorithm Example: window size k = 3; Starting point x2 k!-1 total variable exchange; k(k-1)/2 exchanging to go to best

position

x1,x2,x3,x4,x5,x6,x7 initialx1,x3,x2,x4,x5,x6,x7

swap(x2,x3)x1,x3,x4,x2,x5,x6,x7

swap(x2,x4)x1,x4,x3,x2,x5,x6,x7

swap(x3,x4)x1,x4,x2,x3,x5,x6,x7

swap(x3,x2)x1,x2,x4,x3,x5,x6,x7

swap(x4,x2)

x1,x2,x3,x4,x5,x6,x7

swap(x4,x3)x1,x3,x2,x4,x5,x6,x7

swap(x2,x3)x1,x3,x4,x2,x5,x6,x7

swap(x2,x4)

B. Alizadeh Advanced Logic Design (2008)

39 / 55

Variable Ordering

2. Sifting AlgorithmStarting point x4

x1,x2,x3,x4,x5,x6,x7 initialx1,x2,x3,x5,x4,x6,x7

swap(x4,x5)

x1,x2,x3,x5,x6,x4,x7

swap(x4,x6)

x1,x2,x3,x5,x6,x7,x4

swap(x4,x7)x1,x2,x3,x5,x6,x4,x7

swap(x7,x4)x1,x2,x3,x5,x4,x6,x7

swap(x6,x4)

x1,x2,x3,x4,x5,x6,x7

swap(x5,x4)

x1,x2,x4,x3,x5,x6,x7

swap(x3,x4)

x1,x4,x2,x3,x5,x6,x7

swap(x2,x4)

x4,x1,x2,x3,x5,x6,x7

swap(x1,x4)

x1,x4,x2,x3,x5,x6,x7

swap(x4,x1)x1,x2,x4,x3,x5,x6,x7

swap(x4,x2)x1,x2,x3,x4,x5,x6,x7

swap(x4,x3)x1,x2,x3,x5,x4,x6,x7

swap(x4,x5)x1,x2,x3,x5,x6,x4,x7

swap(x4,x6)x1,x2,x3,x5,x6,x7,x4

swap(x4,x7)

B. Alizadeh Advanced Logic Design (2008)

40 / 55

Variable Ordering

3. Group Sifting Algorithmis an extension of sifting. It moves a group of variables at the time, instead of a single variable.

Symmetric variables A boolean function f(x1,x2,…,xn) is symmetric in xi and xj if the interchange of xi and xj leaves the function identically the same.Once two variables are identified as symmetric, they are “locked” together. This effectively leads to an algorithm that sifts groups of variables of varying size.

B. Alizadeh Advanced Logic Design (2008)

41 / 55Variable Ordering

4. Relative Absolute Position (RAP) In each iteration do Sifting and Symmetry checking (Window

Permutation)1. At each iteration, a variable that has not been sifted yet is chosen2. In each Sifting, Check it against its neighbor for symmetry 3. If symmetry is found, a group is formed and the relative position is fixed

References:1. “Who Are the Variables in Your Neighborhood”, Fabio

Somenzi2. “Dynamic Variable Ordering for Ordered Binary

Decision Diagrams”, Richard Rudell

B. Alizadeh Advanced Logic Design (2008)

42 / 55

References

1. H.R. Andersen, “An Introduction to Binary Decision Diagrams”, Lecture notes 1997. Web: http://www.it.dtu.dk/~hra

2. T. Kropf, “Introduction To Formal Verification”, Springer 1999. 3. K.S. Brace, R.L. Rudell and R.E. Bryant, “Efficient

Implementation of a BDD Package”, 27th ACM/IEEE Design Automation Conference 1990, pp. 40.

4. E. M. Clarke, O. Grumberg and D.A. Peled, “Model Checking”, 1999 E.M. Clarke, O. Grumberg and Lucent Technologies.

5. http://vlsi.colorado.edu/~fabio/CUDD/

B. Alizadeh Advanced Logic Design (2008)

43 / 55

BDDs and their applications

B. Alizadeh Advanced Logic Design (2008)

44 / 55

Overview

BDD-based representation of functions, functions with dcs, relations, minterms, cubes, sets, sets of sets, state machines, partitions, set systems, graphs, covering tables, matrices - what else?:)

Common features of all successful BDD-based representations

Detailed discussion of project possibilities Selecting representation for your problem

B. Alizadeh Advanced Logic Design (2008)

45 / 55

Relations

Relation is a mapping Bn Bm, where B = {0,1}, n > 0, m > 0.

If m = 1, a relation is a function For example, F( x1,x2, y1,y2,y3 ), n = 2, m = 3

x1 x2 y1 y2 y3

0 0 1 - 0

0 1 0 1 -

1 0 1 1 0

1 1 0 1 -

B. Alizadeh Advanced Logic Design (2008)

46 / 55Relations Are Reducible to Functions

Relation over variables (x1,x2,…,xn) and (y1,y2,…,ym) can be represented as a boolean function, which is 1 for a given minterm iff this minterm represents related assignments of variables (x1,x2,…,xn) and (y1,y2,…,ym).

B. Alizadeh Advanced Logic Design (2008)

47 / 55Example

1

1

0

0

0

0

0

0

y1

1111

1011

1101

0001

1110

1010

1100

0000

y2x3x2x1x1

x2

x3

y1

y2

This is a relation with n = 3, m = 2

B. Alizadeh Advanced Logic Design (2008)

48 / 55

Example (continued)

111111

1

1

0

1

1

1

0

y2

1

0

0

0

0

0

0

y1

0

1011

1101

1001

1110

1010

1100

1000

Fx3x2x1

other

x1

x2

x3

y1

y2

0 1

B. Alizadeh Advanced Logic Design (2008)

49 / 55Minterms and Cubes

Given a function F(x1,x2,…,xn), a product of all its variables in arbitrary polarities is a minterm

A product of its variables, which does not necessarily include all variables, is a cube

Each minterm is a cube; the reverse is not true

B. Alizadeh Advanced Logic Design (2008)

50 / 55Implicit Cube Representation

To represent cubes of n-variable function F(x1,x2,…,xn), two sets of n vars are used: signature variables S = (s1,s2,...,sn) and polarity variables P = (p1,p2,...,pn)

si variable is true iff i-th variable is present in the cube; pi variable is true iff i-th variable enters this cube in positive polarity

For example, cube x2x3’x4 is represented by the pair [(0111), (1101)]

B. Alizadeh Advanced Logic Design (2008)

51 / 55

Characteristic Function of a Set

Function F: Bn B, B = {0,1}, defines a subset of minterms of Bn, on which it is 1.

Given a binary encoding of a set of elements, characteristic function of a subset of this set is a boolean function, which is 1 for minterms encoding the subset and 0 for other minterms.

B. Alizadeh Advanced Logic Design (2008)

52 / 55

Example

Problem: Given the set {p0, p1, p2, p3, p4, p5 } and its encoding:

p0 – p2 – p4 – p1 – p3 – p5 – find characteristic function of subset {p0, p2, p3}

and represent the subset using BDD Solution: Define a function over the encoding

variables (x0,x1,x2) such that it is equal to 1 for minterms representing subset {p0, p2, p3}.

{p0, p2, p3}(x0,x1,x2)= + +

012 xxx012 xxx012 xxx

012 xxx012 xxx012 xxx

012 xxx012 xxx 012 xxx

B. Alizadeh Advanced Logic Design (2008)

53 / 55BDD Representation of the Characteristic Function

x2

x0

x1

10

012 xxx

012 xxx

012 xxx

F =

+

+

B. Alizadeh Advanced Logic Design (2008)

54 / 55

FSMs: Transition Relation

FSM is { I, O, S, , ) (r inputs, m states, n outputs) Transition relation is a boolean

function T: Br x Bm x Bm B, B={0,1} such that T( i, x, y) = 1 iff state y

can be reached in one transition from state x when input i is applied

B. Alizadeh Advanced Logic Design (2008)

55 / 55FSMs: Output Relation

Output relation is a boolean function

O: Br x Bm x Bn B such that O( i, x, o) = 1 iff output

o can be produced when the FSM is in state x and input i is applied