AXI リファレンスガイド (UG761) - ザイリンクス - All …€ŽABMA AXI4-Stream...

[Guide Subtitle] ( )

UG761 (v13.2) 2011 7 6 ( )

AXI

UG761 (v13.2) 2011 7 6

AXI japan.xilinx.com UG761 (v13.2) 2011 7 6

Xilinx is providing this product documentation, hereinafter Information, to you AS IS with no warranty of any kind, expressor implied. Xilinx makes no representation that the Information, or any particular implementation thereof, is free from any claimsof infringement. You are responsible for obtaining any rights you may require for any implementation based on the Information.All specifications are subject to change without notice. XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THEINFORMATION OR ANY IMPLEMENTATION BASED THEREON, INCLUDING BUT NOT LIMITED TO ANYWARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OFINFRINGEMENT AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULARPURPOSE. Except as stated herein, none of the Information may be copied, reproduced, distributed, republished, downloaded, displayed,posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying,recording, or otherwise, without the prior written consent of Xilinx. 2011 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarksof Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.ARM and AMBA are registered trademarks of ARM in the EU and other countries. All other trademarks are the property oftheir respective owners. (v13.2)

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2010/09/21 1.0 12.42011/03/01 2.0 2 13.1

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A ARESETN 2011/03/07 3.0 2011/07/06 4.0 13.2

AXI IP

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AXI japan.xilinx.com 1UG761 (v13.2) 2011 7 6

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1 : AXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5AXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

AXI4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6AXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9AXI4-Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9AXI4-Stream . . . . . . . . . . . . . . . . . . . . . . . . . .9

AXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2 : IP AXI AXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

: Embedded Edition System Edition . . . . . . . . . . . . . . . . . . .11AXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11AXI IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 : XPS ChipScope . . . . . . . . . . . . . . . .12

Project Navigator IP . . . . . . . . . . . . .12System Generator : DSP Edition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

System Generator AXI4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 AXI IP : Logic Edition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

AXI IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 AXI IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

AXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17AXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21AXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21AXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

AXI . . . . . . . . . . . . . . . . . . . . . . . . . . . .29AXI-To-AXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29AXI-To-AXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Centralized DMA ( DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33AXI DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34AXI DMA . . . . . . . . . . . . . . . . . . . . . . . . . . .34 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 DMA AXI4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

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DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35AXI4 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37DMA AXI4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

DMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39AXI VDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40VDMA AXI4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

IP . . . . . . . . . . . . . . . . . . . . . . .41Virtex-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42Spartan-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

3 : FPGA AXI IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45AXI4-Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

AXI4-Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47AXI4-Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55TLAST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

DSP IP AXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4 : AXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

IP AXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59AXI-To-PLB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60AXI4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60PLBv4.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61AXI-To-PLBv4.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Local-Link AXI4-Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Local-Link AXI4-Stream . . . . . . . . . . . . . . . . . . . . . . . . . .62

Local-Link AXI4-Stream . . . . . . . . . . . . . . . .64Local-Link IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65Local-Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

IP System Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65System Generator for DSP IP AXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65TDATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

System Generator PLBv4.6 . . . . . . . . . . . . . . . . . . . . . . . .67FSL ( ) AXI4-Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

FSL AXI4-Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 FSL AXI4-Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

DSP IP AXI4-Stream HDL . . . . . . . . . . . . . . . . . . . . . . . . . 69 DSP IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70IP CORE Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71



AXI4-Stream . . . . . . . . . . . . . . . . . . . .71AXI () . . . . . . . . . . . . . 72 . . . . . . . . . . . . . 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

5 : AXI AXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

/ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 /Fmax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

/ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

AXI4 : AXI4 . . . . . . . . . . . . 85AXI4 MPMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85AXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86AXI4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87AXI . . . . . . . . . . . . . . . . . . . . . . . . . .88AXI MPMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90AXI MPMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

AXI . . . . . . . . . . . . . . . . . . . . . . .91 AXI IP . . . . . . . . . . . . .91

AXI ChipScope AXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92Cadence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 . . . . . .92

AXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94AXI . . . . . . . . . . . . .94 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 . . . . . . . . . . . . . . .96

A : AXI AXI4 AXI4-Lite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97AXI4 AXI4-Lite . . . . . . . . . . . . . . . . . . . . . . . . . . . .98AXI4 AXI4-Lite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99AXI4 AXI4-Lite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100AXI4 AXI4-Lite . . . . . . . . . . . . . . . . . . . . . . . . . . .100AXI4 AXI4-Lite . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102

AXI4-Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

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3. [Contents] [AMBA] [AMBA Specifications] [AMBA4]

4. ABMA AXI4-Stream Protocol Specification ABMA AXI Protocol Specificationv2.0

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1-1 : AXI4 IP(1)

AXI4 /

PLBv3.4/v4.6

OPB

NPI

XCL

AXI4-Lite /

PLBv4.6 () DCR

DRP

AXI4-Stream Local-Link

DSP

TRN (PCIe ) FSL

1. 4 AXI

http://japan.xilinx.comhttp://japan.xilinx.com/products/targeted_design_platforms.htmhttp://japan.xilinx.com/products/targeted_design_platforms.htm


2

IP AXI

AXI AXI IP (Xilinx Platform Studio System Generator for DSP ) AXI IP (CORE Generator )

: Embedded Edition System Edition ISE Design Suite : Embedded Edition System Edition AXI

AXI (EDK) AXI IP (pcore)

Base System Builder (BSB) AXI PLBv.46 Xilinx Platform Studio (XPS) ISE Design Suite BSB XPS

Xilinx Platform Studio (XPS) (AXI ) IP

(SDK) SDK Eclipse AXI XML SDK (XPS ) SDK

EDK http://japan.xilinx.com/support/documentation/dt_edk.htm

http://japan.xilinx.comhttp://www.xilinx.com/cgi-bin/SW_Docs_Redirect/sw_docs_redirect?locale=en&ver=13.2&topic=sw+manuals&sub=index.htmlhttp://www.xilinx.com/cgi-bin/SW_Docs_Redirect/sw_docs_redirect?locale=en&ver=13.2&topic=sw+manuals&sub=index.htmlhttp://www.xilinx.com/cgi-bin/SW_Docs_Redirect/sw_docs_redirect?locale=en&ver=13.2&topic=sw+manuals&sub=index.htmlhttp://japan.xilinx.com/support/documentation/dt_edk.htmhttp://japan.xilinx.com/support/documentation/dt_edk.htm


2 : IP AXI

AXI IP XPS Platform Studio IP IP Create andImport Peripheral (CIP) Wizard

: XPS ChipScope ChipScope Pro Analyzer AXI (chipscope_axi_monitor) AXI4 AXI4-Lite AXI / XPS

AXI AXI MicroBlaze

100MHz 50MHz

chipscope_axi_monitor IP /debug XPS

1. System Assembly View (SAV) chipscope_axi_monitor

2. [Bus Name]

AXI IP M

3. ChipScope ICON AXI 4. [SAV Ports] MON_AXI_ACLK

AXI

MON_AXI_TRIG_OUT chipscope_axi_monitor

Project Navigator IP EDK IP DDR3 AXI EDK IP XPS 37856

http://japan.xilinx.comhttp://www.xilinx.com/support/answers/37856.htm


AXI

System Generator : DSP Edition System Generator for DSP AXI4 AXI4-Stream

AXI4 EDK

AXI4-Stream System Generator AXI4 IP

System Generator AXI4 System Generator EDK AXI4( )

EDK System Generator MicroBlaze PLBv4.6 AXI4

System Generator AXI4 EDK

FIFO EDK

2-1 [EDK Processor] [Implementation] AXI4


2-1 : [EDK Processor] [Implementation]



2 : IP AXI

System Generator AXI4-Stream AXI4-Stream [Display shortened port names]

System Generator AXI4-Stream

data_tready 2 data_tvalid data_tdata AXI4-Stream phase_treadyphase_tvalidphase_tdata AXI4-Stream 2-2 rst

TDATA AXI4-Stream TDATA SystemGenerator TDATA 2-3 dout TDATA


2-2 :



AXI


: TDATA

System Generator AXI IP http://japan.xilinx.com/tools/sysgen.htm

AXI IP : Logic Edition AXI4 IP CORE Generator Project NavigatorPlanAhead IP IP [AXI4] AXI4 IP IP AXI4 AXI4-StreamAXI4-Lite

Virtex-6 Spartan-6 AXI4 IP Production IP Virtex-6 Spartan-6 Virtex-5 Virtex-4 Spartan-3 IP IP Production 2-4 CORE Generator IP

2-3 : TDATA

http://japan.xilinx.comhttp:/japan.xilinx.com/tools/sysgen.htmhttp:/japan.xilinx.com/tools/sysgen.htm


2 : IP AXI

16 2-5 PlanAhead [AXI4] IP AXI4


2-4 : IP


2-5 : PlanAhead IP



AXI IP

AXI IP IP AXI AXI IP

Virtex-6 Spartan-6 IP

AXI IP

AXI

Centralized DMA ( DMA)

DMA

DMA

IP

4 AXI AXI IP http://japan.xilinx.com/ipcenter/axi4.htm

AXI IPAXI IP (axi_interconnect) 1 AXI 1 AXI ARM AMBA AXI 4 AXI4-Lite

: AXI IP AXI4-Stream AXI4-Stream IP IP DMA IP

AXI IP (EDK) Project Navigator () pcore CORE Generator

AXI_Interconnect IP (DS768)

AXI AXI IP

AXI (AXI3 AXI4 AXI4-Lite)

256 (INCR) AXI3 16 AXI4

REGION

USER USER ( )

(QoS) AXI ( )

http://japan.xilinx.comhttp://japan.xilinx.com/ipcenter/axi4.htmhttp://japan.xilinx.com/support/documentation/ip_documentation/axi_interconnect/v1_03_a/j_ds768_axi_interconnect.pdf


2 : IP AXI

AXI4 : 32 64 128 256 512 1024

AXI4-Lite : 32

32

(SI) 1 16 SI 16 (MI) 1 16 MI 16

1 16 1 16

1 1 AXI

1 1 AXI

: CORE Generator AXI 1

(32 64 128 256512 1024 )

- 32 64 128 256 512 1024

-

() () ( ) (CACHE )

()

(N:1 1:N)

( )

AXI SI MI

AXI4-Lite

AXI AXI4/AXI4-Lite /



AXI IP

AXI AXI4-Lite ID

- AXI4-Lite ID

AXI AXI4 AXI4-Lite

AXI4-Lite

AXI4-Lite 1

AXI3

AXI3 AXI AXI4 16 16

( )

AXI

AXI 1

FIFO ( )

32 LUT-RAM

512 RAM

(SAMD : Shared-Address, Multiple-Data)

- AXI

-

- 1 3

(SASD) ( )

- 1

- 1 Outstanding

-

Multiple Outstanding ()

(ID )



2 : IP AXI

16 ID ()

( ) 1 ID 1

ID 1 Outstanding

16

( 0 )

SI MI MI

SI

TrustZone

- AXI

- AXI DECERR

/



AXI IP

AXI AXI AXI3

AXI4

MI AXI4

AXI3 1

AXI4 QoS QoS SI MI

AXI AXI4-Lite

AXI AXI C-

AXI AXI AXI AXI

AXI

AXI APB AXI

AXI (ACLKEN) AXI ACLKEN

: AXI4-Stream ACLKEN

AXI 2-6 AXI


2-6 : AXI

AXI Interconnect

SlaveInterface

MasterInterface

SI Hemisphere MI Hemisphere

Crossbar

Master 0 Slave 0

Slave 1Master 1 Reg

iste

r S

lices

Reg

iste

r S

lices

Up-

size

rs

Up-

size

rs

Clo

ck C

onve

rter

s

Dow

n-si

zers

Dat

a F

IFO

s

Clo

ck C

onve

rter

s

Dow

n-si

zers

Pro

toco

l Con

vert

ers

Dat

a F

IFO

s

X12047



2 : IP AXI

AXI SI MI AXI SI MI SI MI AXI

AXI SI (SI ) MI (MI ) AXI 2

AXI

AXI AXI IP 1 AXI 1

N 1

1 N

N M ( )

N M ( )

AXI 1

2-7 ARESET_OUT_N AXI INTERCONNECT_ARESETN


2-7 : AXI

Master 0 Slave 0

Interconnect



AXI IP

AXI 1 1

AXI4-Lite

AXI-3

FIFO

AXI

2-8 1 1

N 1 AXI 1

AXI ()

24 2-9 N 1 AXI


2-8 : AXI 1 1

X12049

Master 0 Slave 0

Interconnect

Conversionand/or

Pipelining



2 : IP AXI

.

1 N 1 AXI 1 2-10 1 N

N M ( ) N M AXI SAMD () 25 2-11


2-9 : N 1 AXI


2-10 : AXI 1 N

X12050

Master 0

Master 1

Slave 0

Interconnect

Arb

iter

X12051

Master 0

Slave 0

Slave 1

Interconnect

Dec

oder

/Rou

ter



AXI IP

2-12

SI ( AXI ) MI ( AXI ) AXI


2-11 : X12052

Master 0

Master 1

Master 2

Slave 0

Slave 1

Slave 2

Interconnect

AW

AR

AW

AR

AW

AR

AW

AR

AW

AR

AW

AR

WriteTransactionArbiter

ReadTransactionArbiter

Router

Router


2-12 : X12053

InterconnectMaster 0

Master 1

Master 2

Slave 0

Slave 1

Slave 2

W

R

W

R

W

R

W

R

W

R

W

R

Write Data Crossbar

Read Data Crossbar



2 : IP AXI

SI () 1 SI MI AXI

N M ( ) N M 2-13 AXI 1 Outstanding

() AXI

AXI 32 64 128 256 512 1024 AXI C_INTERCONNECT_DATA_WIDTH AXI

SI MI AXI AXI

SI MI () () SI (SI AXI ) MI (AXI MI )

MI SI AXI MI SI

SI AXI SI


2-13 :



AXI IP

AXI MI MI

SI AXI SI

AXI MI MI

AXI

AXI ( )

SI MI MI MI

AXI (SI ) RRESP DECERR SLVERR OKAY EXOKAY

MI ( )

SI AW/ARCACHE[1] () (INCR WRAP ) MI

AXI RRESP (SI ) RRESP

(SI) (MI) N:1

(SI) (MI) 1:N



2 : IP AXI

FIFO

5 AXI

MI SI AXI AXI MI SI AXI

AXI SI MI MI

AXI SI MI AXI

2 ( ) SI MI 5 AXI

SI MI 1

SI MI

FIFO AXI SI MI AXI

SI SI FIFO

MI MI FIFO

MI MI MI FIFO

SI SI SI FIFO



AXI IP

FIFO AXI FIFO AXI

AXI IP AXI IP (DS768)

AXI AXI AXI AXI-to-AXI IP (axi2axi_connector) axi2axi_connector IP AXI

AXI-To-AXI axi2axi_connector

1 AXI AXI

EDK

axi2axi_connector ( ) AXI ( ) AXI ( ) 1 AXI ( ) AXI ( 2-14 )

http://japan.xilinx.comhttp://japan.xilinx.com/support/documentation/ip_documentation/axi_interconnect/v1_03_a/j_ds768_axi_interconnect.pdfhttp://japan.xilinx.com/support/documentation/ip_documentation/axi_interconnect/v1_03_a/j_ds768_axi_interconnect.pdf


2 : IP AXI


2-14 : 2 AXI

mb_0

AXI_Interconnect_0

AXI_Interconnect_1

AXI_Interconnect_2

slave_2

axi2axi_connector

slave_1

slave_3

M_AXI_IP

M_AXI_DP

M_AXI_IC

M_AXI_DC

X12036



AXI IP

AXI-To-AXI AXI-To-AXI (axi2axi_connector) 2 AXI axi2axi_connector IP EDK

EDK axi2axi_connector

AXI To AXI AXI To AXIConnector IP (DS803)

EDK pcore AXI IP ( HDL ) EDK AXI AXI pcore AXI EDK

AXI AXI IP

AXI AXI

I/O

2-15 AXI X-Ref Target - Figure 2-15

2-15 : EDK

Individual AXI Ports madeexternal to sub-system

interface

Microblaze

EDK sub-system

Axi_ext_master_conn

ICAXI

DCAXI

S_AXI

M_AXI

Memory controllerAxi_interconnect

X12040

http://japan.xilinx.comhttp://www.xilinx.com/cgi-bin/SW_Docs_Redirect/sw_docs_redirect?locale=en&topic=ip+documentation&sub=ds803_axi_to_axi_interconnect.pdfhttp://www.xilinx.com/cgi-bin/SW_Docs_Redirect/sw_docs_redirect?locale=en&topic=ip+documentation&sub=ds803_axi_to_axi_interconnect.pdf


2 : IP AXI

2-16

Platform Studio IP

http://japan.xilinx.com/ipcenter/axi4.htm


2-16 : EDK

Microblaze

Axi_interconnect

ICAXI S_AXI Memory controller

DCAXI

EDK sub-system

Individual AXI Ports made external to sub-system

interface

Axi_gpio

Axi_ext_slave_conn

S_AXI

S_AXI

X12075

http://japan.xilinx.comhttp://japan.xilinx.com/ipcenter/axi4.htm


AXI IP

Centralized DMA ( DMA) AXI DMA PLBv4.6 DMA AXI4 2-17 AXI (AXI4 AXI4-Lite) DMA

AXI4 DMA AXI4


2-17 : AXI DMA

AXI CDMA

CPU(AXI

MicroBlaze)

AXI4 MMap Interconnect(AXI4-Lite)

AXI BRAM

AXI DDRx

Registers

Scatter Gather Engine

AXI4

AXI4

AXI4 Read

AXI4 Write

AXI4-Lite

AXI4

AXI IntcAXI4-Lite

AXI4-Lite

AXI4 MMap Interconnect

(AXI4)

DP

DC

IC

AXI4

AXI4

Interrupt

Interrupts In

Interrupt Out(To AXI Intc)

AXI4-Stream

AXI4-Stream

DataMover

X12037



2 : IP AXI

AXI DMA AXI DMA PLBv4.6 DMA CPU 1 DMA DMA

AXI DMA 32 64

AXI DMA AXI DMA PLBv4.6 DMA (SG)

SG CPU DMA SG ( ) CPU DMA SG AXI4 AXI4

DMA DMA CPU AXI DMA SG

AXI DMA AXI DataMover AXI4-Stream AXI4 AXI DMA DataMover SG AXI DMA SG

DMA AXI4 DMA FPGA FPGA

DataMover Lite ( (DRE) SG )

/

DRE / (DRE 32 64 )

(32 64 128 256 )

DataMover AXI4



AXI IP

DMA AXI4 AXI4 DMA 4 DMA DataMover

DMA AXI4 DMA ( ) AXI4 IP

36 2-18 AXI DMA

2-1 : AXI DMA AXI4

AXI

AXI4-Lite

32AXI DMA AXI DMA

AXI4 32

AXI DMA DMA

AXI4

MMap AXI4

32 64128 256

3264128 256

MMap AXI4

32 64128 256

32 64128256



2 : IP AXI

2-19 AXI


2-18 : AXI DMA

AXI DMA

S2MM DMA Controller

MM2S DMA Controller

AXI DataMoverA

XI L

ite S

lave

Inte

rfac

e

MM2S_IntrOut

S2MM_IntrOut

ResetModule

Register Module

MM2S_DMACRMM2S_DMASR

MM2S_CURDESC

ReservedMM2S_TAILDESC

Reserved

S2MM_DMACRS2MM_DMASR

S2MM_CURDESC

ReservedS2MM_TAILDESC

Reserved

AX

I Con

trol

Inte

rfac

eA

XI S

tatu

sIn

terfa

ce

SG Engine(Interrupt Coalescing)

SG Interface

AXI Memory Map Read (MM2S)

AXI Memory Map Write (S2MM)

AXI Control Stream (MM2S)

AXI Status Stream (S2MM)

AXI Stream (MM2S)

AXI Stream (S2MM)

AXI Lite

AXI Memory Map SG Read / Write

SG Interface

X12038


2-19 : AXI DMA AXI4

CPU(AXI

MicroBlaze)


AXI Ethernet

AXI BRAM

AXI DDRx

Registers

AXI DMA

Scatter Gather Engine

DataMover

Ethernet Control

and Status

Registers

AXI4-Lite

AXI4-Stream

AXI4-Stream

AXI4-Stream

AXI4-Stream

Tx Payload

Rx Payload

Tx Control

Rx Status

AXI Intc


DP

DC

IC

AXI4

Interrupt

Interrupts In



AXI4-Stream

AXI4-Stream

AVB

Ethernet Tx

Ethernet Rx

MIIM

AXI4-LiteAXI4-Lite

AXI4-Lite

AXI4

AXI4

AXI4

AXI4

AXI4 Read

AXI4 Write

X12039



AXI IP

36 2-19 AXI AXI DMA IP AXI DMA PLBv4.6 (MPMC) PLBv4.6 SDMA

AXI DMA AXI AXI4-Stream AXI4

AXI4 DMA AXI DMA AXI4-Stream DMA (SG) CPU

AXI DMA SG AXI DataMover ( ) AXI4-Stream AXI4

AXI DMA (MM2S) (S2MM) AXI4-Stream

MM2S AXI AXI DMA SG

S2MM AXI SG AXI4 IP

AXI AXI4 AXI4

SG AXI DMA 4



2 : IP AXI

DMA AXI4 AXI4 DMA AXI DMA 8 AXI4

2-2 : AXI DMA

AXI

AXI4-Lite

32 AXI DMA AXI DMA

AXI4 32 AXI4 DMA DMA

AXI4

MM AXI4

32 64128 256

DMA

MM AXI4

32 64128 256

DMA DMA

AXI4-Stream

32 64128 256

MM AXI4-Stream IP

AXI4-Stream

32 64128 256

AXI4-Stream IP MM

AXI4-Stream

32 Tx IP

AXI4-Stream

32 IP Rx



AXI IP

DMAAXI4 DMA (VDMA) DMA

2-20 AXI4 VDMA

40 2-21 AXI VDMA


2-20 : AXI VDMA

AXI VDMA

S2MM DMA Controller

MM2S DMA Controller

AXI DataMover

AX

I Lite

Sla

ve In

terfa

ce

MM2S_IntrOut

S2MM_IntrOut

ResetModule

Register ModuleMM2S_DMACRMM2S_DMASR

MM2S_CURDESC

S2MM_DMACRS2MM_DMASR

S2MM_CURDESCReserved

SG Engine(Interrupt Coalescing )

AXI Memory Map Read (MM2S)

AXI Memory Map Write (S2MM)

AXI MM2S Stream

AXI S2MM Stream

AXI Lite

AXI Memory Map SG Read

MM2S Gen-Lock

MM2S FSync

S2MM Gen-Lock

S2MM FSync

MM2S_TAILDESCReserved

S2MM_TAILDESCReserved

MM2S Frame Size

MM2S Stride

MM2S Strt Addr 0

MM2S Strt Addr N:

MM2S Frame Size

MM2S Stride

MM2S Strt Addr 0

MM2S Strt Addr N:

MM2S Frame Size

MM2S Stride

MM2S Strt Addr 0

MM2S Strt Addr N:

MM2S Frame Size

MM2S Stride

MM2S Strt Addr 0

MM2S Strt Addr N:

axi_resetn

m_axis_mm2s_aresetns_axis_s2mm_aresetn

Line Buffer

Line Buffer

MM2S Line Bufffer Status

S2MM Line Bufffer Status

DownSizer

UpSizer

Reserved

x12054



2 : IP AXI

AXI VDMA AXI VDMA AXI4-Stream DMA (SG) CPU AXI VDMA SG AXI DataMover AXI4-Stream AXI4

AXI VDMA 16

VDMA AXI 2 AXI VDMA Gen-Lock

Gen-Lock 1 AXI VDMA AXI VDMA Gen-Lock Gen-Lock

AXI4-Stream 8 256 AXI4-Stream AXI4 AXI VDMA


2-21 : AXI VDMA IP



AXI IP

VDMA AXI4 2-3 AXI VDMA 6 AXI4

IP IP 2 DDRx (SDRAM) AXI

Virtex-6 Spartan-6 (Virtex-6 Spartan-6 (MCB) ) Virtex-6 Spartan-6 AXI

Virtex-6 Spartan-6 2

EDK axi_v6_ddrx axi_s6_ddrx CORE Generator

(MIG)

HDL 2

AXI4

2-3 : AXI VDMA

AXI

AXI4-Lite 32 AXI VDMA AXI VDMA

AXI4 32 AXI VDMA DMA

AXI4

MM AXI4

32 64128 256

DMA

MM AXI4

32 64128 256

DMA DMA

AXI4-Stream 8 16 3264 128

256

MM AXI4-Stream IP

AXI4-Stream 8 16 3264 128

256

AXI4-Stream IP MM



2 : IP AXI

Virtex-6Virtex-6 (MIG) AXI4

EDK AXI4 axi_v6_ddrx

axi_v6_ddrx (HDL) GUI XPS EDK Virtex-6 AXI4-to-UI (AXI4 ) AXI4 (SI) AXI4-to-UI AXI4 MIG Virtex-6 UI Virtex-6

AXI4 UI 4 AXI4 UI

AXI4 AXI4 UI Virtex-6 /

2-22 AXI4 Virtex-6

Spartan-6 Spartan-6 (MCB) Spartan-6 MCB AXI4 (SI)

Spartan-6 AXI4 MCB

2 AXI4 SI MCB


2-22 : Virtex-6

axi_v6_ddrx (EDK) or memc_ui_top (COREGen) top level

DDR2 / DDR3 PHY

Virtex-6 Memory

Controller

AXI4 Slave Interface

BlockDDR2 / DDR3 DFINative

Interface

User Interface

bllock

UI Interface

AXI4 Interface

DDR2 or DDR3

SDRAM external

AXI4 Master



AXI IP

AXI4

16 AXI4 (INCR) MCB 1 1

16 AXI4 16 MCB

MCB WRAP AXI4 WRAP MCB 2 MCB

axi_s6_ddrx CORE Generator Spartan-6 AXI MIG 6 (MCB ) 32 64 128 MCB 2-23 AXISpartan-6

http://japan.xilinx.com/products/design_resources/mem_corner


2-23 : Spartan-6

X12046

axi_s6_ddrx or mcb_ui_top

mcb_raw_wrapper

fpga boundary

MCB

MCB Soft Calibration Logic

AXI4 Master

AXI4 Master

AXI4 Master AXI4 SlaveInterface 5

AXI4 SlaveInterface 1

AXI4 SlaveInterface 0

LPDDR/DDR/DDR2/DDR3

SDRAM

Port 0

Port 1

Port 5

http://japan.xilinx.comhttp://japan.xilinx.com/products/design_resources/mem_cornerhttp://japan.xilinx.com/products/design_resources/mem_corner


2 : IP AXI



3

FPGA AXI AXI IP IP AXI

IP AXI4 AXI4-Lite

IP

3-1 AXI4 AXI4-Lite IP AXI4

3-1 : AXI4 AXI4-Lite

AXI IP

READY/VALID

AXI READY/VALID

AXI4 :

1 256 1 16

IP

/ IP 32 64 128 256 512 1024

AXI4-Lite 32

AXI4

IP AXI

/ /

AXI IP



3 : FPGA AXI

AXI3 vs. AXI4 AXI4 AXI3 AXI

AXI3 AXI4

AXI3 IP

: AXI4

/

IP IP OK

/ IP IP

000

0011

IP

(QoS)

IP QoS IP QoS

REGION AXI / REGION

IP REGION

IP REGION

AXI IP REGION

IP IP

IP

IP 8 VALID 16

AXI 16 AXI ARESETN IP

AXI CSYSREQCSYSACK CACTIVE IP

3-1 : AXI4 AXI4-Lite ()

AXI IP



AXI4-Stream

AXI4-Stream IP AXI4-Stream

AXI4-Stream 3-2 AXI4-Stream

AXI4-Stream AXI4-Stream

IP ( : )

IP 2 DSP

AXI4-Stream

3-2 : AXI4-Stream

TVALID

TREADY TREADY

TDATA

TSTRB IP : TSTRB TKEEP

TKEEP

TLAST

TID IP IP

TDEST IP IP

TUSER



3 : FPGA AXI

N N

N

1

AXI4-Stream TDATA N

N=12 16 TDATA N=20 24 TDATA

AXI AXI IP

( )

( )

TDATA 16 TDATA 64 4 (4 2 ) (1 TDATA ) ( TDATA )

TDATA ()



AXI4-Stream

TLAST 2

3-1 AXI4-Stream

TLAST Low (TLASTA) TLAST

1 ( )

12

16

TDATA 16


3-1 : AXI4-Stream ( )

X12056



3 : FPGA AXI

1 TLAST High (TLASTB) 0 ()

3-2 ()

3-3 AXI4-Stream

re(X) im(X) X


3-2 : ()

X12057

TDATA[15] ... TDATA[12]

1 ( )

12

16

TDATA 16


3-3 : AXI4-Stream

X12058



AXI4-Stream

: TDATA[15:12] 2 1

TDATA 32 3-4 1 1

2 () 2

(FFT)

MAC (FIR) (TDM)

AXI IP

AXI4-Stream

AXI4-Stream


3-4 : 32 TDATA

X12059

4

12

16

TDATA 16



3 : FPGA AXI

AXI4-Stream 3-5

32 TDATA ( 3-6 )

TDATA 64 ( 3-7 )


3-5 : X12060


3-6 : AXI4-Stream X12061


3-7 : 64 TDATA

x12062



AXI4-Stream

TDATA 128 3-8

AXI4-Stream

AXI4-Stream TLAST TLAST IP IP 3

IP TLAST

TLAST TLAST (CRC) CRC TLAST CRC


3-8 : 128 TDATA

X12063



3 : FPGA AXI

TLAST FFT TLAST

( : N FFT N-1 )

IP TLAST TLASTAXI TLAST

FIR N FFT FIR N TLAST FFT TLAST FFT TLAST

TKEEP TDATA () IP TKEEP TKEEP ( AXI4-Stream v1.0 ) TLAST

TKEEP AXI4-Stream

AXI4-Stream TKEEP TKEEP

AXI IP TKEEP IP

TKEEP TLAST = 1

AXI IP TKEEP TKEEP IP TLAST TKEEP IP IP AXI4-Stream TKEEP

IP ( ) TKEEP TKEEP



AXI4-Stream

AXI4-Stream TUSER

AXI4-Stream TUSER TDATA TUSER IP TUSER TDATA TUSER TDATA

FFT TDATA TUSER TUSER TDATA

( )

VALID AXI4-Stream OOB (Out-Of-Band)

GPIO

I/O

LED ChipScope Pro Analyzer



3 : FPGA AXI

:

TLAST TLAST TLAST 2

TLAST : TLAST TLAST : TLAST

CPU FFT DMA

DMA FFT TLAST

FFT DMA FFT N DMA N

FFT TLAST

DMA 1

CPU FFT CPU

1 1 DMA FFT 32 CPU 64 1 DMA DMA 64 2048 1 DMA 1 TLAST FFT 63 TLAST

TLAST TLAST FFT DMA



DSP IP AXI

1

DMA FFT TLAST CPU DMA FFT TLAST

FFT TLAST TLAST

DSP IP AXI AXI4-Stream

2 FFT ()

1 1 1



3 : FPGA AXI

: TREADY TREADY



4

AXI

I/O AXI

MicroBlaze (PowerPC PLB ) (ARM AXI ) 70 IP CORE Generator

IP AXI IP

PLBv4.6 IP : IP 3

IP

Create and Import Peripheral Wizard IP

PLBv4.6 IP

IP 45 IP ARM ARM AMBAAXI Protocol v2.0 Specification IP AXI

Create and Import Peripheral (CIP) Wizard IP http://japan.xilinx.com/support/answers/37425.htm AXI

IP AXI-To-PLB AXI-To-PLB

IP ( IP Foundation IP ) : IP IP PCIe I/O IP

DSP IP : IP

http://japan.xilinx.comhttp://japan.xilinx.com/support/answers/37425.htm


4 : AXI

Local-Link : Local-Link FIFO 62 Local-Link AXI4-Stream

AXI-To-PLB PLBv4.6 IP AXI-To-PLB IP AXI

AXI4 (PLBv4.6) AXI4 PLBv4.6 AXI4 32 64 PLBv4.6 32 64

AXI (AXI4 AXI4-Lite) PLBv4.6 IP

AXI4 AXI4-Lite PLB v.46 ( )

: AXI:PLB=1:1

AXI PLB : 32

AXI PLB : 32 64 (AXI:PLB=1:1)

AXI4 AXI4 (SI)

AXI4

(AXI4-Lite)

/

1 256 INCR FIXED 1 16 WRAP 2 4 8 16

/

/ ( 2)

/



AXI-To-PLB

PLBv4.6 PLBv4.6 (MI)

/ ( 2)

PLBv4.6

1 4 8

2 16

4 8

1 1

/

32 64 128 PLBv4.6

AXI-To-PLBv4.6 4-1 AXI-To-PLBv4.6

PORT-2 C_EN_DEBUG_REG=1 C_S_AXI_PROTOCOL=AXI4C_S_AXI_SUPPORTS_WRITE=1

AXI 32 64 PLBv4.6 32 64 ( : C_MPLB_NATIVE_DWIDTH= 32/64)AXI-To-PLBv4.6 PLBv4.6 32 64 128

AXI AXI (SI) PLBv4.6 PLBv4.6

(C_S_AXI_PROTOCOL=AXI4 ) AXI PLBv4.6 AXI ( ) PLBv4.6 PLB


4-1 : AXI-To-PLBv4.6

PORT 1

PORT 2

AXI4

Registers

PLB

v46

AXI PLBv46 Bridge

AXI4 Lite

Invalid if (C_BRIDGE_AXI_PROTOCOL=axi4lite)

OR (C_S0_AXI_SUPPORTS_WRITE=0) OR (C_S0_AXI_DEBUG_REGISTER_EN=0)

Valid only when (C_BRIDGE_AXI_PROTOCOL=axi4)

Valid only when (C_BRIDGE_AXI_PROTOCOL=axi4lite)

AXI4-PLBv46 Bridge

Bridge Logic

AXILite-PLBv46 Bridge

X12064



4 : AXI

PLBv4.6 AXI

(16) PLB 2 32x32/64x32

AXI PLB /

Local-Link AXI4-Stream Local-Link IP Low AXI4-Stream AXI4-Stream

Local-Link AXI4-Stream Local-Link AXI4-Stream

ARESETN IP

4-1 : Local-Link

AXI4-Stream

CLK :

ACLK

RST_N :

ARESETN ( )

DATA :

TDATA

SRC_RDY_N Ready :

TVAILD

DST_RDY_N Ready :

TREADY

SOF_N :

EOF_N :

TLAST

CLK :

ACLK



Local-Link AXI4-Stream

AXI4-Stream TDATA Local-Link DATA Local-Link AXI4-Stream TDATA

Ready Low High TVALID TREADY : TREADY

EOF_N Low TLAST

SOF_N AXI4-Stream TLAST ( )

TUSER

4-2 Local-Link

(SRC_RDY_N DST_RDY_N) SOF_N EOF_N

4-3 AXI4-Stream Local-Link SOF


4-2 : Local-Link

CLK

SOF_N

EOF_N

SRC_RDY_N

DST_RDY_N

DATA[63:0]

X12043

P0 P2 P3 P4 P5P1


4-3 : AXI4-Stream

ACLK

TLAST

TVALID

TREADY

TDATA P0 P1 P2 P3 P4 P5X12042



4 : AXI

Local-Link AXI4-Stream 4-2 Local-Link AXI4-Stream

TUSER

Local-Link SOP_N EOP_N SOF/EOF TUSER

REM AXI4-Stream TLAST = 1 TKEEP

SRC_DSC_N TUSER TLAST

AXI4-Stream TUSER AXI4-Stream AXI4-Stream

CH ID (TID) TUSER

4-2 : Local-Link AXI4-Stream

AXI

SOP_N :

TUSER

EOP_N :

TUSER

REM :

TKEEP

SRC_DSC_N :

TUSER

DST_DSC_N :

CH : ID

TID

PARITY :

TUSER



IP System Generator

Local-Link IP Local-Link

High AXI4-Stream High (ARESETN )

Local-Link Local-Link

TUSER TUSER AXI4-Stream

AXI4-Stream AXI4-Stream TVALID TUSER

Local-Link Local-Link

http://japan.xilinx.com/products/design_resources/conn_central/locallink_member/sp06.pdf

IP System Generator DSP PLBv4.6 IP System Generator

System Generator for DSP IP AXI AXI IP System Generator for DSP

IP

System Generator AXI IP High AXI IP System Generator Low aresetn AXI AXI IP 1 System Generator Inverter

aresetn Low 2 aresetn aclken

System Generator AXI IP AXI IP High System Generator AXI IP High aclken

TDATAAXI 1 TDATA CORE Generator DSP IP System Generator TDATA

http://japan.xilinx.comhttp://japan.xilinx.com/products/design_resources/conn_central/locallink_member/sp06.pdf


4 : AXI

4-4 AXI Complex Multiplier

AXI AXI IP 3.1 ( AXI) 4.0 (AXI) AXI 4-5


4-4 : AXI Complex Multiplier


4-5 :



FSL ( ) AXI4-Stream

System Generator AXI IP AXI IP AXI IP GUI maximum performance -1 AXI IP Automatic Manual

Automatic maximum performance -1

AXI Minimum Latency AXI

System Generator AXI AXI IP AXI IP (MSB) (LSB) AXI IP () 2 AXI AXI IP

System Generator PLBv4.6 System Generator PLBv4.6 13 2-1 (pcore) EDK AXI4

[Bus Type] MicroBlaze System Generator System Generator AXI4 MicroBlaze XPS

FSL ( ) AXI4-Stream FSL ( ) AXI4-Stream

FSL AXI4-Stream

FSL AXI4-Stream

FSL FSL AXI4-Stream

FSL AXI4-Stream 4-3 AXI4-Stream

4-3 : AXI4-Stream

AXI

FSL_M_Clk M_AXIS_ACLK

FSL_M_Write M_AXIS_TVALID

FSL_M_Full M_AXIS_TREADY



4 : AXI

FSL AXI4-Stream 4-4 FSL AXI4-Stream

FSL AXI4-Stream

AXI_M_TVALID AXI_TREADY AXI_TREADY AXI4-Stream

FSL FSL_Full FSL_Exists ( )

FSL FSL FSL_Full

AXI4-Stream AXI_S_TREADY

MicroBlaze FSL FSL AXI4-Stream MicroBlaze AXI4-Stream 32 (DFF)

MicroBlaze put fsl DFF MicroBlaze AXI4-Stream AXI4-Stream DFF AXI4-Stream AXI4-Stream TREADY/TVALID FSL DFF AXI_S_TREADY 32 DFF FSL AXI4-Stream FSL AXI4-Stream

MicroBlaze AXI AXI4 FSL

FSL_M_Data M_AXIS_TDATA

FSL_M_Control M_AXIS_TLAST

4-3 : AXI4-Stream ()

AXI

4-4 : FSL AXI4-Stream

AXI

FSL_S_Clk S_AXIS_ACLK

FSL_S_Write S_AXIS_TVALID

FSL_S_Full S_AXIS_TREADY

FSL_S_Data S_AXIS_TDATA

FSL_S_Control S_AXIS_TLAST



DSP IP AXI4-Stream HDL

MicroBlaze (C_STREAM_INTERCONNECT) AXI4-Stream FSL

DSP IP AXI4-Stream HDL DSP IP AXI4-stream FFT DSP DSP IP DSP IP (TDM) 1 TDM

AXI4-Stream DSP IP HDL

DSP IP

IP CORE Generator

AXI4-Stream

DSP IP IP IP IP IP AXI4-Stream


4-6 : IP



4 : AXI

CORE Generator CORE Generator demo_tb DSP IP AXI4-stream VHDL

CORE Generator 1 VHDL demo_tb/tb_.vhd AXI4-Stream IP

demo_tb

IP CORE Generator CORE Generator XCO FIR Compiler v6.0Fast Fourier Transform v8.0 DDS Compiler v5.0 Complex Multiplier v4.0 DSP IP XCO CORE Generator

:

AXI4-Stream XCO CORE Generator /tmp


4-7 : demo_tb


4-8 : CORE Generator



DSP IP AXI4-Stream HDL

AXI4-Stream

DSP IP AXI4-Stream IP Latency Changes Instructions for Minimum Change Migration

AXI4-Stream DSP IP

: DSP IP AXI4-Stream aresetn Low 2 aclken IP 1 High SCLR 2 Low

TDATA : AXI TDATA IP GUI IP TDATA IP TDATA TDATA TDATA



4 : AXI

AXI ()MicroBlaze PLBv4.6 AXI

AXI4 (SDK) IDE MicroBlaze

SDK -mlittle-endian MicroBlaze GNU

LibgenXMD AXI IP MicroBlaze v8.00.a CPU

Xilinx Platform Studio IDE AXI SDK

MicroBlaze


4-9 : TDATA



( SDK ) API OS

MicroBlaze

1.

2. MicroBlaze PLBv4.6

a. XPS AXI SDK

b. SDK AXI

c.

d. GNU makefile mlittle-endian

3. MicroBlaze

a. (.o)

b.

c. ELF ()

d. ( ELF RAM BIT )

e. RAM

f. ( )

g. MicroBlaze



4 : AXI

h. ( )

MicroBlaze MicroBlaze (UG081)

MicroBlaze C_ENDIANNESS MicroBlaze LHUR LWR SHR SWR

4-5 75 4-7 4-5 :

n n+1 n+2 n+3

/

n n+1 n+2 n+3

n+3 n+2 n+1 n

n+3 n+2 n+1 n

/

n+3 n+2 n+1 n

n n+1 n+2 n+3

0 31

/

4-6 :

n n+1

/

n n+1

n+1 n

n+1 n

/

n+1 n

n n+1

http://japan.xilinx.comhttp://www.xilinx.com/support/documentation/sw_manuals/xilinx13_2/mb_ref_guide.pdfhttp://www.xilinx.com/support/documentation/sw_manuals/xilinx13_2/mb_ref_guide.pdf


(Cadence Design Systems ARM Mentor Graphics Synopsys ) AXI

0 15

/

4-7 :

n

0 7

/

4-6 : ()



4 : AXI



5

AXI AXI IP IP IP Fmax IP AXI Spartan Artix Virtex

AXI IP

IP

78 5-1 80 5-2 AXI IP

(++) (+) (0) (-) (--) IP

AXI AXI IP (DS768)XPS

http://japan.xilinx.comhttp://japan.xilinx.com/support/documentation/ip_documentation/axi_interconnect/v1_03_a/j_ds768_axi_interconnect.pdfhttp://japan.xilinx.com/support/documentation/ip_documentation/axi_interconnect/v1_03_a/j_ds768_axi_interconnect.pdf

5 : AXI

78 japan.xilinx.com UG761 (v 13.2) 2011 7 6

5-1 : AXI

/

/Fm

ax

/

( = OFF)

- + 0 - + 0 ( UCF AXI TCL )

-- + 0 -- ++ 0 32 FIFO

( = OFF)

-- -- -- - + 0 ID ID -- - - - + 0

AXI4 ( = OFF)

AXI4-Lite 0 0 -- 0 + ++ AXI3 ID ID AXI3 AXI4 AXI3 16

AXI3 - - - - 0 0

++ 0 -- 0 + ++

- ( )

0 + + 0 0 0

- -- - + 0 0 0

ID

+ + 0 0 + + ID (SASD)

0 0 + 0 0 -

/ 1 ( ) + + - 0 + +

2 4 8 16 32 - 0 + - 0 -

: ++ = + = 0 = - = -- =

www.xilinx.com

5 : AXI


32 ( ) + + - 0 0 0

64 128 256 512 1024 -- - ++ 0 0 0

( = OFF)

7 ( ) - ++ - - + 0 AXI 8 8

1 ( ) -- ++ 0 - + 0

8 ( ) - ++ 0 - + 0

( = OFF)

IP ( )

0 + 0 0 -- 0

FIFO ( = OFF)

SRL - 0 + - 0 0 SRL FIFO 32

BRAM -- 0 ++ - 0 0 BRAM FIFO 512

( = )

0 0 0 + - 0 0

0

AXI ChipScope ( = OFF)

ON - - 0 0 0 ++

AXI ( = OFF)

ON - - 0 0 0 ++

5-1 : AXI ()

/

/Fm

ax

/

: ++ = + = 0 = - = -- =

www.xilinx.com

5 : AXI


5-2 : AXI IP

/

/Fm

ax

/

IP AXI4-Lite ++ 0 - 0 + ++ AXI AXI4

AXI3 AXI4 0 0 0 0 0 0

ON ( ) -- - - - 0 0 AXI IP OFF ON AXI IP OFF OFF ( ) 0 0 0 0 0 0

+ + 0 0 + + AXI AXI

0 0 + 0 0 -

1 + + - 0 + +

> 1 32 - 0 + 0 0 0

32 + + - 0 0 0

64 128 256512 1024

-- - ++ 0 0 0

AXI4 (1 4) 0 0 - + 0 0

( 256) 0 0 ++ -- 0 0

: ++ = + = 0 = - = -- =

www.xilinx.com


AXI

AXI

/ AXI IP

1.

2. AXI (SASD)

AXI / SASD 1 Outstanding () 1 SASD

3. AXI IP

AXI

4. AXI3 AXI4 AXI IP IP ( )

5. AXI4-Lite AXI3 AXI4-Lite AXI AXI4-Lite AXI4-Lite AXI4-Lite IP

6. / IP

7. AXI

AXI IP AXI

AXI IP



5 : AXI

/Fmax 1. AXI

AXI FIFO Generator AXI AXI

2. DDR3 PCIe IP (PAR) IP IP

a. PAR

b. AXI IP AXI AXI

3. / ( / 7 )

4. IP IP IP AXI IP

5. IP IP ( ) IP

/ 1. 82 /Fmax

2.

3. FIFO

4. IP IP

IP



AXI

5.

AXI AXI AXI

6. /

/

7. AXI AXI

8. IP / AXI

IP AXI

1.

2. AXI3 AXI4 AXI

3.

4.



5 : AXI

5.

6. IP /

/

7. AXI DDRx (MIG) / () DRAM

8. AXI

AXI

1.

IP IP

2. /

AXI (SASD) SASD 1

AXI SASD 1

3. AXI4-Lite AXI3 AXI4 IP AXI4-Lite

4. AXI ChipScope AXI IP

5. AXI ChipScope AXI AXI /

6. AXI



AXI4 : AXI4

AXI4 : AXI4

AXI4 MPMC AXI4 (AXI MPMC) AXI AXI ( AXI MIG ) AXI4

85 5-1 N 1 AXI MIG AXI

AXI AXI AXI MIG IP Fmax AXI MPMC AXI MPMC

AXI MPMC 1 AXI MIG 8 16 32 64 128 -1 Virtex-6 300 400MHz ( MIG ) 600 800MHz 4 AXI 32 48MHz AXI4 100MB/sec 100MB/sec 4 2 100MB/sec = 800MB/sec 85 5-3


5-1 : AXI4 MPMC

5-3 :

DDR3 ( )

(MHz)

(MHz)

(MB/sec)

8 300 600 600

8 400 800 800



5 : AXI

2 16 DDR3 300 400MHz 1200 1600MB/sec ( 800MB/sec 67% 50%) 400MHz 8 DDR3 / / ( ) AXI MIG AXI 4 AXI 1/2 300 400MHz 16 DDR3 150 200MHz 64 AXI

AXI AXI 150 200MHz 64 AXI

AXI AXI 48MHz 32 32 64 200MHz AXI 48MHz AXI

200MHz

48MHz AXI

48 4 = 192MHz AXI

192 2 = 384MHz

: 48 192 384MHz MMCM (MixedMode Clock Manager)

16 300 600 1200

16 400 800 1600

32 300 600 2400

32 400 800 3200

64 300 600 4800

64 400 800 6400

128 300 600 9600

5-3 : ()

DDR3 ( )

(MHz)

(MHz)

(MB/sec)



AXI4 : AXI4

5-2

AXI4 AXI4 AXI4 AXI4 256

/ /

FIFO

AXI4 AXI AXI

AXI 32 (AxSIZE = 0x2) AXI (AxCACHE[3]=1)

XPS C_SUPPORTS_NARROW AXI MIG CORE Generator AXI MIG


5-2 : AXI



5 : AXI

AXI4

AXI4 ( C_SUPPORTS_THREADS=0 ) AXI4

AXI AXI ID AXI4 AXI

ChipScope AXI

AXI AXI MIG AXI AXI AXI 2

AXI AXI FIFO

5-3 AXI


5-3 : AXI :

AXI Interconnect

SlaveInterface

MasterInterface

SI Hemisphere MI Hemisphere

Crossbar

Master 0 Slave 0

Slave 1Master 1 Reg

iste

r S

lices

Reg

iste

r S

lices

Up-

size

rs

Up-

size

rs

Clo

ck C

onve

rter

s

Dow

n-si

zers

Dat

a F

IFO

s

Clo

ck C

onve

rter

s

Dow

n-si

zers

Pro

toco

l Con

vert

ers

Dat

a F

IFO

s

X12047



AXI4 : AXI4

AXI 88 5-3 FIFO

AXI (1/2 1/4 ) FIFO FIFO AXI FIFO AXI AXI FIFO 32 512 AXI4 256 FIFO 512

AXI AXI AXI 5 8 AXI AXI AXI AXI 48MHz 48MHz 192MHz

/

AXI

AXI 1 1 2

FIFO Outstanding FIFO 64 512

32 1024 AXI4 256 AXI FIFO 4

AXI 1 2 4 8 16 32 AXI 2 4

4 2 2 8

8 4 16

4 1 2



5 : AXI

AXI MPMC AXI MPMC AXI

/ 4 8 / /

10MB/sec 100MB/sec

AXI

/

: MicroBlaze 128 256 512 AXI AXI 1 MicroBlaze

( )



AXI4 : AXI4

AXI MPMC

AXI MPMC

AXI MPMC

AXI AXI (SASD)

SASD AXI 1

SASD AXI SASD IP

AXI IP AXI MPMC 1 IP N 1 AXI AXI 1

FIFO

IP 2 AXI 1 AXI MPMC

AXI AXI MPMC 32 128 AXI

: XPS AXI 2 AXI-to-AXI IP IP XPS



5 : AXI

AXI ChipScope AXI

XPS AXI ChipScope AXI AXI ChipScope

AXI ChipScope AXI AXI ChipScope AXI

AXI AXI IP FPGA AXI IP

: AXI FIFO AXI

Cadence XPS AXI (BFM) AXI AXI IP XPS Cadence

BFM BFM IP AXI

AXI IP AXI (UG783) AXI (DS824)

AXI MPMC AXI 2

400MHz 16 DDR3 200MHz 64 AXI 300MHz 32 DDR3 150MHz 128 AXI

AXI 200MHz 150MHz



AXI4 : AXI4

FPGA

SASD ( )

( )

FIFO/

: AXI AXI



5 : AXI

AXI AXI

AXI Virtex-6 MIG 8 16 32 64 128 DDR3 AXI 4 32 64 128 256 512

32 AXI4-Lite 64 DDR3 AXI MIG AXIMIG 256 32 AXI 256 AXI

AXI MIG 64 DDR3 DIMM ML605 64 DDR3 DIMM AXIMIG MicroBlaze

AXI AXI

AXI 5 5 100MHz 64 AXI 100MHz 64 75MHz 32 64:32 32:64 10 10

64 AXI AXI 32

XPS XPS

AXI



AXI

AXI

AXI

AXI4-Lite IP

AXI4-Lite IP

AXI4-Lite IP SASD AXI AXI AXI4-Lite IP AXI4-Lite SASD AXI4-Lite

1 7

7 AXI4-Lite AXI AW AR B

1 R W

8 AXI 1 7 8

IP AXI4

AXI

AXI AXI IP



5 : AXI

IP BFM

IP AXI (XPS Cadence BFM ) AXI / (Cadence ARM )

AXI

AXI IP (PAR) AXI ChipScope AXI4

AXI IP

AXI IP AXI

SASD (/ 1 ) ( FIFO )

AXI ChipScope

BSB (Base System Builder) AXI BSB AXI IP

BSB

BSB AXI 81 AXI BSB

AXI IP IBM CoreConnect/ MPMC AXI BSB CoreConnect/MPMC BSB BSB CoreConnect/MPMC AXI BSB



A

AXI AXI4 AXI-Lite AXI4-Stream IP AXI (www.amba.com )

AXI4 AXI4-Lite

A-1 AXI

A-1 : AXI

AXI4 AXI4-Lite

ACLK

ARESETN Low IP () IP 8 VALID 16

http://japan.xilinx.comwww.amba.com


A : AXI

AXI4 AXI4-Lite A-2

:

A-2 :

AXI4 AXI4-Lite

AWID

ID ()

ID AXI

AWADDR

32 ()

: EDK 32

AWLEN

:

(INCR) 256 (WRAP) 16

AWSIZE 8 1024

AWSIZE

AWBURST INCR WRAP FIXED FIXED FIXED INCR

AWLOCK IP

IP

AWCACHE 0011

IP () ()

IP

AWPROT 000

IP () ()

IP



AXI4 AXI4-Lite

AXI4 AXI4-Lite A-3

:

AWQOS IP

IP QoS

AWREGION IP

IP

AXI

AWUSER IP

IP

AWVALID

AWREADY

A-2 : ()

AXI4 AXI4-Lite

A-3 :

AXI4 AXI4-Lite

WDATA 32 1024 32

AXI4-Lite 64

WSTRB WSTRB ( )

WLAST

WUSER IP

IP

WVALID

WREADY



A : AXI

AXI4 AXI4-Lite A-4

:

AXI4 AXI4-Lite A-5

:

A-4 :

AXI4 AXI4-Lite

BID

AWID

BRESP EXOKAY BUSER IP

IP

BVALID

BREADY

A-5 :

AXI4 AXI4-Lite

ARID

ID ()

ID AXI

ARADDR

32 ()

: EDK 32

ARLEN INCR WRAP FIXED FIXED FIXED INCR



AXI4 AXI4-Lite

ARSIZE 8 1024

ARSIZE

ARBURST INCR WRAP FIXED FIXED FIXED INCR

ARLOCK IP

IP

ARCACHE 0011

IP () ()

IP

ARPROT 000

IP () ()

IP

ARQOS IP

IP QoS

ARREGION IP

IP

AXI

ARUSER IP

IP

ARVALID

ARREADY

A-5 : ()

AXI4 AXI4-Lite



A : AXI

AXI4 AXI4-Lite A-6

:

A-6 :

AXI4 AXI4-Lite

RID

ARID

RDATA 32 1024 32

AXI4-Lite 64

RRESP EXOKAY RLAST

RUSER IP

IP

RVALID

RREADY



AXI4-Stream

AXI4-Stream AXI4-Stream A-7

A-7 : AXI4-Stream

( )

TVALID N/A

TREADY 1

TDATA 0

AXI IP : 8 4096 AXI IP ( )

TSTRB TKEEP

1

TSTRB TSTRB

TKEEP 1 IP

IP TKEEP

TLAST 0

TLAST TID 0

AXI IP : 1 32 AXI IP ( )

TDEST 0

AXI IP : 1 32 AXI IP ( )

TUSER 0

AXI IP : 1 4096 AXI IP ( )



A : AXI



B

AXI B-1 : AXI

AXI AXI

AXI4

256

: MIG RAMEDKPCIe FIFO

AXI4-Lite

32 1

: UART Lite IIC

AXI4-Stream

DSP

AXI4

AXI4-Lite

AXI4-Stream

IP 1

1 IP

AXI4

AXI4-Lite

AXI4-Stream

VALID AXI

()

AXI4-Stream1

DSP

AXI4

AXI4-Lite

/ 1



B : AXI

AXI4

AXI4-Lite

AXI4-Stream

VALID 1

AXI4

AXI4-Lite

AXI4-Stream

AXI4

AXI4-Lite

AXI4-Stream

IP AXI IP IP ( IP 1 )

AXI4

AXI4-Lite

AXI4-Stream

IP IP AXI IP ( IP 1 )

()

AXI4

AXI4-Lite

AXI4-Stream

AXI AXI () IP

()

AXI4

AXI4-Lite

AXI4-Stream

AXI () AXI IP

SIAXI4

AXI4-Lite

AXI

XPS AXI AXI

CORE Generator 1 1

EDK

MIAXI4

AXI4-Lite

AXI

XPS AXI AXI

CORE Generator 1 1

EDK

SI AXI4

AXI4-Lite

: 1 IP 1

EDK

MI AXI4

AXI4-Lite

: 1 IP 1

EDK

B-1 : AXI ()



SI AXI4

AXI4-Lite SI

MI AXI4

AXI4-Lite MI

AXI4

AXI4-Lite

AXI4-Stream

(/ )

AXI4

AXI4-Lite

AXI4-Stream

(/ )

SAMD : AXI

SASD : AXI

1 SASD AXI

EDK

SAMD AXI

AXI SI MI

B-1 : AXI ()



B : AXI



C

ARM AMBA AXI Protocol v2.0 Specification

AMBA4 AXI4-Stream Protocol v1.0

http://www.amba.com ARM AMBA AXI 5

http://japan.xilinx.com/support/documentation/axi_ip_documentation.htm

AXII Interconnect IP (DS768)

AXI-To-AXI Connector IP (DS803)

AXI External Master Connector (DS804)

AXI External Slave Connector (DS805)

AXI (DS824)

AXI (UG783) : http://japan.xilinx.com/support/documentation/sw_manuals/xilinx13_2/ug783_axi_bfm.pdf

MicroBlaze (UG081) : http://japan.xilinx.com/support/documentation/sw_manuals/xilinx13_2/mb_ref_guide.pdf

ISE Design Suite : (UG798) : http://japan.xilinx.com/support/documentation/sw_manuals/xilinx13_2/iil.pdf

ISE Design Suite : (UG631) : http://japan.xilinx.com/support/documentation/sw_manuals/xilinx13_2/irn.pdf

: http://japan.xilinx.com/design

: http://japan.xilinx.com/support/mysupport.htm

: http://japan.xilinx.com/support/documentation

: http://japan.xilinx.com/support/documentation/sw_manuals/glossary

EDK : http://japan.xilinx.com/tools/embedded.htm

CORE Generator : http://japan.xilinx.com/tools/coregen.htm

: http://japan.xilinx.com/products/design_resources/mem_corner System Generator : http://japan.xilinx.com/tools/sysgen.htm

http://japan.xilinx.comhttp://www.amba.comhttp://japan.xilinx.com/support/documentation/axi_ip_documentation.htmhttp://japan.xilinx.com/support/documentation/ip_documentation/axi_interconnect/v1_03_a/j_ds768_axi_interconnect.pdfhttp://www.xilinx.com/cgi-bin/SW_Docs_Redirect/sw_docs_redirect?locale=en&topic=ip+documentation&sub=ug768_axi_interconnect.pdfhttp://www.xilinx.com/cgi-bin/SW_Docs_Redirect/sw_docs_redirect?locale=en&topic=ip+documentation&sub=ds803_axi_to_axi_connector.pdfhttp://www.xilinx.com/cgi-bin/SW_Docs_Redirect/sw_docs_redirect?locale=en&topic=ip+documentation&sub=ds803_axi_interconnect.pdfhttp://www.xilinx.com/cgi-bin/SW_Docs_Redirect/sw_docs_redirect?locale=en&topic=ip+documentation&sub=ds804_axi_ext_master_conn.pdfhttp://www.xilinx.com/cgi-bin/SW_Docs_Redirect/sw_docs_redirect?locale=en&topic=ip+documentation&sub=ds805_axi_ext_slave_conn.pdfhttp://japan.xilinx.com/support/documentation/sw_manuals/xilinx13_2/ug783_axi_bfm.pdfhttp://japan.xilinx.com/support/documentation/sw_manuals/xilinx13_2/ug783_axi_bfm.pdfhttp://japan.xilinx.com/support/documentation/sw_manuals/xilinx13_2/mb_ref_guide.pdfhttp://japan.xilinx.com/support/documentation/sw_manuals/xilinx13_2/mb_ref_guide.pdfhttp://japan.xilinx.com/support/documentation/sw_manuals/xilinx13_2/iil.pdfhttp://japan.xilinx.com/support/documentation/sw_manuals/xilinx13_2/irn.pdfhttp://japan.xilinx.com/designhttp://japan.xilinx.com/support/mysupport.htmhttp://japan.xilinx.com/support/documentationhttp://japan.xilinx.com/support/documentation/sw_manuals/glossary http://japan.xilinx.com/tools/embedded.htmhttp://japan.xilinx.com/tools/coregen.htmhttp://japan.xilinx.com/tools/coregen.htmhttp://japan.xilinx.com/products/design_resources/mem_cornerhttp://japan.xilinx.com/tools/sysgen.htmhttp://japan.xilinx.com/tools/sysgen.htm


C :

Local-Link : http://japan.xilinx.com/products/design_resources/conn_central/locallink_member/sp06.pdf

: http://japan.xilinx.com/products/targeted_design_platforms.htm

: http://japan.xilinx.com/support/answers/37425.htm

http://japan.xilinx.comhttp://japan.xilinx.com/products/design_resources/conn_central/locallink_member/sp06.pdfhttp://japan.xilinx.com/products/design_resources/conn_central/locallink_member/sp06.pdfhttp://japan.xilinx.com/products/targeted_design_platforms.htmhttp://japan.xilinx.com/products/targeted_design_platforms.htmhttp://japan.xilinx.com/products/targeted_design_platforms.htmhttp://japan.xilinx.com/products/targeted_design_platforms.htmhttp://japan.xilinx.com/support/answers/37425.htm

AXI 1 : AXI AXI AXI4

AXI IP IP IPAXI4-Stream AXI4-Stream

AXI

2 : IP AXI AXI : Embedded Edition System EditionProject Navigator IP System Generator : DSP Edition AXI IP : Logic Edition

AXI IP AXI IPAXI Centralized DMA ( DMA) DMA DMA IP

3 : FPGA AXI IP AXI4-Stream AXI4-Stream

DSP IP AXI

4 : AXI IP AXI

AXI-To-PLB AXI4 PLBv4.6 AXI-To-PLBv4.6

Local-Link AXI4-Stream Local-Link AXI4-Stream

IP System Generator System Generator for DSP IP AXI System Generator PLBv4.6

FSL ( ) AXI4-Stream FSL AXI4-Stream FSL AXI4-Stream

DSP IP AXI4-Stream HDL DSP IP IP CORE Generator AXI4-Stream

AXI ()

5 : AXI AXI //Fmax

AXI4 : AXI4 AXI4 MPMC AXI AXI4 AXI AXI MPMC AXI MPMC AXI ChipScope AXI

AXI AXI IP

A : AXI AXI4 AXI4-Lite AXI4 AXI4-Lite AXI4 AXI4-Lite AXI4 AXI4-Lite AXI4 AXI4-Lite AXI4 AXI4-Lite

AXI4-Stream

B : AXI C :

AXI リファレンスガイド (UG761) - ザイリンクス - All …€ŽABMA AXI4-Stream...

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Transcript of AXI リファレンスガイド (UG761) - ザイリンクス - All …€ŽABMA AXI4-Stream...

AXI リファレンス ガイド (UG761) - ザイリンクス - All …€ŽABMA AXI4-Stream...

Documents

Transcript of AXI リファレンス ガイド (UG761) - ザイリンクス - All …€ŽABMA AXI4-Stream...

AXI リファレンスガイド (UG761) - ザイリンクス - All …€ŽABMA AXI4-Stream...

Transcript of AXI リファレンスガイド (UG761) - ザイリンクス - All …€ŽABMA AXI4-Stream...