Automatic Generation of Automatic Generation of Compact Semiconductor Compact Semiconductor

Device Models using Device Models using Paragon and ADMSParagon and ADMS

Vivek Chaudhary, Matt Francis, Wei Zheng, Alan Mantooth, Laurent Lemaitre*

Mixed Signal CAD Laboratory * Freescale SemiconductorDepartment of Electrical Engineering Geneva SwitzerlandUniversity of Arkansas

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OutlineOutline

IntroductionAbstract Model RepresentationXML SchemaModeling MethodologyModel CompilationBSIMSOI ModelConclusion

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IntroductionIntroduction

Semiconductor device modeling is extremely time consumingModel implementation in SPICE-like simulators is cumbersomeDesigners from different scientific backgrounds do not use the same analysis tools or same modeling languages

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Various Levels of AbstractionVarious Levels of Abstraction

Simulator-Specific Code (SPICE, Spectre, etc.)

GUI-based tools(Paragon)

Language IndependentModel Abstraction

Highest level description ofmodel behavior

Support multiple languages

One model supports several simulators

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Model RepresentationModel Representation

XML

VHDL-AMS

Goals for XML format:Simulator independentHigher than HDLsCaptures semiconductor device physics and multi-physics (electro-thermal, etc.)

C/C++ (SPICE, Spectre, Eldo)

HDLs Verilog-AMS

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Why XML?Why XML?

XML:• Superset of HTML, simple/structured format• Lends itself to open source and

standardization• Much XML-based technology already exists

• Example: MathML, used for model expressions, is becoming de facto standard for math on the web

• Extensible• Self-documenting

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XML SchemaXML Schema--DTDDTDModel

InterfacePorts

ParametersBody

BranchesQuantities

Expressions

QuantitiesExpressions

Macro-models

name CDATA #REQUIREDversion CDATA #REQUIRED

>

default CDATA #IMPLIEDname CDATA #REQUIREDnature (real | integer | time) #REQUIREDunit CDATA #REQUIREDtype (instance | process) #REQUIRED

>

message CDATA #REQUIREDtype (note | error | warning) #REQUIRED

>

min CDATA #REQUIREDmax CDATA #REQUIREDexclude_max (yes | no) #IMPLIEDexclude_min (yes | no) #IMPLIED

>

Conditional

Conditional

Symbol

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XML SchemaXML Schema--DTDDTDModel

InterfacePorts

ParametersBody

BranchesQuantities

Expressions

QuantitiesExpressions

Macro-models

Conditional

Conditional

Symbol

name CDATA #REQUIREDmode (in | out | inout) #REQUIREDnature (electrical | mechanical_angular_speed |

mechanical_angular_displacement | mechanical_translational_speed | mechanical_translational_displacement | thermal | optical | magnetic) #REQUIRED

type (terminal | quantity | signal | logic) #REQUIRED>

name CDATA #REQUIRED>

name CDATA #IMPLIED>

name CDATA #REQUIREDnature (through | across) #REQUIREDtype CDATA #IMPLIEDunit CDATA #IMPLIED

>

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XML SchemaXML Schema--DTDDTDModel

InterfacePorts

ParametersBody

BranchesQuantities

Expressions

QuantitiesExpressions

Macro-models

Conditional

Conditional

Symbol

name CDATA #REQUIREDfilename CDATA #REQUIRED

>

name CDATA #REQUIREDvalue CDATA #REQUIRED

>

name CDATA #REQUIRED>

name (pos | neg | CDATA) #REQUIREDmappedto CDATA #REQUIREDtype (port | param) #REQUIRED

>

nature (simultaneous | sequential) #REQUIRED>

type (sequential | simulataneous | conditional) #REQUIRED

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Modeling MethodologyModeling Methodology

Paragon UI

XML

ADMS Model Compiler

Spectre C(CMI Interface)

Verilog-A

MCAST Model Compiler

VHDL-AMS

spice3f5

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Model CompilationModel Compilation

Model compilation is automatic generation of compact semiconductor device models for various SPICE like simulatorsADMS is a freely available model compiler for SPICE-like simulators

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AdvantagesAdvantagesModel development time is dramatically reducedGenerated model is easier to maintain and reuseSame abstract representation of the model can be used by a model compiler to generate low level C/C++ code for different simulators

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LargeLarge--Signal Model of BSIMSOISignal Model of BSIMSOI

Ids + Ic

Ibd

Ibs

Iii

Idgidl

Isgidl

RbpQd

Qb

QeQg

Qjdwg

Qjswg

Qs (overlap)

Qd (overlap)

P

Cs,e

Cs,esw

Cd,e

Cd,esw

BackgatE

Body

(External Body)

(Substrate)

Gate

Drain

Source

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Paragon ImplementationParagon Implementation

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Paragon ImplementationParagon Implementation

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Paragon ImplementationParagon Implementation

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Paragon ImplementationParagon Implementation

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Model Compilation using ADMSModel Compilation using ADMS

Paragon UI

XML

ADMS Model Compiler

Spectre C(CMI Interface)

Verilog-A

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ResultsResults

Duration: about two week to implement and validate the BSIMSOI model in Paragon model and generate C model for Spectre using ADMS.Results for all analyses match exactly with native Spectre model

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DC CharacteristicsDC Characteristics

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Interesting BehaviorInteresting Behavior

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Relative PerformanceRelative PerformanceTransient analysis of a 2 transistor circuit

Vdd

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Relative PerformanceRelative Performance

Model CPU time Time factor

Native Spectre

140ms 1X

Verilog-AMS 33.2s 237X

ADMS 200ms 1.4X

Vdd

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RadhardRadhard OpampOpamp

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DC CurveDC Curve

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Open Loop Frequency ResponseOpen Loop Frequency Response

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ConclusionConclusionModeling methodology described enables the user to quickly and correctly create new compact semiconductor device models for various SPICE and SPICE-like simulators

Model development time is significantly reduced

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ConclusionConclusionTime required to validate and test a new model is also significantly reduced

Higher-level XML description of the model is easy to maintain, reuse and update and this leads to an increased efficiency in the overall model creation process.

Automatic Generation of Compact Semiconductor Device Models using Paragon and ADMSOutlineIntroductionVarious Levels of AbstractionModel RepresentationWhy XML?XML Schema-DTDXML Schema-DTDXML Schema-DTDModeling MethodologyModel CompilationAdvantagesLarge-Signal Model of BSIMSOIParagon ImplementationParagon ImplementationParagon ImplementationParagon ImplementationModel Compilation using ADMSResultsDC CharacteristicsInteresting BehaviorRelative PerformanceRelative PerformanceRadhard OpampDC CurveOpen Loop Frequency ResponseConclusionConclusion